Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27054

1

T1

120

T2

50

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23554

1

T1

120

T2

26

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3500

1

T2

24

T7

14

T13

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21047

1

T1

120

T2

1

T4

20

auto[1]

6007

1

T2

49

T3

1

T5

7

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22998

1

T1

120

T2

27

T3

1

auto[1]

4056

1

T2

23

T5

2

T7

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	272	1			T2	1		T100	1		T140	18
values[0]	6	1			T248	6		-	-		-	-
values[1]	597	1			T5	7		T48	15		T215	35
values[2]	861	1			T2	49		T37	1		T29	4
values[3]	502	1			T36	14		T48	25		T141	2
values[4]	2915	1			T6	20		T14	1		T83	9
values[5]	639	1			T36	10		T29	14		T130	15
values[6]	784	1			T3	1		T8	15		T11	19
values[7]	822	1			T13	6		T29	19		T132	8
values[8]	693	1			T7	14		T13	6		T27	11
values[9]	1205	1			T11	13		T12	26		T37	13
minimum	17758	1			T1	120		T4	20		T5	32

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	644	1			T5	7		T130	13		T48	15
values[1]	756	1			T2	49		T37	1		T29	4
values[2]	588	1			T36	14		T48	25		T141	2
values[3]	3008	1			T6	20		T14	1		T83	9
values[4]	622	1			T12	3		T36	10		T29	14
values[5]	813	1			T3	1		T8	15		T11	19
values[6]	744	1			T7	14		T13	6		T132	1
values[7]	696	1			T13	6		T27	11		T37	23
values[8]	1112	1			T2	1		T11	13		T12	26
values[9]	182	1			T42	15		T213	16		T140	18
minimum	17889	1			T1	120		T4	20		T5	32

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22791

1

T1

120

T2

26

T3

1

auto[1]

4263

1

T2

24

T5

1

T6

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T5	5		T48	9		T131	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T130	1		T215	18		T126	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T2	14		T29	2		T132	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T2	12		T37	1		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T36	14		T48	14		T30	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T141	1		T136	1		T227	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1648	1			T6	20		T14	1		T83	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T48	16		T163	13		T127	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T12	3		T42	8		T216	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T36	10		T29	12		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T3	1		T8	15		T11	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T138	9		T214	1		T217	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T30	1		T148	11		T271	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T7	1		T13	1		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T13	1		T80	1		T163	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T27	8		T37	23		T59	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T2	1		T11	1		T12	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	356	1			T100	1		T31	5		T140	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T182	1		T154	1		T257	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T42	11		T213	16		T140	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17686	1			T1	120		T4	20		T5	32
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T134	1		T217	6		T181	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T5	2		T48	6		T214	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T130	12		T215	17		T126	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T2	11		T29	2		T132	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T2	12		T130	3		T136	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T48	11		T30	13		T126	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T141	1		T136	8		T224	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	982	1			T83	8		T98	21		T99	27
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T48	12		T163	11		T129	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T42	8		T31	1		T135	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T29	2		T259	6		T260	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T11	17		T29	9		T132	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T138	13		T214	11		T140	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T148	10		T181	16		T255	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T7	13		T13	5		T141	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T13	5		T80	1		T163	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T27	3		T125	10		T16	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T11	12		T12	13		T32	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T31	2		T140	11		T15	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T182	2		T154	9		T257	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T42	4		T140	8		T129	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T28	1		T29	2		T59	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T181	12		T248	5		T280	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T2	1		T182	1		T282	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T100	1		T140	10		T152	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T248	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T5	5		T48	9		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T215	18		T134	1		T217	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T2	14		T29	2		T132	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T2	12		T37	1		T130	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T36	14		T48	14		T30	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T141	1		T136	1		T226	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1607	1			T6	20		T14	1		T83	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T163	13		T129	15		T227	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T130	1		T216	11		T31	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T36	10		T29	12		T48	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T3	1		T8	15		T11	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T138	9		T271	1		T165	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T29	10		T132	1		T80	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T13	1		T141	13		T215	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T13	1		T33	14		T187	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T7	1		T27	8		T37	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T11	1		T12	13		T80	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	431	1			T37	13		T42	11		T213	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17645	1			T1	120		T4	20		T5	32
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T182	12		T282	13		T18	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T140	8		T152	11		T253	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T248	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T5	2		T48	6		T214	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T215	17		T126	12		T181	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T2	11		T29	2		T132	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T2	12		T130	15		T136	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T48	11		T30	13		T126	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T141	1		T136	8		T226	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	939	1			T83	8		T98	21		T99	27
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T163	11		T129	11		T224	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T130	14		T31	1		T148	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T29	2		T48	12		T259	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T11	17		T42	8		T15	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T138	13		T238	10		T222	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T29	9		T132	7		T80	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T13	5		T141	14		T215	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T13	5		T33	12		T128	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T7	13		T27	3		T125	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T11	12		T12	13		T80	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T42	4		T31	2		T140	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T28	1		T29	2		T59	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T5	6		T48	7		T131	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T130	13		T215	18		T126	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T2	12		T29	3		T132	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T2	13		T37	1		T130	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T36	1		T48	12		T30	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T141	2		T136	9		T227	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1323	1			T6	2		T14	1		T83	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T48	13		T163	12		T127	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T12	1		T42	9		T216	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T36	1		T29	3		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T3	1		T8	1		T11	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T138	14		T214	12		T217	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T30	1		T148	11		T271	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T7	14		T13	6		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T13	6		T80	2		T163	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T27	7		T37	2		T59	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T2	1		T11	13		T12	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T100	1		T31	6		T140	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T182	3		T154	10		T257	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T42	5		T213	1		T140	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17796	1			T1	120		T4	20		T5	32
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T134	1		T217	1		T181	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T5	1		T48	8		T148	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T215	17		T220	8		T299	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T2	13		T29	1		T232	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T2	11		T237	8		T221	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T36	13		T48	13		T30	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T227	10		T224	9		T137	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1307	1			T6	18		T34	25		T35	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T48	15		T163	12		T127	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T12	2		T42	7		T216	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T36	9		T29	11		T263	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T8	14		T36	12		T29	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T138	8		T217	7		T140	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T148	10		T236	6		T221	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T141	12		T215	9		T163	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T163	6		T33	7		T187	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T27	4		T37	21		T133	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T12	12		T212	6		T142	25
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T31	1		T140	11		T218	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T257	7		T264	4		T300	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T42	10		T213	15		T140	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T253	10		T301	1		T261	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T217	5		T181	2		T280	15

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T2	1		T182	13		T282	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T100	1		T140	9		T152	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T248	6		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T5	6		T48	7		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T215	18		T134	1		T217	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T2	12		T29	3		T132	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T2	13		T37	1		T130	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T36	1		T48	12		T30	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T141	2		T136	9		T226	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1275	1			T6	2		T14	1		T83	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T163	12		T129	12		T227	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T130	15		T216	1		T31	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T36	1		T29	3		T48	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T3	1		T8	1		T11	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T138	14		T271	1		T165	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T29	12		T132	8		T80	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T13	6		T141	15		T215	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T13	6		T33	19		T187	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T7	14		T27	7		T37	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T11	13		T12	14		T80	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	366	1			T37	1		T42	5		T213	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17758	1			T1	120		T4	20		T5	32
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T282	13		T18	7		T258	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T140	9		T152	10		T253	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T5	1		T48	8		T240	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T215	17		T217	5		T181	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T2	13		T29	1		T232	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T2	11		T237	8		T221	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T36	13		T48	13		T30	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T137	13		T175	8		T266	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1271	1			T6	18		T34	25		T35	23
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T163	12		T129	14		T227	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T216	10		T148	15		T127	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T36	9		T29	11		T48	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T8	14		T12	2		T36	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T138	8		T165	16		T238	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T29	7		T80	7		T148	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T141	12		T215	9		T217	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T33	7		T187	2		T129	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T27	4		T37	9		T133	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T12	12		T212	6		T163	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	347	1			T37	12		T42	10		T213	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22791

1

T1

120

T2

26

T3

1

auto[1]

auto[0]

4263

1

T2

24

T5

1

T6

18