Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27054

1

T1

120

T2

50

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20959

1

T1

120

T2

26

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

6095

1

T2

24

T5

7

T6

20

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20820

1

T1

120

T2

50

T4

20

auto[1]

6234

1

T3

1

T5

7

T6

20

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22998

1

T1

120

T2

27

T3

1

auto[1]

4056

1

T2

23

T5

2

T7

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	203	1			T100	1		T130	15		T132	9
values[0]	13	1			T278	13		-	-		-	-
values[1]	650	1			T3	1		T13	6		T37	10
values[2]	780	1			T2	25		T27	11		T36	13
values[3]	681	1			T28	2		T36	14		T130	4
values[4]	814	1			T11	23		T37	1		T29	14
values[5]	687	1			T7	14		T141	27		T134	1
values[6]	550	1			T2	1		T5	7		T8	15
values[7]	634	1			T11	9		T130	13		T48	25
values[8]	846	1			T2	24		T12	3		T13	6
values[9]	3438	1			T6	20		T12	26		T14	1
minimum	17758	1			T1	120		T4	20		T5	32

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	628	1			T2	25		T3	1		T27	11
values[1]	3019	1			T6	20		T14	1		T83	9
values[2]	797	1			T37	1		T130	4		T48	28
values[3]	694	1			T11	23		T29	14		T134	1
values[4]	675	1			T2	1		T7	14		T141	27
values[5]	510	1			T5	7		T8	15		T11	9
values[6]	803	1			T12	3		T13	6		T130	13
values[7]	713	1			T2	24		T100	1		T36	10
values[8]	1075	1			T12	26		T100	1		T37	13
values[9]	145	1			T132	1		T133	10		T127	13
minimum	17995	1			T1	120		T4	20		T5	32

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22791

1

T1

120

T2

26

T3

1

auto[1]

4263

1

T2

24

T5

1

T6

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T2	14		T3	1		T37	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T27	8		T48	9		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T126	1		T140	12		T218	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1710	1			T6	20		T14	1		T83	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T37	1		T48	16		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T130	1		T80	1		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T11	1		T29	12		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T11	1		T131	1		T217	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T2	1		T7	1		T141	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T134	1		T212	7		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T139	1		T176	1		T238	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T5	5		T8	15		T11	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T13	1		T130	1		T42	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T12	3		T48	14		T42	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T100	1		T214	1		T126	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T2	12		T36	10		T59	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	317	1			T100	1		T130	1		T132	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T12	13		T37	13		T29	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T132	1		T133	10		T237	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T127	13		T153	1		T302	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17689	1			T1	120		T4	20		T5	32
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T149	1		T236	7		T228	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T2	11		T232	5		T182	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T27	3		T48	6		T254	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T126	16		T140	11		T136	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1069	1			T83	8		T98	21		T99	27
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T48	12		T148	3		T140	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T130	3		T80	1		T214	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T11	9		T29	2		T16	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T11	12		T140	8		T15	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T7	13		T141	14		T31	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T149	5		T276	7		T234	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T238	8		T248	2		T152	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T5	2		T11	8		T29	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T13	5		T130	12		T42	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T48	11		T42	4		T129	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T214	4		T229	13		T280	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T2	12		T138	13		T214	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T130	14		T132	16		T141	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T12	13		T29	2		T215	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T281	2		T303	1		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T304	10		T284	14		T286	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T13	5		T28	1		T29	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T149	9		T228	9		T305	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T100	1		T130	1		T132	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T306	1		T277	1		T21	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T278	13		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T3	1		T13	1		T37	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T131	1		T217	8		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T2	14		T48	16		T140	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T27	8		T36	13		T48	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T134	1		T126	1		T148	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T28	2		T36	14		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T11	1		T37	1		T29	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T11	1		T131	1		T140	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T7	1		T141	13		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T212	7		T217	4		T128	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T2	1		T176	1		T238	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T5	5		T8	15		T29	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T130	1		T139	1		T125	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T11	1		T48	14		T42	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T13	1		T100	1		T42	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T2	12		T12	3		T59	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T132	1		T141	1		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1804	1			T6	20		T12	13		T14	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17645	1			T1	120		T4	20		T5	32
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T130	14		T132	7		T31	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T277	1		T21	1		T304	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T13	5		T232	5		T224	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T149	9		T254	3		T228	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T2	11		T48	12		T140	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T27	3		T48	6		T215	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T126	16		T148	3		T140	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T130	3		T80	2		T125	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T11	9		T29	2		T142	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T11	12		T140	8		T15	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T7	13		T141	14		T31	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T128	11		T149	5		T129	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T238	8		T152	11		T282	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T5	2		T29	9		T182	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T130	12		T125	7		T163	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T11	8		T48	11		T42	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T13	5		T42	8		T214	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T2	12		T138	13		T214	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T132	9		T141	1		T148	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1107	1			T12	13		T83	8		T98	21
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T28	1		T29	2		T59	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T2	12		T3	1		T37	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T27	7		T48	7		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T126	17		T140	12		T218	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1415	1			T6	2		T14	1		T83	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T37	1		T48	13		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T130	4		T80	2		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T11	10		T29	3		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T11	13		T131	1		T217	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T2	1		T7	14		T141	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T134	1		T212	1		T149	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T139	1		T176	1		T238	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T5	6		T8	1		T11	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T13	6		T130	13		T42	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T12	1		T48	12		T42	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T100	1		T214	5		T126	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T2	13		T36	1		T59	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	338	1			T100	1		T130	15		T132	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T12	14		T37	1		T29	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T132	1		T133	1		T237	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T127	1		T153	1		T302	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17807	1			T1	120		T4	20		T5	32
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T149	10		T236	1		T228	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T2	13		T37	9		T232	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T27	4		T48	8		T217	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T140	11		T218	6		T188	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1364	1			T6	18		T34	25		T35	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T48	15		T148	7		T140	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T127	5		T129	9		T233	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T29	11		T16	5		T17	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T217	3		T140	9		T15	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T141	12		T31	1		T163	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T212	6		T137	5		T276	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T238	5		T152	14		T258	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T5	1		T8	14		T29	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T42	7		T163	6		T15	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T12	2		T48	13		T42	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T229	13		T280	13		T258	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T2	11		T36	9		T138	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T148	25		T142	12		T181	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T12	12		T37	12		T29	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T133	9		T237	8		T281	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T127	12		T284	11		T294	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T224	9		T282	13		T264	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T236	6		T228	3		T241	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T100	1		T130	15		T132	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T306	1		T277	2		T21	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T278	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T3	1		T13	6		T37	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T131	1		T217	1		T149	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T2	12		T48	13		T140	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T27	7		T36	1		T48	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T134	1		T126	17		T148	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T28	2		T36	1		T130	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T11	10		T37	1		T29	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T11	13		T131	1		T140	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T7	14		T141	15		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T212	1		T217	1		T128	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T2	1		T176	1		T238	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T5	6		T8	1		T29	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T130	13		T139	1		T125	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T11	9		T48	12		T42	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T13	6		T100	1		T42	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T2	13		T12	1		T59	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T132	10		T141	2		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1470	1			T6	2		T12	14		T14	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17758	1			T1	120		T4	20		T5	32
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T133	9		T148	10		T237	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T294	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T278	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T37	9		T232	14		T224	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T217	7		T236	6		T254	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T2	13		T48	15		T140	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T27	4		T36	12		T48	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T148	7		T140	7		T175	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T36	13		T80	7		T216	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T29	11		T142	13		T16	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T140	9		T15	1		T129	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T141	12		T31	1		T163	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T212	6		T217	3		T128	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T238	5		T152	14		T282	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T5	1		T8	14		T29	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T163	6		T15	1		T165	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T48	13		T42	10		T129	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T42	7		T229	13		T280	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T2	11		T12	2		T138	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T148	15		T142	12		T181	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1441	1			T6	18		T12	12		T34	25

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22791

1

T1

120

T2

26

T3

1

auto[1]

auto[0]

4263

1

T2

24

T5

1

T6

18