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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.69 99.07 96.67 100.00 100.00 98.83 98.33 90.92


Total test records in report: 920
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T798 /workspace/coverage/default/17.adc_ctrl_clock_gating.494735616 Jun 02 02:46:03 PM PDT 24 Jun 02 02:55:59 PM PDT 24 321930093675 ps
T799 /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.1881671865 Jun 02 02:45:33 PM PDT 24 Jun 02 03:07:50 PM PDT 24 615491585684 ps
T800 /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.2804967945 Jun 02 02:46:56 PM PDT 24 Jun 02 02:51:57 PM PDT 24 610097108539 ps
T801 /workspace/coverage/default/27.adc_ctrl_fsm_reset.1162914938 Jun 02 02:46:11 PM PDT 24 Jun 02 02:50:22 PM PDT 24 72453728016 ps
T802 /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.3607056209 Jun 02 02:45:51 PM PDT 24 Jun 02 02:48:41 PM PDT 24 70351888574 ps
T47 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.1030100177 Jun 02 02:42:49 PM PDT 24 Jun 02 02:42:51 PM PDT 24 406110485 ps
T49 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3840847651 Jun 02 02:42:59 PM PDT 24 Jun 02 02:43:02 PM PDT 24 4770745324 ps
T44 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2849054829 Jun 02 02:42:44 PM PDT 24 Jun 02 02:42:49 PM PDT 24 5123417435 ps
T803 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3939679147 Jun 02 02:42:55 PM PDT 24 Jun 02 02:42:57 PM PDT 24 426035932 ps
T103 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3474162038 Jun 02 02:42:55 PM PDT 24 Jun 02 02:42:57 PM PDT 24 348459408 ps
T804 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1451111493 Jun 02 02:42:54 PM PDT 24 Jun 02 02:42:56 PM PDT 24 514436636 ps
T45 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3797568300 Jun 02 02:42:49 PM PDT 24 Jun 02 02:43:04 PM PDT 24 4250172530 ps
T52 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1184609082 Jun 02 02:42:45 PM PDT 24 Jun 02 02:42:49 PM PDT 24 1459490987 ps
T805 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2960085422 Jun 02 02:42:41 PM PDT 24 Jun 02 02:42:43 PM PDT 24 343779602 ps
T806 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1950977886 Jun 02 02:42:53 PM PDT 24 Jun 02 02:42:55 PM PDT 24 368292585 ps
T46 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1280322545 Jun 02 02:42:53 PM PDT 24 Jun 02 02:42:59 PM PDT 24 5188839911 ps
T807 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.1577408715 Jun 02 02:42:54 PM PDT 24 Jun 02 02:42:56 PM PDT 24 479295980 ps
T50 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1861559331 Jun 02 02:42:45 PM PDT 24 Jun 02 02:42:48 PM PDT 24 5438321765 ps
T124 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.39206927 Jun 02 02:42:37 PM PDT 24 Jun 02 02:43:35 PM PDT 24 53221356059 ps
T51 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3090092469 Jun 02 02:42:36 PM PDT 24 Jun 02 02:42:45 PM PDT 24 9060009798 ps
T57 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1429808182 Jun 02 02:42:52 PM PDT 24 Jun 02 02:42:57 PM PDT 24 510513156 ps
T104 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1314479707 Jun 02 02:42:42 PM PDT 24 Jun 02 02:44:10 PM PDT 24 42769412160 ps
T105 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2393783224 Jun 02 02:42:53 PM PDT 24 Jun 02 02:42:55 PM PDT 24 401844751 ps
T68 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2557953465 Jun 02 02:42:52 PM PDT 24 Jun 02 02:42:55 PM PDT 24 539643397 ps
T808 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.812925723 Jun 02 02:42:54 PM PDT 24 Jun 02 02:42:56 PM PDT 24 308501670 ps
T69 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2276652512 Jun 02 02:42:43 PM PDT 24 Jun 02 02:42:46 PM PDT 24 545562995 ps
T106 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3851204406 Jun 02 02:42:43 PM PDT 24 Jun 02 02:42:45 PM PDT 24 780482129 ps
T809 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2575138509 Jun 02 02:42:57 PM PDT 24 Jun 02 02:42:59 PM PDT 24 496551304 ps
T66 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.4286860495 Jun 02 02:42:42 PM PDT 24 Jun 02 02:42:54 PM PDT 24 3939668252 ps
T120 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2828792732 Jun 02 02:42:51 PM PDT 24 Jun 02 02:42:53 PM PDT 24 519550582 ps
T810 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3499633639 Jun 02 02:42:46 PM PDT 24 Jun 02 02:42:47 PM PDT 24 403347030 ps
T811 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.3463122785 Jun 02 02:42:54 PM PDT 24 Jun 02 02:42:57 PM PDT 24 344631246 ps
T67 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.10738299 Jun 02 02:42:49 PM PDT 24 Jun 02 02:42:52 PM PDT 24 384580682 ps
T812 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.1534594821 Jun 02 02:42:53 PM PDT 24 Jun 02 02:42:56 PM PDT 24 382202462 ps
T86 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1692367605 Jun 02 02:42:50 PM PDT 24 Jun 02 02:42:51 PM PDT 24 822986261 ps
T60 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.990511605 Jun 02 02:42:35 PM PDT 24 Jun 02 02:42:38 PM PDT 24 496337001 ps
T813 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3846256332 Jun 02 02:42:43 PM PDT 24 Jun 02 02:42:45 PM PDT 24 292695680 ps
T107 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2820441513 Jun 02 02:42:43 PM PDT 24 Jun 02 02:44:44 PM PDT 24 52565610983 ps
T108 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2486727112 Jun 02 02:42:42 PM PDT 24 Jun 02 02:42:47 PM PDT 24 1247695578 ps
T814 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.808537495 Jun 02 02:42:41 PM PDT 24 Jun 02 02:42:43 PM PDT 24 498554569 ps
T58 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.20659628 Jun 02 02:42:43 PM PDT 24 Jun 02 02:42:45 PM PDT 24 595917828 ps
T815 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.198095329 Jun 02 02:42:48 PM PDT 24 Jun 02 02:42:51 PM PDT 24 518610373 ps
T816 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3992252984 Jun 02 02:42:53 PM PDT 24 Jun 02 02:42:56 PM PDT 24 384327047 ps
T121 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.3518264900 Jun 02 02:42:49 PM PDT 24 Jun 02 02:43:01 PM PDT 24 4260668537 ps
T109 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2358514848 Jun 02 02:42:42 PM PDT 24 Jun 02 02:42:49 PM PDT 24 1238184443 ps
T817 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2503688580 Jun 02 02:42:53 PM PDT 24 Jun 02 02:42:55 PM PDT 24 474279226 ps
T818 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.4178625371 Jun 02 02:42:33 PM PDT 24 Jun 02 02:42:36 PM PDT 24 374484757 ps
T65 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2658553140 Jun 02 02:42:34 PM PDT 24 Jun 02 02:42:37 PM PDT 24 414683992 ps
T819 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3070611613 Jun 02 02:42:50 PM PDT 24 Jun 02 02:43:12 PM PDT 24 7762976353 ps
T820 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3161971324 Jun 02 02:42:43 PM PDT 24 Jun 02 02:42:45 PM PDT 24 937738376 ps
T821 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.3610556216 Jun 02 02:42:57 PM PDT 24 Jun 02 02:43:00 PM PDT 24 604586991 ps
T822 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3176864388 Jun 02 02:42:41 PM PDT 24 Jun 02 02:42:44 PM PDT 24 843412618 ps
T122 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.158670987 Jun 02 02:42:48 PM PDT 24 Jun 02 02:43:00 PM PDT 24 4067318780 ps
T61 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2045533844 Jun 02 02:42:53 PM PDT 24 Jun 02 02:42:57 PM PDT 24 534343711 ps
T53 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1553420161 Jun 02 02:42:50 PM PDT 24 Jun 02 02:42:58 PM PDT 24 4178986459 ps
T823 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2116178970 Jun 02 02:42:53 PM PDT 24 Jun 02 02:42:57 PM PDT 24 852909986 ps
T110 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2184129085 Jun 02 02:42:43 PM PDT 24 Jun 02 02:42:46 PM PDT 24 451256180 ps
T123 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.3269993449 Jun 02 02:42:54 PM PDT 24 Jun 02 02:42:58 PM PDT 24 2351733422 ps
T336 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3527579075 Jun 02 02:42:36 PM PDT 24 Jun 02 02:42:44 PM PDT 24 8163349557 ps
T824 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1890992466 Jun 02 02:42:51 PM PDT 24 Jun 02 02:42:53 PM PDT 24 441900678 ps
T111 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.1843029364 Jun 02 02:42:53 PM PDT 24 Jun 02 02:42:55 PM PDT 24 427603480 ps
T825 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.4273470736 Jun 02 02:42:41 PM PDT 24 Jun 02 02:42:43 PM PDT 24 284918286 ps
T112 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1998923788 Jun 02 02:42:44 PM PDT 24 Jun 02 02:44:10 PM PDT 24 52048714913 ps
T826 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.2818447673 Jun 02 02:42:51 PM PDT 24 Jun 02 02:42:53 PM PDT 24 348409657 ps
T827 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.4293141536 Jun 02 02:42:55 PM PDT 24 Jun 02 02:42:58 PM PDT 24 512434887 ps
T70 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3999586052 Jun 02 02:42:53 PM PDT 24 Jun 02 02:43:06 PM PDT 24 4483719078 ps
T828 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.3413683151 Jun 02 02:43:05 PM PDT 24 Jun 02 02:43:07 PM PDT 24 292548870 ps
T829 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1816212354 Jun 02 02:42:44 PM PDT 24 Jun 02 02:42:47 PM PDT 24 650962275 ps
T116 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2150745510 Jun 02 02:42:37 PM PDT 24 Jun 02 02:42:39 PM PDT 24 435543680 ps
T830 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2220425200 Jun 02 02:42:52 PM PDT 24 Jun 02 02:42:55 PM PDT 24 457239027 ps
T831 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3596794623 Jun 02 02:42:56 PM PDT 24 Jun 02 02:42:57 PM PDT 24 472787610 ps
T832 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.235713845 Jun 02 02:42:57 PM PDT 24 Jun 02 02:42:59 PM PDT 24 530594158 ps
T833 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.1315374896 Jun 02 02:42:51 PM PDT 24 Jun 02 02:42:53 PM PDT 24 322139423 ps
T834 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3703262856 Jun 02 02:42:52 PM PDT 24 Jun 02 02:43:03 PM PDT 24 4074088583 ps
T835 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3706056310 Jun 02 02:42:49 PM PDT 24 Jun 02 02:42:57 PM PDT 24 2104683946 ps
T836 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.2545843687 Jun 02 02:42:53 PM PDT 24 Jun 02 02:42:55 PM PDT 24 353753157 ps
T837 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3444222639 Jun 02 02:42:53 PM PDT 24 Jun 02 02:43:16 PM PDT 24 4340029736 ps
T838 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2172277503 Jun 02 02:42:42 PM PDT 24 Jun 02 02:42:46 PM PDT 24 1731709656 ps
T113 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3202593211 Jun 02 02:42:55 PM PDT 24 Jun 02 02:42:57 PM PDT 24 404953865 ps
T839 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.715950026 Jun 02 02:42:50 PM PDT 24 Jun 02 02:42:53 PM PDT 24 680813646 ps
T840 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.2034562014 Jun 02 02:42:47 PM PDT 24 Jun 02 02:42:49 PM PDT 24 605162727 ps
T841 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.494096622 Jun 02 02:42:43 PM PDT 24 Jun 02 02:42:52 PM PDT 24 4427608301 ps
T842 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.4115467154 Jun 02 02:42:49 PM PDT 24 Jun 02 02:42:52 PM PDT 24 554211163 ps
T843 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.600293707 Jun 02 02:42:49 PM PDT 24 Jun 02 02:42:51 PM PDT 24 402553723 ps
T844 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1573099337 Jun 02 02:42:34 PM PDT 24 Jun 02 02:42:37 PM PDT 24 385262177 ps
T845 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2057756927 Jun 02 02:42:48 PM PDT 24 Jun 02 02:42:52 PM PDT 24 477011996 ps
T846 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.3701272873 Jun 02 02:42:53 PM PDT 24 Jun 02 02:42:55 PM PDT 24 469857858 ps
T847 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.322433914 Jun 02 02:43:01 PM PDT 24 Jun 02 02:43:02 PM PDT 24 356064210 ps
T117 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.1985380521 Jun 02 02:42:33 PM PDT 24 Jun 02 02:42:38 PM PDT 24 1243388682 ps
T114 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3116051546 Jun 02 02:42:48 PM PDT 24 Jun 02 02:42:51 PM PDT 24 422893106 ps
T115 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.1091443953 Jun 02 02:42:46 PM PDT 24 Jun 02 02:42:48 PM PDT 24 411993073 ps
T848 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.45497318 Jun 02 02:42:50 PM PDT 24 Jun 02 02:42:51 PM PDT 24 407643262 ps
T849 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3884085349 Jun 02 02:42:53 PM PDT 24 Jun 02 02:42:55 PM PDT 24 513330330 ps
T850 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.291857070 Jun 02 02:42:53 PM PDT 24 Jun 02 02:42:56 PM PDT 24 348948286 ps
T851 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.407123355 Jun 02 02:42:49 PM PDT 24 Jun 02 02:43:03 PM PDT 24 8765058375 ps
T852 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2654978785 Jun 02 02:42:47 PM PDT 24 Jun 02 02:42:49 PM PDT 24 492248560 ps
T853 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.1387794413 Jun 02 02:42:53 PM PDT 24 Jun 02 02:42:55 PM PDT 24 451707413 ps
T854 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.874198731 Jun 02 02:43:05 PM PDT 24 Jun 02 02:43:17 PM PDT 24 4561557856 ps
T855 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2235232677 Jun 02 02:42:48 PM PDT 24 Jun 02 02:42:50 PM PDT 24 584830686 ps
T856 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.583966355 Jun 02 02:42:53 PM PDT 24 Jun 02 02:43:02 PM PDT 24 8724557639 ps
T857 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2014211694 Jun 02 02:42:57 PM PDT 24 Jun 02 02:42:59 PM PDT 24 354797745 ps
T858 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2685643262 Jun 02 02:42:48 PM PDT 24 Jun 02 02:43:00 PM PDT 24 5059654667 ps
T118 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1031930152 Jun 02 02:42:37 PM PDT 24 Jun 02 02:42:40 PM PDT 24 2295982036 ps
T859 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1034781746 Jun 02 02:42:52 PM PDT 24 Jun 02 02:42:54 PM PDT 24 532067469 ps
T860 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.366884437 Jun 02 02:42:47 PM PDT 24 Jun 02 02:42:51 PM PDT 24 615577410 ps
T861 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1891412140 Jun 02 02:42:48 PM PDT 24 Jun 02 02:42:51 PM PDT 24 443851379 ps
T862 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.4281483630 Jun 02 02:42:47 PM PDT 24 Jun 02 02:42:50 PM PDT 24 526909624 ps
T863 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.2202242660 Jun 02 02:42:53 PM PDT 24 Jun 02 02:42:56 PM PDT 24 536353794 ps
T864 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1176426469 Jun 02 02:42:55 PM PDT 24 Jun 02 02:42:57 PM PDT 24 393188231 ps
T865 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1266978214 Jun 02 02:42:48 PM PDT 24 Jun 02 02:42:51 PM PDT 24 470249480 ps
T866 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3960808053 Jun 02 02:42:46 PM PDT 24 Jun 02 02:42:49 PM PDT 24 451878455 ps
T867 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1351661719 Jun 02 02:42:52 PM PDT 24 Jun 02 02:42:55 PM PDT 24 365223474 ps
T868 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.674787952 Jun 02 02:42:51 PM PDT 24 Jun 02 02:42:53 PM PDT 24 412332864 ps
T869 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.64663957 Jun 02 02:42:42 PM PDT 24 Jun 02 02:42:45 PM PDT 24 2132941059 ps
T870 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1026648858 Jun 02 02:42:47 PM PDT 24 Jun 02 02:42:51 PM PDT 24 342360510 ps
T871 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1734440451 Jun 02 02:42:49 PM PDT 24 Jun 02 02:42:52 PM PDT 24 442707677 ps
T338 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.4077817114 Jun 02 02:42:47 PM PDT 24 Jun 02 02:42:56 PM PDT 24 4971885274 ps
T872 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3376139745 Jun 02 02:42:51 PM PDT 24 Jun 02 02:42:53 PM PDT 24 719712954 ps
T119 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2233551281 Jun 02 02:42:35 PM PDT 24 Jun 02 02:44:18 PM PDT 24 52340489918 ps
T873 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.3034197506 Jun 02 02:42:36 PM PDT 24 Jun 02 02:42:38 PM PDT 24 373542221 ps
T874 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2860466994 Jun 02 02:42:40 PM PDT 24 Jun 02 02:42:42 PM PDT 24 465370403 ps
T875 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.858664512 Jun 02 02:42:55 PM PDT 24 Jun 02 02:42:57 PM PDT 24 470705752 ps
T876 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1640217273 Jun 02 02:42:36 PM PDT 24 Jun 02 02:42:38 PM PDT 24 416057775 ps
T877 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1839318432 Jun 02 02:42:56 PM PDT 24 Jun 02 02:42:58 PM PDT 24 502365296 ps
T71 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2438743802 Jun 02 02:42:53 PM PDT 24 Jun 02 02:42:58 PM PDT 24 4163605906 ps
T878 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3178645569 Jun 02 02:42:48 PM PDT 24 Jun 02 02:42:51 PM PDT 24 560264641 ps
T72 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3381122107 Jun 02 02:42:53 PM PDT 24 Jun 02 02:43:07 PM PDT 24 8152184114 ps
T879 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2718987739 Jun 02 02:42:56 PM PDT 24 Jun 02 02:42:58 PM PDT 24 1628396131 ps
T880 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.3862012387 Jun 02 02:42:53 PM PDT 24 Jun 02 02:42:55 PM PDT 24 316301723 ps
T881 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3321792909 Jun 02 02:42:42 PM PDT 24 Jun 02 02:42:43 PM PDT 24 389042997 ps
T882 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3349412304 Jun 02 02:42:51 PM PDT 24 Jun 02 02:42:59 PM PDT 24 8518775868 ps
T883 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.4048500185 Jun 02 02:42:57 PM PDT 24 Jun 02 02:42:59 PM PDT 24 484676448 ps
T884 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3681086208 Jun 02 02:42:47 PM PDT 24 Jun 02 02:42:59 PM PDT 24 3937446590 ps
T885 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.1183379923 Jun 02 02:42:46 PM PDT 24 Jun 02 02:42:48 PM PDT 24 526683832 ps
T886 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1202545683 Jun 02 02:42:54 PM PDT 24 Jun 02 02:42:56 PM PDT 24 801952425 ps
T887 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1355182005 Jun 02 02:42:52 PM PDT 24 Jun 02 02:42:55 PM PDT 24 3968192760 ps
T888 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1249753183 Jun 02 02:42:54 PM PDT 24 Jun 02 02:42:57 PM PDT 24 4085804219 ps
T889 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.2683819997 Jun 02 02:43:05 PM PDT 24 Jun 02 02:43:06 PM PDT 24 379116209 ps
T890 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1865697824 Jun 02 02:42:49 PM PDT 24 Jun 02 02:42:51 PM PDT 24 527547553 ps
T337 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1126355543 Jun 02 02:42:40 PM PDT 24 Jun 02 02:42:53 PM PDT 24 4602295268 ps
T891 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3285298950 Jun 02 02:42:52 PM PDT 24 Jun 02 02:42:54 PM PDT 24 433855605 ps
T892 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1064852501 Jun 02 02:42:47 PM PDT 24 Jun 02 02:42:58 PM PDT 24 2376634573 ps
T893 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1495163565 Jun 02 02:42:43 PM PDT 24 Jun 02 02:42:47 PM PDT 24 1323941805 ps
T894 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.1305656946 Jun 02 02:42:53 PM PDT 24 Jun 02 02:42:56 PM PDT 24 418410176 ps
T895 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3183577653 Jun 02 02:42:35 PM PDT 24 Jun 02 02:42:37 PM PDT 24 781832399 ps
T896 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.1857342468 Jun 02 02:42:49 PM PDT 24 Jun 02 02:42:51 PM PDT 24 503948917 ps
T897 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.2056545871 Jun 02 02:42:52 PM PDT 24 Jun 02 02:42:57 PM PDT 24 2822487522 ps
T898 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2766504541 Jun 02 02:42:48 PM PDT 24 Jun 02 02:42:58 PM PDT 24 3857857001 ps
T899 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1862674353 Jun 02 02:42:56 PM PDT 24 Jun 02 02:42:57 PM PDT 24 297992749 ps
T900 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.697327936 Jun 02 02:43:05 PM PDT 24 Jun 02 02:43:06 PM PDT 24 381374331 ps
T901 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1058704639 Jun 02 02:42:47 PM PDT 24 Jun 02 02:42:49 PM PDT 24 502056857 ps
T902 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.923139874 Jun 02 02:42:51 PM PDT 24 Jun 02 02:42:54 PM PDT 24 416008218 ps
T903 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2657377318 Jun 02 02:42:41 PM PDT 24 Jun 02 02:42:49 PM PDT 24 8306992176 ps
T904 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1758501419 Jun 02 02:42:48 PM PDT 24 Jun 02 02:42:51 PM PDT 24 1938802421 ps
T905 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.780036653 Jun 02 02:42:51 PM PDT 24 Jun 02 02:42:53 PM PDT 24 449912530 ps
T906 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.190782689 Jun 02 02:42:36 PM PDT 24 Jun 02 02:42:40 PM PDT 24 4748646016 ps
T907 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1205493102 Jun 02 02:42:52 PM PDT 24 Jun 02 02:42:55 PM PDT 24 3037999899 ps
T908 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2119441078 Jun 02 02:42:42 PM PDT 24 Jun 02 02:42:47 PM PDT 24 2493134473 ps
T909 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1767737190 Jun 02 02:42:53 PM PDT 24 Jun 02 02:42:55 PM PDT 24 445777474 ps
T910 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1767173353 Jun 02 02:42:46 PM PDT 24 Jun 02 02:42:47 PM PDT 24 484357112 ps
T911 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.990961205 Jun 02 02:42:54 PM PDT 24 Jun 02 02:42:56 PM PDT 24 416524223 ps
T912 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.248313182 Jun 02 02:42:53 PM PDT 24 Jun 02 02:42:56 PM PDT 24 457484243 ps
T913 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3154839618 Jun 02 02:42:47 PM PDT 24 Jun 02 02:42:49 PM PDT 24 514732550 ps
T914 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.476848241 Jun 02 02:42:41 PM PDT 24 Jun 02 02:42:44 PM PDT 24 566862530 ps
T915 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2779408987 Jun 02 02:42:51 PM PDT 24 Jun 02 02:43:03 PM PDT 24 4212883439 ps
T916 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.367904264 Jun 02 02:42:53 PM PDT 24 Jun 02 02:42:55 PM PDT 24 340797482 ps
T917 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.779221694 Jun 02 02:42:41 PM PDT 24 Jun 02 02:42:42 PM PDT 24 563427488 ps
T918 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.1997334225 Jun 02 02:42:47 PM PDT 24 Jun 02 02:42:50 PM PDT 24 498184281 ps
T919 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.502935962 Jun 02 02:42:49 PM PDT 24 Jun 02 02:43:01 PM PDT 24 4410167276 ps
T920 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.1880368319 Jun 02 02:42:52 PM PDT 24 Jun 02 02:42:54 PM PDT 24 623319403 ps

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.4053110114
Short name T5
Test name
Test status
Simulation time 40464744789 ps
CPU time 116.17 seconds
Started Jun 02 02:46:32 PM PDT 24
Finished Jun 02 02:48:29 PM PDT 24
Peak memory 218004 kb
Host smart-1954c1e1-e3ce-41af-aa15-857de0ed26e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053110114 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.4053110114
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.1071878630
Short name T2
Test name
Test status
Simulation time 632077523773 ps
CPU time 791.68 seconds
Started Jun 02 02:45:59 PM PDT 24
Finished Jun 02 02:59:11 PM PDT 24
Peak memory 201712 kb
Host smart-643640ab-dc29-437d-b56f-d1acc7c94b51
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071878630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.1071878630
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.230730553
Short name T29
Test name
Test status
Simulation time 477996492855 ps
CPU time 461.89 seconds
Started Jun 02 02:48:02 PM PDT 24
Finished Jun 02 02:55:45 PM PDT 24
Peak memory 210464 kb
Host smart-117de52b-62d6-46f0-a154-c6d48bd4b929
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230730553 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.230730553
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.395038712
Short name T42
Test name
Test status
Simulation time 648296073508 ps
CPU time 549.82 seconds
Started Jun 02 02:46:00 PM PDT 24
Finished Jun 02 02:55:16 PM PDT 24
Peak memory 202052 kb
Host smart-5d6e59fe-e76e-4270-8aa9-aa2e98b0387f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395038712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all.
395038712
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.1116636537
Short name T48
Test name
Test status
Simulation time 513338048153 ps
CPU time 291.65 seconds
Started Jun 02 02:48:09 PM PDT 24
Finished Jun 02 02:53:02 PM PDT 24
Peak memory 201800 kb
Host smart-c77dbd05-901d-49c5-93eb-20af1af839fe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116636537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.1116636537
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.3506764402
Short name T228
Test name
Test status
Simulation time 526525636312 ps
CPU time 898.09 seconds
Started Jun 02 02:46:09 PM PDT 24
Finished Jun 02 03:01:09 PM PDT 24
Peak memory 201724 kb
Host smart-c4525302-b3fc-4465-995a-c0acaa402819
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506764402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.3506764402
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.2147928133
Short name T140
Test name
Test status
Simulation time 495973012377 ps
CPU time 260.1 seconds
Started Jun 02 02:47:18 PM PDT 24
Finished Jun 02 02:51:39 PM PDT 24
Peak memory 201776 kb
Host smart-9180eea1-62b1-4232-921e-835d990b7429
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147928133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.2147928133
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.1849805168
Short name T148
Test name
Test status
Simulation time 524408974339 ps
CPU time 637.44 seconds
Started Jun 02 02:46:14 PM PDT 24
Finished Jun 02 02:56:52 PM PDT 24
Peak memory 201788 kb
Host smart-149e78e7-ab65-4715-baa0-c3281b9b1f23
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849805168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.1849805168
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1184609082
Short name T52
Test name
Test status
Simulation time 1459490987 ps
CPU time 3.04 seconds
Started Jun 02 02:42:45 PM PDT 24
Finished Jun 02 02:42:49 PM PDT 24
Peak memory 211184 kb
Host smart-0abb496b-d714-4365-b886-3c6eb6d7c754
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184609082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.1184609082
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.689741950
Short name T11
Test name
Test status
Simulation time 484846367882 ps
CPU time 487.34 seconds
Started Jun 02 02:45:52 PM PDT 24
Finished Jun 02 02:54:00 PM PDT 24
Peak memory 201784 kb
Host smart-fe87214d-8477-470d-93ef-75b1e999ee46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689741950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.689741950
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.1321483940
Short name T181
Test name
Test status
Simulation time 507810730030 ps
CPU time 289.39 seconds
Started Jun 02 02:45:57 PM PDT 24
Finished Jun 02 02:50:47 PM PDT 24
Peak memory 201840 kb
Host smart-89d07ab0-e04a-4fbe-adfe-1e998448dd01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321483940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.1321483940
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.1844815100
Short name T54
Test name
Test status
Simulation time 3741692971 ps
CPU time 2.86 seconds
Started Jun 02 02:45:14 PM PDT 24
Finished Jun 02 02:45:19 PM PDT 24
Peak memory 217456 kb
Host smart-5de6805a-f535-4656-98d5-2ea0139c2e78
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844815100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.1844815100
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.2420742072
Short name T214
Test name
Test status
Simulation time 496570257321 ps
CPU time 570.29 seconds
Started Jun 02 02:46:27 PM PDT 24
Finished Jun 02 02:55:57 PM PDT 24
Peak memory 201712 kb
Host smart-f0f70890-bea4-4a35-ba26-b50d58b9af13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420742072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.2420742072
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.526073942
Short name T152
Test name
Test status
Simulation time 519911223341 ps
CPU time 94.96 seconds
Started Jun 02 02:46:11 PM PDT 24
Finished Jun 02 02:47:47 PM PDT 24
Peak memory 201852 kb
Host smart-a1e90f34-4c87-47a7-a2bf-e7e786a74690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526073942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.526073942
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.1297294905
Short name T34
Test name
Test status
Simulation time 400638582171 ps
CPU time 950.01 seconds
Started Jun 02 02:46:39 PM PDT 24
Finished Jun 02 03:02:30 PM PDT 24
Peak memory 201732 kb
Host smart-5e42cf45-16fd-4eb3-a0aa-2c7949cca550
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297294905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.1297294905
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1314479707
Short name T104
Test name
Test status
Simulation time 42769412160 ps
CPU time 87.35 seconds
Started Jun 02 02:42:42 PM PDT 24
Finished Jun 02 02:44:10 PM PDT 24
Peak memory 201932 kb
Host smart-6b3fbef0-586c-4a2d-8a53-7de862c9f051
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314479707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.1314479707
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.2062760946
Short name T282
Test name
Test status
Simulation time 508354824858 ps
CPU time 1267.43 seconds
Started Jun 02 02:46:09 PM PDT 24
Finished Jun 02 03:07:19 PM PDT 24
Peak memory 201924 kb
Host smart-96134a2f-fe2f-4354-9b4d-030ced4677f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062760946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.2062760946
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.1341450305
Short name T136
Test name
Test status
Simulation time 487538790727 ps
CPU time 119.69 seconds
Started Jun 02 02:46:11 PM PDT 24
Finished Jun 02 02:48:12 PM PDT 24
Peak memory 201852 kb
Host smart-af197f95-ccb0-4aee-9067-9232b7165330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341450305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.1341450305
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.197803434
Short name T215
Test name
Test status
Simulation time 359083554049 ps
CPU time 754.81 seconds
Started Jun 02 02:46:07 PM PDT 24
Finished Jun 02 02:58:44 PM PDT 24
Peak memory 201772 kb
Host smart-5a7e686d-e6b6-4a44-8c40-d4fa375afb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197803434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.197803434
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.1001125146
Short name T257
Test name
Test status
Simulation time 379655742549 ps
CPU time 220.29 seconds
Started Jun 02 02:46:34 PM PDT 24
Finished Jun 02 02:50:15 PM PDT 24
Peak memory 201752 kb
Host smart-208fb9df-4f66-40fe-96c4-0f4942b0f099
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001125146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.1001125146
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.1823465242
Short name T13
Test name
Test status
Simulation time 334650188996 ps
CPU time 168.82 seconds
Started Jun 02 02:46:02 PM PDT 24
Finished Jun 02 02:48:52 PM PDT 24
Peak memory 201776 kb
Host smart-b4b6f612-68fe-4b8c-8dae-7fd527fce71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823465242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.1823465242
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.3814144533
Short name T132
Test name
Test status
Simulation time 490093766441 ps
CPU time 1212.51 seconds
Started Jun 02 02:46:01 PM PDT 24
Finished Jun 02 03:06:14 PM PDT 24
Peak memory 201868 kb
Host smart-faea6871-f965-4dbc-8196-e79ada402bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814144533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.3814144533
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.3691819711
Short name T235
Test name
Test status
Simulation time 352505637335 ps
CPU time 216.82 seconds
Started Jun 02 02:45:14 PM PDT 24
Finished Jun 02 02:48:53 PM PDT 24
Peak memory 201840 kb
Host smart-b1b5d9ab-50da-4d2b-812c-d5fa2fd7e19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691819711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.3691819711
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.3997305185
Short name T373
Test name
Test status
Simulation time 405903414 ps
CPU time 0.87 seconds
Started Jun 02 02:45:51 PM PDT 24
Finished Jun 02 02:45:53 PM PDT 24
Peak memory 201416 kb
Host smart-f39a1fdc-f815-45c8-ae46-185fe7ad156f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997305185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.3997305185
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.2350655449
Short name T217
Test name
Test status
Simulation time 527629306986 ps
CPU time 1090.36 seconds
Started Jun 02 02:46:11 PM PDT 24
Finished Jun 02 03:04:23 PM PDT 24
Peak memory 201828 kb
Host smart-57091666-cdde-4c53-ba43-96345d199e9d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350655449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.2350655449
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.3074219643
Short name T21
Test name
Test status
Simulation time 224254781688 ps
CPU time 203.32 seconds
Started Jun 02 02:45:39 PM PDT 24
Finished Jun 02 02:49:03 PM PDT 24
Peak memory 210104 kb
Host smart-8d84269a-9459-4cc5-9392-468439a8619b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074219643 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.3074219643
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.3151399028
Short name T272
Test name
Test status
Simulation time 158723904020 ps
CPU time 99.14 seconds
Started Jun 02 02:46:03 PM PDT 24
Finished Jun 02 02:47:43 PM PDT 24
Peak memory 201852 kb
Host smart-e67ea922-1840-480d-8aea-754a3d8ce225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151399028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.3151399028
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.4090257264
Short name T149
Test name
Test status
Simulation time 491460181784 ps
CPU time 961.91 seconds
Started Jun 02 02:46:13 PM PDT 24
Finished Jun 02 03:02:16 PM PDT 24
Peak memory 201768 kb
Host smart-6aaa7409-2b8b-4afd-8e30-764973aede6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090257264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.4090257264
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3527579075
Short name T336
Test name
Test status
Simulation time 8163349557 ps
CPU time 7.03 seconds
Started Jun 02 02:42:36 PM PDT 24
Finished Jun 02 02:42:44 PM PDT 24
Peak memory 201876 kb
Host smart-bcfea058-be69-4ac5-b8a8-6ca6b0a5deab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527579075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.3527579075
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.2013092141
Short name T287
Test name
Test status
Simulation time 346025900426 ps
CPU time 837.65 seconds
Started Jun 02 02:46:08 PM PDT 24
Finished Jun 02 03:00:08 PM PDT 24
Peak memory 201708 kb
Host smart-264d3844-df5a-4752-9b04-175c0fc4dd90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013092141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.2013092141
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.2188565474
Short name T284
Test name
Test status
Simulation time 539751018719 ps
CPU time 902.38 seconds
Started Jun 02 02:46:42 PM PDT 24
Finished Jun 02 03:01:45 PM PDT 24
Peak memory 201692 kb
Host smart-2a28ef9b-3128-4d1a-ba57-dd5c10bbbdf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188565474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.2188565474
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.3519142582
Short name T243
Test name
Test status
Simulation time 344498466451 ps
CPU time 440.66 seconds
Started Jun 02 02:47:02 PM PDT 24
Finished Jun 02 02:54:23 PM PDT 24
Peak memory 201764 kb
Host smart-a5d30d96-22d5-4a1d-9b47-e3bd27afbfb2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519142582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.3519142582
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.761975382
Short name T277
Test name
Test status
Simulation time 544059701025 ps
CPU time 123.48 seconds
Started Jun 02 02:46:11 PM PDT 24
Finished Jun 02 02:48:16 PM PDT 24
Peak memory 201820 kb
Host smart-5d91717f-2fda-4d75-87c6-dd00a21e3080
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761975382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all.
761975382
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.730694106
Short name T293
Test name
Test status
Simulation time 490902683453 ps
CPU time 1081.73 seconds
Started Jun 02 02:46:02 PM PDT 24
Finished Jun 02 03:04:05 PM PDT 24
Peak memory 201772 kb
Host smart-5bd31d86-0e4b-4b9a-82c0-68f297c83946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730694106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.730694106
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.2333564531
Short name T245
Test name
Test status
Simulation time 491570303143 ps
CPU time 1205.72 seconds
Started Jun 02 02:47:52 PM PDT 24
Finished Jun 02 03:07:58 PM PDT 24
Peak memory 201676 kb
Host smart-7660df48-f02d-4dad-b952-067758a7d9b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333564531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.2333564531
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.540378868
Short name T22
Test name
Test status
Simulation time 109210420823 ps
CPU time 56.43 seconds
Started Jun 02 02:46:21 PM PDT 24
Finished Jun 02 02:47:18 PM PDT 24
Peak memory 210064 kb
Host smart-3ae3a45e-605e-49b0-9c0a-49b0b283acef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540378868 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.540378868
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.2507735879
Short name T312
Test name
Test status
Simulation time 657840040890 ps
CPU time 122.39 seconds
Started Jun 02 02:45:38 PM PDT 24
Finished Jun 02 02:47:41 PM PDT 24
Peak memory 201820 kb
Host smart-aca2f28a-6240-4d39-ad41-e69e1fc2c37b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507735879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
2507735879
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.299484142
Short name T285
Test name
Test status
Simulation time 776357443510 ps
CPU time 381.69 seconds
Started Jun 02 02:46:24 PM PDT 24
Finished Jun 02 02:52:46 PM PDT 24
Peak memory 201780 kb
Host smart-26b9c2d0-e563-4bca-b87c-b5e17857ffd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299484142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all.
299484142
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.339688837
Short name T141
Test name
Test status
Simulation time 340126266306 ps
CPU time 231.15 seconds
Started Jun 02 02:46:53 PM PDT 24
Finished Jun 02 02:50:45 PM PDT 24
Peak memory 201772 kb
Host smart-fcdf47af-27b5-4833-be05-fdbe9ca2a4f1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339688837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gati
ng.339688837
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.3352148898
Short name T278
Test name
Test status
Simulation time 200025749394 ps
CPU time 491.26 seconds
Started Jun 02 02:46:15 PM PDT 24
Finished Jun 02 02:54:27 PM PDT 24
Peak memory 201800 kb
Host smart-7fa6233b-60f3-49b6-a555-97da59249b48
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352148898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.3352148898
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.2292391310
Short name T225
Test name
Test status
Simulation time 498873917330 ps
CPU time 1150.36 seconds
Started Jun 02 02:46:10 PM PDT 24
Finished Jun 02 03:05:22 PM PDT 24
Peak memory 201804 kb
Host smart-19d64b06-10b5-4988-a48b-a6aa5df32d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292391310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.2292391310
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.2404218984
Short name T33
Test name
Test status
Simulation time 199003055186 ps
CPU time 282.09 seconds
Started Jun 02 02:47:50 PM PDT 24
Finished Jun 02 02:52:33 PM PDT 24
Peak memory 210316 kb
Host smart-9a4b6422-8996-4387-85a4-7dba774f890b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404218984 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.2404218984
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.1519280248
Short name T194
Test name
Test status
Simulation time 122803427509 ps
CPU time 522.33 seconds
Started Jun 02 02:45:18 PM PDT 24
Finished Jun 02 02:54:02 PM PDT 24
Peak memory 202112 kb
Host smart-f1503eed-3430-4025-ab0e-da3636a3992b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519280248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.1519280248
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.1192593707
Short name T248
Test name
Test status
Simulation time 328817221433 ps
CPU time 673.39 seconds
Started Jun 02 02:45:46 PM PDT 24
Finished Jun 02 02:57:01 PM PDT 24
Peak memory 201860 kb
Host smart-b2dd348a-99e6-4121-8b2d-bacc95586808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192593707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.1192593707
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2150745510
Short name T116
Test name
Test status
Simulation time 435543680 ps
CPU time 1 seconds
Started Jun 02 02:42:37 PM PDT 24
Finished Jun 02 02:42:39 PM PDT 24
Peak memory 201644 kb
Host smart-1adfcfa9-2fe8-4635-b77b-23504d214e97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150745510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.2150745510
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.331117930
Short name T258
Test name
Test status
Simulation time 346180309746 ps
CPU time 730.46 seconds
Started Jun 02 02:45:49 PM PDT 24
Finished Jun 02 02:58:01 PM PDT 24
Peak memory 201856 kb
Host smart-47f7d4a6-4981-4f24-baea-b46c7901942d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331117930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_
wakeup.331117930
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.2975821108
Short name T246
Test name
Test status
Simulation time 455426640671 ps
CPU time 1375.26 seconds
Started Jun 02 02:46:09 PM PDT 24
Finished Jun 02 03:09:06 PM PDT 24
Peak memory 210236 kb
Host smart-0bf9002e-a075-4973-b6dd-67df3236a30b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975821108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.2975821108
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.1151836539
Short name T264
Test name
Test status
Simulation time 624699819676 ps
CPU time 1282.99 seconds
Started Jun 02 02:46:04 PM PDT 24
Finished Jun 02 03:07:29 PM PDT 24
Peak memory 201784 kb
Host smart-d3d6e6a8-dee6-43a2-8121-2dbf455c030e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151836539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.1151836539
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.544886107
Short name T198
Test name
Test status
Simulation time 232793371584 ps
CPU time 804.77 seconds
Started Jun 02 02:46:08 PM PDT 24
Finished Jun 02 02:59:35 PM PDT 24
Peak memory 202004 kb
Host smart-557dff3a-3510-4357-bf4c-d15ab719a748
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544886107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all.
544886107
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.803577281
Short name T94
Test name
Test status
Simulation time 326392158449 ps
CPU time 709.67 seconds
Started Jun 02 02:46:05 PM PDT 24
Finished Jun 02 02:57:56 PM PDT 24
Peak memory 201800 kb
Host smart-73ddd88d-4cec-4c1a-9eb2-c36c23bc8349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803577281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.803577281
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.12527472
Short name T281
Test name
Test status
Simulation time 593618008532 ps
CPU time 1271.71 seconds
Started Jun 02 02:46:25 PM PDT 24
Finished Jun 02 03:07:38 PM PDT 24
Peak memory 201784 kb
Host smart-a35d7787-cb38-4fea-b245-518a9b1d39ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12527472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.12527472
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.2805338078
Short name T256
Test name
Test status
Simulation time 160208991696 ps
CPU time 391.24 seconds
Started Jun 02 02:45:12 PM PDT 24
Finished Jun 02 02:51:45 PM PDT 24
Peak memory 201868 kb
Host smart-ec2a0268-db30-46c9-9b64-9ebad6c27875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805338078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.2805338078
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.824063442
Short name T165
Test name
Test status
Simulation time 557242077358 ps
CPU time 313.27 seconds
Started Jun 02 02:46:02 PM PDT 24
Finished Jun 02 02:51:16 PM PDT 24
Peak memory 201788 kb
Host smart-80287d37-007b-4b95-a4ac-fb0486bbc40c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824063442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_
wakeup.824063442
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.2590246911
Short name T204
Test name
Test status
Simulation time 128388509989 ps
CPU time 505.04 seconds
Started Jun 02 02:46:08 PM PDT 24
Finished Jun 02 02:54:35 PM PDT 24
Peak memory 202140 kb
Host smart-0bb1277e-e21a-4c4c-af4b-e1721f5c44d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590246911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.2590246911
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.840780344
Short name T286
Test name
Test status
Simulation time 723429472435 ps
CPU time 523.02 seconds
Started Jun 02 02:46:47 PM PDT 24
Finished Jun 02 02:55:31 PM PDT 24
Peak memory 217688 kb
Host smart-121363fd-b435-4027-aa68-7bf62c037253
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840780344 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.840780344
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.445234570
Short name T294
Test name
Test status
Simulation time 358882106707 ps
CPU time 829.77 seconds
Started Jun 02 02:46:51 PM PDT 24
Finished Jun 02 03:00:42 PM PDT 24
Peak memory 201784 kb
Host smart-43d39e8c-e615-42e4-bd7a-142298e558da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445234570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.445234570
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.3339729119
Short name T289
Test name
Test status
Simulation time 414199521232 ps
CPU time 1087.12 seconds
Started Jun 02 02:45:48 PM PDT 24
Finished Jun 02 03:03:56 PM PDT 24
Peak memory 202156 kb
Host smart-895487ad-5355-4e9c-a53f-d24f65039ffb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339729119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
3339729119
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1126355543
Short name T337
Test name
Test status
Simulation time 4602295268 ps
CPU time 12.5 seconds
Started Jun 02 02:42:40 PM PDT 24
Finished Jun 02 02:42:53 PM PDT 24
Peak memory 201948 kb
Host smart-d8f74b9d-0957-47a0-bcd4-67870e04b188
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126355543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.1126355543
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.1483722019
Short name T333
Test name
Test status
Simulation time 358192525526 ps
CPU time 851.55 seconds
Started Jun 02 02:45:59 PM PDT 24
Finished Jun 02 03:00:11 PM PDT 24
Peak memory 201704 kb
Host smart-80caa6de-8e08-4174-a98d-ffd8bd63b031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483722019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.1483722019
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.2431502490
Short name T301
Test name
Test status
Simulation time 216852777360 ps
CPU time 130.61 seconds
Started Jun 02 02:46:04 PM PDT 24
Finished Jun 02 02:48:16 PM PDT 24
Peak memory 210064 kb
Host smart-12cbb09a-0b19-417e-bcb1-50219f09f493
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431502490 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.2431502490
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.4092216411
Short name T239
Test name
Test status
Simulation time 342778838775 ps
CPU time 655.07 seconds
Started Jun 02 02:46:03 PM PDT 24
Finished Jun 02 02:56:58 PM PDT 24
Peak memory 201572 kb
Host smart-48fa5f07-c413-452c-872d-c4bafd7d5366
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092216411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.4092216411
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.3844133596
Short name T734
Test name
Test status
Simulation time 593619600453 ps
CPU time 152.95 seconds
Started Jun 02 02:45:23 PM PDT 24
Finished Jun 02 02:47:56 PM PDT 24
Peak memory 201796 kb
Host smart-dd87f94d-9fd0-481f-825b-a0e57f65c009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844133596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.3844133596
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.3355331113
Short name T250
Test name
Test status
Simulation time 330974523323 ps
CPU time 343.63 seconds
Started Jun 02 02:46:02 PM PDT 24
Finished Jun 02 02:51:47 PM PDT 24
Peak memory 201720 kb
Host smart-cf78a055-e0bf-45db-bbd5-c90b47a2e97b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355331113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.3355331113
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.3897186356
Short name T279
Test name
Test status
Simulation time 322584196186 ps
CPU time 397.73 seconds
Started Jun 02 02:46:33 PM PDT 24
Finished Jun 02 02:53:11 PM PDT 24
Peak memory 201756 kb
Host smart-40ef5c6b-62bc-4296-af76-eee603b015b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897186356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.3897186356
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.1390178311
Short name T330
Test name
Test status
Simulation time 416958277591 ps
CPU time 1214.18 seconds
Started Jun 02 02:47:07 PM PDT 24
Finished Jun 02 03:07:21 PM PDT 24
Peak memory 210292 kb
Host smart-bdada088-46c9-4b65-a6d8-11cd2984d698
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390178311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.1390178311
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.2492702775
Short name T233
Test name
Test status
Simulation time 345761479151 ps
CPU time 772.91 seconds
Started Jun 02 02:47:35 PM PDT 24
Finished Jun 02 03:00:28 PM PDT 24
Peak memory 201716 kb
Host smart-6ce4a450-a9f4-4caf-bfd9-f724e6fc151b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492702775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.2492702775
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.1503002422
Short name T244
Test name
Test status
Simulation time 161080033211 ps
CPU time 306.29 seconds
Started Jun 02 02:48:09 PM PDT 24
Finished Jun 02 02:53:16 PM PDT 24
Peak memory 201728 kb
Host smart-00d843da-9580-4607-bd90-32af2ab93109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503002422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.1503002422
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.990511605
Short name T60
Test name
Test status
Simulation time 496337001 ps
CPU time 1.79 seconds
Started Jun 02 02:42:35 PM PDT 24
Finished Jun 02 02:42:38 PM PDT 24
Peak memory 201912 kb
Host smart-a95339a0-dc32-42a0-9f9c-01ff131e8d64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990511605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.990511605
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.1871592177
Short name T356
Test name
Test status
Simulation time 329239627380 ps
CPU time 816.04 seconds
Started Jun 02 02:45:15 PM PDT 24
Finished Jun 02 02:58:54 PM PDT 24
Peak memory 201788 kb
Host smart-dfff6f5c-3264-441b-8706-8de4e4708505
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871592177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.1871592177
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.3487424442
Short name T262
Test name
Test status
Simulation time 539230461243 ps
CPU time 84.28 seconds
Started Jun 02 02:45:58 PM PDT 24
Finished Jun 02 02:47:23 PM PDT 24
Peak memory 201852 kb
Host smart-0334ed34-1380-4181-85d1-dfc6ae53c874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487424442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.3487424442
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.17715847
Short name T690
Test name
Test status
Simulation time 567327510338 ps
CPU time 262.27 seconds
Started Jun 02 02:45:44 PM PDT 24
Finished Jun 02 02:50:07 PM PDT 24
Peak memory 201796 kb
Host smart-5222f92f-0851-4f7d-bb72-8019c7094db7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17715847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_w
akeup.17715847
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.4185256776
Short name T341
Test name
Test status
Simulation time 130103150423 ps
CPU time 427 seconds
Started Jun 02 02:45:51 PM PDT 24
Finished Jun 02 02:52:58 PM PDT 24
Peak memory 202304 kb
Host smart-cf971b07-3541-4507-b0d5-f754598d02f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185256776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.4185256776
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.621854820
Short name T202
Test name
Test status
Simulation time 126610246232 ps
CPU time 561.39 seconds
Started Jun 02 02:45:58 PM PDT 24
Finished Jun 02 02:55:19 PM PDT 24
Peak memory 202056 kb
Host smart-f86c5f2c-282f-4cc6-88f6-3290dbf9029e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621854820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.621854820
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.661154152
Short name T265
Test name
Test status
Simulation time 505262307073 ps
CPU time 583.78 seconds
Started Jun 02 02:46:09 PM PDT 24
Finished Jun 02 02:55:55 PM PDT 24
Peak memory 201836 kb
Host smart-b2d96bda-cf40-466c-a365-f8ee1f265738
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661154152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gati
ng.661154152
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.915881134
Short name T321
Test name
Test status
Simulation time 554082774183 ps
CPU time 623.26 seconds
Started Jun 02 02:46:08 PM PDT 24
Finished Jun 02 02:56:34 PM PDT 24
Peak memory 201704 kb
Host smart-ca3c1114-552c-41ba-9412-1850432f4cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915881134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.915881134
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.1474815458
Short name T96
Test name
Test status
Simulation time 383441660703 ps
CPU time 599.32 seconds
Started Jun 02 02:46:27 PM PDT 24
Finished Jun 02 02:56:28 PM PDT 24
Peak memory 217824 kb
Host smart-b806721b-8bf0-49f8-89b2-0e599f6308a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474815458 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.1474815458
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.1647452526
Short name T216
Test name
Test status
Simulation time 176371184272 ps
CPU time 95.96 seconds
Started Jun 02 02:46:52 PM PDT 24
Finished Jun 02 02:48:29 PM PDT 24
Peak memory 201860 kb
Host smart-b5001cb6-61d5-4b54-96d9-54c4aae52249
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647452526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.1647452526
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.875538190
Short name T292
Test name
Test status
Simulation time 385081350478 ps
CPU time 979.16 seconds
Started Jun 02 02:45:42 PM PDT 24
Finished Jun 02 03:02:01 PM PDT 24
Peak memory 201844 kb
Host smart-efcdcc2e-d649-45ae-b333-b8e26a97df65
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875538190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_w
akeup.875538190
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.1311528181
Short name T1
Test name
Test status
Simulation time 81423469073 ps
CPU time 307.96 seconds
Started Jun 02 02:45:33 PM PDT 24
Finished Jun 02 02:50:42 PM PDT 24
Peak memory 202072 kb
Host smart-34ab8165-6979-421b-912e-d68a4ce1b7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311528181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.1311528181
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1031930152
Short name T118
Test name
Test status
Simulation time 2295982036 ps
CPU time 2.74 seconds
Started Jun 02 02:42:37 PM PDT 24
Finished Jun 02 02:42:40 PM PDT 24
Peak memory 201924 kb
Host smart-463afa81-7281-4678-a02e-fbf0596538ab
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031930152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.1031930152
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.39206927
Short name T124
Test name
Test status
Simulation time 53221356059 ps
CPU time 57.85 seconds
Started Jun 02 02:42:37 PM PDT 24
Finished Jun 02 02:43:35 PM PDT 24
Peak memory 201960 kb
Host smart-3bc54468-7fe9-48a7-98c7-adfa434b4f37
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39206927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_ba
sh.39206927
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.1985380521
Short name T117
Test name
Test status
Simulation time 1243388682 ps
CPU time 3.67 seconds
Started Jun 02 02:42:33 PM PDT 24
Finished Jun 02 02:42:38 PM PDT 24
Peak memory 201652 kb
Host smart-95170229-3d0b-4b8f-988b-0236d6d7170c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985380521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.1985380521
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1640217273
Short name T876
Test name
Test status
Simulation time 416057775 ps
CPU time 1.3 seconds
Started Jun 02 02:42:36 PM PDT 24
Finished Jun 02 02:42:38 PM PDT 24
Peak memory 201764 kb
Host smart-636fe6fb-c4e7-4660-a7ce-b160931d4c67
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640217273 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.1640217273
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.3034197506
Short name T873
Test name
Test status
Simulation time 373542221 ps
CPU time 1.05 seconds
Started Jun 02 02:42:36 PM PDT 24
Finished Jun 02 02:42:38 PM PDT 24
Peak memory 201680 kb
Host smart-6a3ca21e-c328-4d61-8045-76c621c5e74c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034197506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.3034197506
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.190782689
Short name T906
Test name
Test status
Simulation time 4748646016 ps
CPU time 3.8 seconds
Started Jun 02 02:42:36 PM PDT 24
Finished Jun 02 02:42:40 PM PDT 24
Peak memory 201880 kb
Host smart-43317c25-8c80-425f-b704-f5362ed6f540
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190782689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ct
rl_same_csr_outstanding.190782689
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2658553140
Short name T65
Test name
Test status
Simulation time 414683992 ps
CPU time 2.43 seconds
Started Jun 02 02:42:34 PM PDT 24
Finished Jun 02 02:42:37 PM PDT 24
Peak memory 201928 kb
Host smart-33bd1c1d-b2ec-4ce4-ab52-bcb43a92541a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658553140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.2658553140
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3090092469
Short name T51
Test name
Test status
Simulation time 9060009798 ps
CPU time 8.29 seconds
Started Jun 02 02:42:36 PM PDT 24
Finished Jun 02 02:42:45 PM PDT 24
Peak memory 201948 kb
Host smart-d92de99e-77eb-47b8-bf6c-513bf4d6e13c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090092469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.3090092469
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3176864388
Short name T822
Test name
Test status
Simulation time 843412618 ps
CPU time 2.41 seconds
Started Jun 02 02:42:41 PM PDT 24
Finished Jun 02 02:42:44 PM PDT 24
Peak memory 201836 kb
Host smart-b75c2663-dfdc-4d5e-bba3-ed2bac96b97b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176864388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.3176864388
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2233551281
Short name T119
Test name
Test status
Simulation time 52340489918 ps
CPU time 101.24 seconds
Started Jun 02 02:42:35 PM PDT 24
Finished Jun 02 02:44:18 PM PDT 24
Peak memory 201968 kb
Host smart-c001a2c1-431f-4460-8580-2c508d6b3ced
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233551281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.2233551281
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3183577653
Short name T895
Test name
Test status
Simulation time 781832399 ps
CPU time 1.17 seconds
Started Jun 02 02:42:35 PM PDT 24
Finished Jun 02 02:42:37 PM PDT 24
Peak memory 201716 kb
Host smart-fb2efef2-4d4d-4af9-850a-bc8e9c087ccb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183577653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.3183577653
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.20659628
Short name T58
Test name
Test status
Simulation time 595917828 ps
CPU time 1.67 seconds
Started Jun 02 02:42:43 PM PDT 24
Finished Jun 02 02:42:45 PM PDT 24
Peak memory 201728 kb
Host smart-5a0fe9a5-6f71-4a42-9cb8-5f5b26d8261c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20659628 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.20659628
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.4178625371
Short name T818
Test name
Test status
Simulation time 374484757 ps
CPU time 1.57 seconds
Started Jun 02 02:42:33 PM PDT 24
Finished Jun 02 02:42:36 PM PDT 24
Peak memory 201688 kb
Host smart-9cbf6077-a91b-46a5-bac4-e96f8031656d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178625371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.4178625371
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1573099337
Short name T844
Test name
Test status
Simulation time 385262177 ps
CPU time 1.52 seconds
Started Jun 02 02:42:34 PM PDT 24
Finished Jun 02 02:42:37 PM PDT 24
Peak memory 201644 kb
Host smart-44fba4ac-8e85-4092-b262-7c5a75366d2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573099337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.1573099337
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.494096622
Short name T841
Test name
Test status
Simulation time 4427608301 ps
CPU time 8.25 seconds
Started Jun 02 02:42:43 PM PDT 24
Finished Jun 02 02:42:52 PM PDT 24
Peak memory 201940 kb
Host smart-d2d71748-2e82-4aa4-9642-59df54ceea56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494096622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ct
rl_same_csr_outstanding.494096622
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3178645569
Short name T878
Test name
Test status
Simulation time 560264641 ps
CPU time 1.61 seconds
Started Jun 02 02:42:48 PM PDT 24
Finished Jun 02 02:42:51 PM PDT 24
Peak memory 201696 kb
Host smart-c1eb8819-5c78-4abf-ac55-0e6786eb25cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178645569 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.3178645569
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3116051546
Short name T114
Test name
Test status
Simulation time 422893106 ps
CPU time 1.83 seconds
Started Jun 02 02:42:48 PM PDT 24
Finished Jun 02 02:42:51 PM PDT 24
Peak memory 201644 kb
Host smart-0add3c8a-bfc0-459b-8f35-22d7b7058927
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116051546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.3116051546
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1890992466
Short name T824
Test name
Test status
Simulation time 441900678 ps
CPU time 1.14 seconds
Started Jun 02 02:42:51 PM PDT 24
Finished Jun 02 02:42:53 PM PDT 24
Peak memory 201708 kb
Host smart-ea7334f3-a19c-490c-a98a-0fb9abd6a38d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890992466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.1890992466
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3706056310
Short name T835
Test name
Test status
Simulation time 2104683946 ps
CPU time 7.7 seconds
Started Jun 02 02:42:49 PM PDT 24
Finished Jun 02 02:42:57 PM PDT 24
Peak memory 201708 kb
Host smart-657bc796-dd5c-4e7e-889f-9d74b17aa116
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706056310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.3706056310
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.366884437
Short name T860
Test name
Test status
Simulation time 615577410 ps
CPU time 3.92 seconds
Started Jun 02 02:42:47 PM PDT 24
Finished Jun 02 02:42:51 PM PDT 24
Peak memory 211108 kb
Host smart-e0f459ca-9c88-4f0b-949a-7cca65883638
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366884437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.366884437
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3349412304
Short name T882
Test name
Test status
Simulation time 8518775868 ps
CPU time 7.42 seconds
Started Jun 02 02:42:51 PM PDT 24
Finished Jun 02 02:42:59 PM PDT 24
Peak memory 201944 kb
Host smart-74d14194-0ae4-47a2-8ec9-bde7ddf8360e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349412304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.3349412304
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3376139745
Short name T872
Test name
Test status
Simulation time 719712954 ps
CPU time 1.01 seconds
Started Jun 02 02:42:51 PM PDT 24
Finished Jun 02 02:42:53 PM PDT 24
Peak memory 201984 kb
Host smart-324307f7-8e83-4ddd-916a-eb8a48fe22f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376139745 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.3376139745
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1767173353
Short name T910
Test name
Test status
Simulation time 484357112 ps
CPU time 0.98 seconds
Started Jun 02 02:42:46 PM PDT 24
Finished Jun 02 02:42:47 PM PDT 24
Peak memory 201684 kb
Host smart-de418a1e-8c98-4f03-af5e-23ac3e2cfd8d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767173353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.1767173353
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3596794623
Short name T831
Test name
Test status
Simulation time 472787610 ps
CPU time 0.77 seconds
Started Jun 02 02:42:56 PM PDT 24
Finished Jun 02 02:42:57 PM PDT 24
Peak memory 201628 kb
Host smart-e18cd461-1f32-4062-9bf7-276e31420825
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596794623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.3596794623
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2779408987
Short name T915
Test name
Test status
Simulation time 4212883439 ps
CPU time 11.65 seconds
Started Jun 02 02:42:51 PM PDT 24
Finished Jun 02 02:43:03 PM PDT 24
Peak memory 201936 kb
Host smart-91ba94d1-824e-470d-a9f6-42e3bc6e65ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779408987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.2779408987
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.923139874
Short name T902
Test name
Test status
Simulation time 416008218 ps
CPU time 2.68 seconds
Started Jun 02 02:42:51 PM PDT 24
Finished Jun 02 02:42:54 PM PDT 24
Peak memory 210132 kb
Host smart-379cbb7b-eaa0-4641-a8c9-f96f6deb3f57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923139874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.923139874
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3703262856
Short name T834
Test name
Test status
Simulation time 4074088583 ps
CPU time 10.33 seconds
Started Jun 02 02:42:52 PM PDT 24
Finished Jun 02 02:43:03 PM PDT 24
Peak memory 201980 kb
Host smart-c03fefbd-79d4-415a-9cb7-46520ea367f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703262856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.3703262856
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.1857342468
Short name T896
Test name
Test status
Simulation time 503948917 ps
CPU time 1.25 seconds
Started Jun 02 02:42:49 PM PDT 24
Finished Jun 02 02:42:51 PM PDT 24
Peak memory 201844 kb
Host smart-07a481a9-3a24-4bfb-aebb-445f8fd1bc38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857342468 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.1857342468
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1266978214
Short name T865
Test name
Test status
Simulation time 470249480 ps
CPU time 1.92 seconds
Started Jun 02 02:42:48 PM PDT 24
Finished Jun 02 02:42:51 PM PDT 24
Peak memory 201692 kb
Host smart-990163d2-a1da-4e8e-ac61-4df433ffc6ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266978214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.1266978214
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.45497318
Short name T848
Test name
Test status
Simulation time 407643262 ps
CPU time 0.71 seconds
Started Jun 02 02:42:50 PM PDT 24
Finished Jun 02 02:42:51 PM PDT 24
Peak memory 201924 kb
Host smart-0cb40aab-533e-4c0f-8ade-23d2188faacf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45497318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.45497318
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.158670987
Short name T122
Test name
Test status
Simulation time 4067318780 ps
CPU time 10.97 seconds
Started Jun 02 02:42:48 PM PDT 24
Finished Jun 02 02:43:00 PM PDT 24
Peak memory 201904 kb
Host smart-876ce5f3-eed6-47ee-9162-119c2c806342
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158670987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_c
trl_same_csr_outstanding.158670987
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.2818447673
Short name T826
Test name
Test status
Simulation time 348409657 ps
CPU time 1.81 seconds
Started Jun 02 02:42:51 PM PDT 24
Finished Jun 02 02:42:53 PM PDT 24
Peak memory 201976 kb
Host smart-d32efa27-05b8-4643-83d0-9be8c4e7f407
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818447673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.2818447673
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3070611613
Short name T819
Test name
Test status
Simulation time 7762976353 ps
CPU time 21.41 seconds
Started Jun 02 02:42:50 PM PDT 24
Finished Jun 02 02:43:12 PM PDT 24
Peak memory 201984 kb
Host smart-358427c4-f357-41b5-9a6a-069b196ccdca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070611613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.3070611613
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.780036653
Short name T905
Test name
Test status
Simulation time 449912530 ps
CPU time 1.42 seconds
Started Jun 02 02:42:51 PM PDT 24
Finished Jun 02 02:42:53 PM PDT 24
Peak memory 201740 kb
Host smart-5e81f922-d269-4393-b7a0-05d87ab073e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780036653 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.780036653
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1034781746
Short name T859
Test name
Test status
Simulation time 532067469 ps
CPU time 1.4 seconds
Started Jun 02 02:42:52 PM PDT 24
Finished Jun 02 02:42:54 PM PDT 24
Peak memory 201576 kb
Host smart-699ca3eb-518d-492f-91f6-56412576e228
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034781746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.1034781746
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3960808053
Short name T866
Test name
Test status
Simulation time 451878455 ps
CPU time 1.69 seconds
Started Jun 02 02:42:46 PM PDT 24
Finished Jun 02 02:42:49 PM PDT 24
Peak memory 201608 kb
Host smart-f3977e04-6ccf-4df4-aca4-21a3d9538dcf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960808053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.3960808053
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1758501419
Short name T904
Test name
Test status
Simulation time 1938802421 ps
CPU time 2.04 seconds
Started Jun 02 02:42:48 PM PDT 24
Finished Jun 02 02:42:51 PM PDT 24
Peak memory 201700 kb
Host smart-12e8c90d-de4f-46f5-9621-71c740244350
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758501419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.1758501419
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2057756927
Short name T845
Test name
Test status
Simulation time 477011996 ps
CPU time 3.35 seconds
Started Jun 02 02:42:48 PM PDT 24
Finished Jun 02 02:42:52 PM PDT 24
Peak memory 201956 kb
Host smart-be6839d6-56da-4163-9155-54c9503d6c50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057756927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.2057756927
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2438743802
Short name T71
Test name
Test status
Simulation time 4163605906 ps
CPU time 4.12 seconds
Started Jun 02 02:42:53 PM PDT 24
Finished Jun 02 02:42:58 PM PDT 24
Peak memory 201924 kb
Host smart-96593c11-9943-4af8-95b6-1da277344e45
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438743802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.2438743802
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.4281483630
Short name T862
Test name
Test status
Simulation time 526909624 ps
CPU time 1.07 seconds
Started Jun 02 02:42:47 PM PDT 24
Finished Jun 02 02:42:50 PM PDT 24
Peak memory 201584 kb
Host smart-37d3c1d5-33e1-4b00-b2ea-e8468108f9dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281483630 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.4281483630
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1734440451
Short name T871
Test name
Test status
Simulation time 442707677 ps
CPU time 1.85 seconds
Started Jun 02 02:42:49 PM PDT 24
Finished Jun 02 02:42:52 PM PDT 24
Peak memory 201636 kb
Host smart-b035c318-00c9-418f-b23a-348ebf5ccab7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734440451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.1734440451
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.198095329
Short name T815
Test name
Test status
Simulation time 518610373 ps
CPU time 1.86 seconds
Started Jun 02 02:42:48 PM PDT 24
Finished Jun 02 02:42:51 PM PDT 24
Peak memory 201604 kb
Host smart-5ad7bd26-1c1c-40d7-8914-a9a8047f7256
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198095329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.198095329
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3444222639
Short name T837
Test name
Test status
Simulation time 4340029736 ps
CPU time 21.67 seconds
Started Jun 02 02:42:53 PM PDT 24
Finished Jun 02 02:43:16 PM PDT 24
Peak memory 201972 kb
Host smart-69b04419-b9ef-4cd2-a864-f6b0b0a577b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444222639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.3444222639
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1026648858
Short name T870
Test name
Test status
Simulation time 342360510 ps
CPU time 3.03 seconds
Started Jun 02 02:42:47 PM PDT 24
Finished Jun 02 02:42:51 PM PDT 24
Peak memory 218232 kb
Host smart-5e5514ad-e2f2-4cf3-bc34-30064603eb9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026648858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.1026648858
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.407123355
Short name T851
Test name
Test status
Simulation time 8765058375 ps
CPU time 13.41 seconds
Started Jun 02 02:42:49 PM PDT 24
Finished Jun 02 02:43:03 PM PDT 24
Peak memory 201924 kb
Host smart-4223190d-a5c2-4fca-b98b-490ad1512c53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407123355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_in
tg_err.407123355
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1692367605
Short name T86
Test name
Test status
Simulation time 822986261 ps
CPU time 1.14 seconds
Started Jun 02 02:42:50 PM PDT 24
Finished Jun 02 02:42:51 PM PDT 24
Peak memory 201724 kb
Host smart-9b035bb1-d62e-4d2f-ae57-779879c43fe5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692367605 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.1692367605
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2393783224
Short name T105
Test name
Test status
Simulation time 401844751 ps
CPU time 1.19 seconds
Started Jun 02 02:42:53 PM PDT 24
Finished Jun 02 02:42:55 PM PDT 24
Peak memory 201696 kb
Host smart-4d2d63a1-2c07-4d65-8d41-a1070365d505
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393783224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.2393783224
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.2545843687
Short name T836
Test name
Test status
Simulation time 353753157 ps
CPU time 1.21 seconds
Started Jun 02 02:42:53 PM PDT 24
Finished Jun 02 02:42:55 PM PDT 24
Peak memory 201684 kb
Host smart-8b913c5f-c39c-42c2-85ed-21bed35ff249
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545843687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.2545843687
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1280322545
Short name T46
Test name
Test status
Simulation time 5188839911 ps
CPU time 4.22 seconds
Started Jun 02 02:42:53 PM PDT 24
Finished Jun 02 02:42:59 PM PDT 24
Peak memory 201884 kb
Host smart-31b57eda-2152-41ab-ba7f-c08c6fcb539e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280322545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.1280322545
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.4115467154
Short name T842
Test name
Test status
Simulation time 554211163 ps
CPU time 2.77 seconds
Started Jun 02 02:42:49 PM PDT 24
Finished Jun 02 02:42:52 PM PDT 24
Peak memory 201900 kb
Host smart-c4a3463c-a1fd-44bc-8d2b-ab67e561c9a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115467154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.4115467154
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.583966355
Short name T856
Test name
Test status
Simulation time 8724557639 ps
CPU time 7.72 seconds
Started Jun 02 02:42:53 PM PDT 24
Finished Jun 02 02:43:02 PM PDT 24
Peak memory 201956 kb
Host smart-223fcec4-706b-4f0a-8393-e3e6d464a538
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583966355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_in
tg_err.583966355
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.3610556216
Short name T821
Test name
Test status
Simulation time 604586991 ps
CPU time 2.29 seconds
Started Jun 02 02:42:57 PM PDT 24
Finished Jun 02 02:43:00 PM PDT 24
Peak memory 201744 kb
Host smart-cf3c3fb9-f497-4589-86d4-8b490d739c18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610556216 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.3610556216
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3474162038
Short name T103
Test name
Test status
Simulation time 348459408 ps
CPU time 0.97 seconds
Started Jun 02 02:42:55 PM PDT 24
Finished Jun 02 02:42:57 PM PDT 24
Peak memory 201704 kb
Host smart-20ac814c-44f3-4bf4-bb37-4751e9b56276
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474162038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.3474162038
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3884085349
Short name T849
Test name
Test status
Simulation time 513330330 ps
CPU time 1.71 seconds
Started Jun 02 02:42:53 PM PDT 24
Finished Jun 02 02:42:55 PM PDT 24
Peak memory 201664 kb
Host smart-2097bef5-43c7-40dc-b8c3-67a653c6d76f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884085349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.3884085349
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.3269993449
Short name T123
Test name
Test status
Simulation time 2351733422 ps
CPU time 2.78 seconds
Started Jun 02 02:42:54 PM PDT 24
Finished Jun 02 02:42:58 PM PDT 24
Peak memory 201764 kb
Host smart-3456b9c8-b07b-4d27-a62c-795781f7256b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269993449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.3269993449
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2718987739
Short name T879
Test name
Test status
Simulation time 1628396131 ps
CPU time 1.72 seconds
Started Jun 02 02:42:56 PM PDT 24
Finished Jun 02 02:42:58 PM PDT 24
Peak memory 201908 kb
Host smart-b9f7e447-bf75-444b-a931-abd7b030d019
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718987739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.2718987739
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3999586052
Short name T70
Test name
Test status
Simulation time 4483719078 ps
CPU time 11.86 seconds
Started Jun 02 02:42:53 PM PDT 24
Finished Jun 02 02:43:06 PM PDT 24
Peak memory 201660 kb
Host smart-8c9f1807-fb72-4287-97c1-434259a6fb24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999586052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.3999586052
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1202545683
Short name T886
Test name
Test status
Simulation time 801952425 ps
CPU time 1.13 seconds
Started Jun 02 02:42:54 PM PDT 24
Finished Jun 02 02:42:56 PM PDT 24
Peak memory 201728 kb
Host smart-1ffb1a76-f9f2-4368-a2ad-5d0c814c76dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202545683 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.1202545683
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3202593211
Short name T113
Test name
Test status
Simulation time 404953865 ps
CPU time 1.03 seconds
Started Jun 02 02:42:55 PM PDT 24
Finished Jun 02 02:42:57 PM PDT 24
Peak memory 201624 kb
Host smart-e7a1d563-a782-4cd3-b6c3-e3c287f544a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202593211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.3202593211
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3992252984
Short name T816
Test name
Test status
Simulation time 384327047 ps
CPU time 1.57 seconds
Started Jun 02 02:42:53 PM PDT 24
Finished Jun 02 02:42:56 PM PDT 24
Peak memory 201688 kb
Host smart-3c92ed12-f0cf-4136-8dcb-7ec49c13b866
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992252984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.3992252984
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.2056545871
Short name T897
Test name
Test status
Simulation time 2822487522 ps
CPU time 3.76 seconds
Started Jun 02 02:42:52 PM PDT 24
Finished Jun 02 02:42:57 PM PDT 24
Peak memory 201756 kb
Host smart-34a9dd22-443d-43c4-8263-2a3336f85fd2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056545871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.2056545871
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2116178970
Short name T823
Test name
Test status
Simulation time 852909986 ps
CPU time 3.44 seconds
Started Jun 02 02:42:53 PM PDT 24
Finished Jun 02 02:42:57 PM PDT 24
Peak memory 209964 kb
Host smart-3e800b19-8851-406e-b987-ce1e03588696
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116178970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.2116178970
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3381122107
Short name T72
Test name
Test status
Simulation time 8152184114 ps
CPU time 12.72 seconds
Started Jun 02 02:42:53 PM PDT 24
Finished Jun 02 02:43:07 PM PDT 24
Peak memory 201972 kb
Host smart-b0c7f545-8230-4451-8c90-6a450b07f312
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381122107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.3381122107
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.858664512
Short name T875
Test name
Test status
Simulation time 470705752 ps
CPU time 1.19 seconds
Started Jun 02 02:42:55 PM PDT 24
Finished Jun 02 02:42:57 PM PDT 24
Peak memory 201676 kb
Host smart-296f9915-cf1c-4df4-b3bc-94031131e412
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858664512 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.858664512
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.1843029364
Short name T111
Test name
Test status
Simulation time 427603480 ps
CPU time 0.95 seconds
Started Jun 02 02:42:53 PM PDT 24
Finished Jun 02 02:42:55 PM PDT 24
Peak memory 201628 kb
Host smart-e418b910-2763-423c-b06e-fd63f482f23b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843029364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.1843029364
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.3413683151
Short name T828
Test name
Test status
Simulation time 292548870 ps
CPU time 1.32 seconds
Started Jun 02 02:43:05 PM PDT 24
Finished Jun 02 02:43:07 PM PDT 24
Peak memory 201616 kb
Host smart-8cfef3e2-46c9-4fe6-bd85-8fdbe0efc556
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413683151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.3413683151
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1249753183
Short name T888
Test name
Test status
Simulation time 4085804219 ps
CPU time 2.45 seconds
Started Jun 02 02:42:54 PM PDT 24
Finished Jun 02 02:42:57 PM PDT 24
Peak memory 201904 kb
Host smart-6ccf132a-ed76-481e-b692-97bd9fd76d52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249753183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.1249753183
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1429808182
Short name T57
Test name
Test status
Simulation time 510513156 ps
CPU time 4.01 seconds
Started Jun 02 02:42:52 PM PDT 24
Finished Jun 02 02:42:57 PM PDT 24
Peak memory 201996 kb
Host smart-bfd269d0-2736-4e5b-9525-f9924dc1baf3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429808182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.1429808182
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.874198731
Short name T854
Test name
Test status
Simulation time 4561557856 ps
CPU time 11.35 seconds
Started Jun 02 02:43:05 PM PDT 24
Finished Jun 02 02:43:17 PM PDT 24
Peak memory 201864 kb
Host smart-4a7c1279-753d-4830-bd3d-23cce34e211f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874198731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_in
tg_err.874198731
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1351661719
Short name T867
Test name
Test status
Simulation time 365223474 ps
CPU time 1.71 seconds
Started Jun 02 02:42:52 PM PDT 24
Finished Jun 02 02:42:55 PM PDT 24
Peak memory 201724 kb
Host smart-1d8f69ac-50b7-4191-834b-24ac6b7fa5b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351661719 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.1351661719
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1767737190
Short name T909
Test name
Test status
Simulation time 445777474 ps
CPU time 1.08 seconds
Started Jun 02 02:42:53 PM PDT 24
Finished Jun 02 02:42:55 PM PDT 24
Peak memory 201708 kb
Host smart-40cd64f9-2cce-440a-a6fd-30f9d9fb5ffa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767737190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.1767737190
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2220425200
Short name T830
Test name
Test status
Simulation time 457239027 ps
CPU time 1.31 seconds
Started Jun 02 02:42:52 PM PDT 24
Finished Jun 02 02:42:55 PM PDT 24
Peak memory 201632 kb
Host smart-e2331eb4-ef80-4bde-98cc-9218a03f2a3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220425200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.2220425200
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1205493102
Short name T907
Test name
Test status
Simulation time 3037999899 ps
CPU time 1.48 seconds
Started Jun 02 02:42:52 PM PDT 24
Finished Jun 02 02:42:55 PM PDT 24
Peak memory 201960 kb
Host smart-36dceda3-cbab-4000-935d-25e663abab58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205493102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.1205493102
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2045533844
Short name T61
Test name
Test status
Simulation time 534343711 ps
CPU time 2.65 seconds
Started Jun 02 02:42:53 PM PDT 24
Finished Jun 02 02:42:57 PM PDT 24
Peak memory 218312 kb
Host smart-36e480b6-1710-4ec1-93a2-25e442e85a22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045533844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.2045533844
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3840847651
Short name T49
Test name
Test status
Simulation time 4770745324 ps
CPU time 3.07 seconds
Started Jun 02 02:42:59 PM PDT 24
Finished Jun 02 02:43:02 PM PDT 24
Peak memory 201936 kb
Host smart-27a68fd0-07bc-4ff3-abf8-de44cb21ae0c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840847651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.3840847651
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2184129085
Short name T110
Test name
Test status
Simulation time 451256180 ps
CPU time 2.59 seconds
Started Jun 02 02:42:43 PM PDT 24
Finished Jun 02 02:42:46 PM PDT 24
Peak memory 201856 kb
Host smart-c4caf28f-360f-4b67-b729-2b4e68a6f8c8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184129085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.2184129085
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1998923788
Short name T112
Test name
Test status
Simulation time 52048714913 ps
CPU time 85.33 seconds
Started Jun 02 02:42:44 PM PDT 24
Finished Jun 02 02:44:10 PM PDT 24
Peak memory 201936 kb
Host smart-19263196-4be4-491d-b9c2-adcd54bb59f9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998923788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.1998923788
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3851204406
Short name T106
Test name
Test status
Simulation time 780482129 ps
CPU time 1.15 seconds
Started Jun 02 02:42:43 PM PDT 24
Finished Jun 02 02:42:45 PM PDT 24
Peak memory 201684 kb
Host smart-b470f8f1-22e7-4964-b0e0-da1584cced05
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851204406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.3851204406
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.808537495
Short name T814
Test name
Test status
Simulation time 498554569 ps
CPU time 1.41 seconds
Started Jun 02 02:42:41 PM PDT 24
Finished Jun 02 02:42:43 PM PDT 24
Peak memory 210104 kb
Host smart-42e3e2ad-d59e-44e3-894e-038a81bb0ee1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808537495 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.808537495
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2860466994
Short name T874
Test name
Test status
Simulation time 465370403 ps
CPU time 1.97 seconds
Started Jun 02 02:42:40 PM PDT 24
Finished Jun 02 02:42:42 PM PDT 24
Peak memory 201636 kb
Host smart-3129ccb3-b428-4b27-8d01-f294906db7a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860466994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.2860466994
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3846256332
Short name T813
Test name
Test status
Simulation time 292695680 ps
CPU time 1.36 seconds
Started Jun 02 02:42:43 PM PDT 24
Finished Jun 02 02:42:45 PM PDT 24
Peak memory 201684 kb
Host smart-37689add-c350-4d77-8aa6-529ab6fc4b10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846256332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.3846256332
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2119441078
Short name T908
Test name
Test status
Simulation time 2493134473 ps
CPU time 3.91 seconds
Started Jun 02 02:42:42 PM PDT 24
Finished Jun 02 02:42:47 PM PDT 24
Peak memory 201700 kb
Host smart-9e26e0c6-ab81-4fbc-8ac7-d1bce8eb60cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119441078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.2119441078
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2172277503
Short name T838
Test name
Test status
Simulation time 1731709656 ps
CPU time 2.69 seconds
Started Jun 02 02:42:42 PM PDT 24
Finished Jun 02 02:42:46 PM PDT 24
Peak memory 201936 kb
Host smart-6584252e-408f-40df-8595-c98e18b1716b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172277503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.2172277503
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.4048500185
Short name T883
Test name
Test status
Simulation time 484676448 ps
CPU time 0.95 seconds
Started Jun 02 02:42:57 PM PDT 24
Finished Jun 02 02:42:59 PM PDT 24
Peak memory 201800 kb
Host smart-f7c2bcca-3034-4898-b6de-759141efd36c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048500185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.4048500185
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.4293141536
Short name T827
Test name
Test status
Simulation time 512434887 ps
CPU time 1.81 seconds
Started Jun 02 02:42:55 PM PDT 24
Finished Jun 02 02:42:58 PM PDT 24
Peak memory 201668 kb
Host smart-cb1a7a14-1d44-4007-b73f-0c0ba72cc52f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293141536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.4293141536
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.3862012387
Short name T880
Test name
Test status
Simulation time 316301723 ps
CPU time 0.96 seconds
Started Jun 02 02:42:53 PM PDT 24
Finished Jun 02 02:42:55 PM PDT 24
Peak memory 201652 kb
Host smart-42fe81b3-a590-4b71-9527-9a4729ecbc70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862012387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.3862012387
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.697327936
Short name T900
Test name
Test status
Simulation time 381374331 ps
CPU time 0.84 seconds
Started Jun 02 02:43:05 PM PDT 24
Finished Jun 02 02:43:06 PM PDT 24
Peak memory 201628 kb
Host smart-0a4e9257-494c-4576-acaf-d3ef700d9e50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697327936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.697327936
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.2202242660
Short name T863
Test name
Test status
Simulation time 536353794 ps
CPU time 1.31 seconds
Started Jun 02 02:42:53 PM PDT 24
Finished Jun 02 02:42:56 PM PDT 24
Peak memory 201600 kb
Host smart-dfb11142-2ced-4936-8152-e5b4fcec8a9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202242660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.2202242660
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2503688580
Short name T817
Test name
Test status
Simulation time 474279226 ps
CPU time 1.09 seconds
Started Jun 02 02:42:53 PM PDT 24
Finished Jun 02 02:42:55 PM PDT 24
Peak memory 201688 kb
Host smart-bd04b404-024d-4b8b-8c38-6a3b2cd4b589
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503688580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.2503688580
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.291857070
Short name T850
Test name
Test status
Simulation time 348948286 ps
CPU time 0.83 seconds
Started Jun 02 02:42:53 PM PDT 24
Finished Jun 02 02:42:56 PM PDT 24
Peak memory 201680 kb
Host smart-d3367e0c-4445-417c-953e-e75ce2570af7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291857070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.291857070
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.1880368319
Short name T920
Test name
Test status
Simulation time 623319403 ps
CPU time 0.72 seconds
Started Jun 02 02:42:52 PM PDT 24
Finished Jun 02 02:42:54 PM PDT 24
Peak memory 201640 kb
Host smart-985c913e-23cc-4062-a8d2-6ac71924636b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880368319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.1880368319
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.322433914
Short name T847
Test name
Test status
Simulation time 356064210 ps
CPU time 0.82 seconds
Started Jun 02 02:43:01 PM PDT 24
Finished Jun 02 02:43:02 PM PDT 24
Peak memory 201676 kb
Host smart-5041f7f8-9374-4118-8eab-f4afd6a85ff7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322433914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.322433914
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1950977886
Short name T806
Test name
Test status
Simulation time 368292585 ps
CPU time 0.86 seconds
Started Jun 02 02:42:53 PM PDT 24
Finished Jun 02 02:42:55 PM PDT 24
Peak memory 201672 kb
Host smart-9d1f4676-85a3-4c92-be3e-3b71d3bab6c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950977886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.1950977886
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2358514848
Short name T109
Test name
Test status
Simulation time 1238184443 ps
CPU time 5.93 seconds
Started Jun 02 02:42:42 PM PDT 24
Finished Jun 02 02:42:49 PM PDT 24
Peak memory 201864 kb
Host smart-5eaad8d3-462e-4e82-8320-17b235383db1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358514848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.2358514848
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2820441513
Short name T107
Test name
Test status
Simulation time 52565610983 ps
CPU time 119.61 seconds
Started Jun 02 02:42:43 PM PDT 24
Finished Jun 02 02:44:44 PM PDT 24
Peak memory 201928 kb
Host smart-d6890f22-10a3-4025-b699-1e51f0c57bed
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820441513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.2820441513
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3161971324
Short name T820
Test name
Test status
Simulation time 937738376 ps
CPU time 1.13 seconds
Started Jun 02 02:42:43 PM PDT 24
Finished Jun 02 02:42:45 PM PDT 24
Peak memory 201624 kb
Host smart-97ac689e-c040-4f6d-be23-0e8b2e18fe5a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161971324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.3161971324
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2276652512
Short name T69
Test name
Test status
Simulation time 545562995 ps
CPU time 2.19 seconds
Started Jun 02 02:42:43 PM PDT 24
Finished Jun 02 02:42:46 PM PDT 24
Peak memory 201768 kb
Host smart-6c9957e9-dd26-411b-81c4-8375122c0dba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276652512 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.2276652512
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.779221694
Short name T917
Test name
Test status
Simulation time 563427488 ps
CPU time 1.12 seconds
Started Jun 02 02:42:41 PM PDT 24
Finished Jun 02 02:42:42 PM PDT 24
Peak memory 201648 kb
Host smart-80cba536-85b5-499f-834c-67a72d6d109b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779221694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.779221694
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.4273470736
Short name T825
Test name
Test status
Simulation time 284918286 ps
CPU time 0.99 seconds
Started Jun 02 02:42:41 PM PDT 24
Finished Jun 02 02:42:43 PM PDT 24
Peak memory 201660 kb
Host smart-caf3453f-7089-420c-9051-dcfe91d9af67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273470736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.4273470736
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2849054829
Short name T44
Test name
Test status
Simulation time 5123417435 ps
CPU time 4.42 seconds
Started Jun 02 02:42:44 PM PDT 24
Finished Jun 02 02:42:49 PM PDT 24
Peak memory 201932 kb
Host smart-08085754-6797-4efc-83bf-33b7fbc893aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849054829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.2849054829
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.1183379923
Short name T885
Test name
Test status
Simulation time 526683832 ps
CPU time 1.78 seconds
Started Jun 02 02:42:46 PM PDT 24
Finished Jun 02 02:42:48 PM PDT 24
Peak memory 201940 kb
Host smart-09f31d2d-5022-4385-a995-10e28e758459
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183379923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.1183379923
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1553420161
Short name T53
Test name
Test status
Simulation time 4178986459 ps
CPU time 7.23 seconds
Started Jun 02 02:42:50 PM PDT 24
Finished Jun 02 02:42:58 PM PDT 24
Peak memory 201984 kb
Host smart-89255f71-afd3-4c0e-b4eb-6d1f24da8f86
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553420161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.1553420161
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.248313182
Short name T912
Test name
Test status
Simulation time 457484243 ps
CPU time 1.65 seconds
Started Jun 02 02:42:53 PM PDT 24
Finished Jun 02 02:42:56 PM PDT 24
Peak memory 201648 kb
Host smart-bef254d3-900f-4e1e-875a-9150d807adf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248313182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.248313182
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1839318432
Short name T877
Test name
Test status
Simulation time 502365296 ps
CPU time 0.93 seconds
Started Jun 02 02:42:56 PM PDT 24
Finished Jun 02 02:42:58 PM PDT 24
Peak memory 201572 kb
Host smart-700e1bc8-90a2-4b5d-95f4-1c04b132d52b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839318432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.1839318432
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.3463122785
Short name T811
Test name
Test status
Simulation time 344631246 ps
CPU time 1.55 seconds
Started Jun 02 02:42:54 PM PDT 24
Finished Jun 02 02:42:57 PM PDT 24
Peak memory 201628 kb
Host smart-3db8ff0a-9ab0-41d2-bec6-8d082ce6f3d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463122785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.3463122785
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1451111493
Short name T804
Test name
Test status
Simulation time 514436636 ps
CPU time 0.93 seconds
Started Jun 02 02:42:54 PM PDT 24
Finished Jun 02 02:42:56 PM PDT 24
Peak memory 201680 kb
Host smart-e391fbc6-b85f-446d-9acf-57651308aed6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451111493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.1451111493
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2575138509
Short name T809
Test name
Test status
Simulation time 496551304 ps
CPU time 1.1 seconds
Started Jun 02 02:42:57 PM PDT 24
Finished Jun 02 02:42:59 PM PDT 24
Peak memory 201800 kb
Host smart-9952114c-f5d9-426e-b110-f5bf45f1aefe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575138509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.2575138509
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.367904264
Short name T916
Test name
Test status
Simulation time 340797482 ps
CPU time 1.08 seconds
Started Jun 02 02:42:53 PM PDT 24
Finished Jun 02 02:42:55 PM PDT 24
Peak memory 201932 kb
Host smart-34b911bb-b8db-4bf0-996a-bf0b802e277f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367904264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.367904264
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.235713845
Short name T832
Test name
Test status
Simulation time 530594158 ps
CPU time 0.89 seconds
Started Jun 02 02:42:57 PM PDT 24
Finished Jun 02 02:42:59 PM PDT 24
Peak memory 201668 kb
Host smart-b88bf1c3-25e1-4d7c-8252-b0dac0a618a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235713845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.235713845
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.1305656946
Short name T894
Test name
Test status
Simulation time 418410176 ps
CPU time 1.67 seconds
Started Jun 02 02:42:53 PM PDT 24
Finished Jun 02 02:42:56 PM PDT 24
Peak memory 201604 kb
Host smart-7457c3ee-7e30-4eca-a03a-a4a11abd4669
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305656946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.1305656946
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.2683819997
Short name T889
Test name
Test status
Simulation time 379116209 ps
CPU time 0.82 seconds
Started Jun 02 02:43:05 PM PDT 24
Finished Jun 02 02:43:06 PM PDT 24
Peak memory 201620 kb
Host smart-b7575cea-de40-48c7-a92d-e9436582d3fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683819997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.2683819997
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1176426469
Short name T864
Test name
Test status
Simulation time 393188231 ps
CPU time 1.54 seconds
Started Jun 02 02:42:55 PM PDT 24
Finished Jun 02 02:42:57 PM PDT 24
Peak memory 201684 kb
Host smart-2792a892-26f9-48bb-877c-7e0a6aba2963
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176426469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.1176426469
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1495163565
Short name T893
Test name
Test status
Simulation time 1323941805 ps
CPU time 2.97 seconds
Started Jun 02 02:42:43 PM PDT 24
Finished Jun 02 02:42:47 PM PDT 24
Peak memory 201924 kb
Host smart-0c0c44f6-9208-4f64-932f-e70ecd6be283
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495163565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.1495163565
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2486727112
Short name T108
Test name
Test status
Simulation time 1247695578 ps
CPU time 3.69 seconds
Started Jun 02 02:42:42 PM PDT 24
Finished Jun 02 02:42:47 PM PDT 24
Peak memory 201684 kb
Host smart-32483038-b8e4-4377-b741-95579c62c407
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486727112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.2486727112
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.476848241
Short name T914
Test name
Test status
Simulation time 566862530 ps
CPU time 1.67 seconds
Started Jun 02 02:42:41 PM PDT 24
Finished Jun 02 02:42:44 PM PDT 24
Peak memory 201752 kb
Host smart-aa0dd142-9a7e-4163-8f75-b5e751ff6065
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476848241 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.476848241
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3321792909
Short name T881
Test name
Test status
Simulation time 389042997 ps
CPU time 1.05 seconds
Started Jun 02 02:42:42 PM PDT 24
Finished Jun 02 02:42:43 PM PDT 24
Peak memory 201644 kb
Host smart-3f4aa62f-72ac-44dd-84bf-bef44ba93e23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321792909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.3321792909
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2960085422
Short name T805
Test name
Test status
Simulation time 343779602 ps
CPU time 0.78 seconds
Started Jun 02 02:42:41 PM PDT 24
Finished Jun 02 02:42:43 PM PDT 24
Peak memory 201632 kb
Host smart-dec0184b-35f7-4167-a7ab-e782acdddd26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960085422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.2960085422
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1064852501
Short name T892
Test name
Test status
Simulation time 2376634573 ps
CPU time 10.41 seconds
Started Jun 02 02:42:47 PM PDT 24
Finished Jun 02 02:42:58 PM PDT 24
Peak memory 201732 kb
Host smart-c4cfb9be-2703-4bff-a88e-5c021defbb5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064852501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.1064852501
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.64663957
Short name T869
Test name
Test status
Simulation time 2132941059 ps
CPU time 2.96 seconds
Started Jun 02 02:42:42 PM PDT 24
Finished Jun 02 02:42:45 PM PDT 24
Peak memory 217712 kb
Host smart-0dded906-16b8-4e09-b94e-5e5afa0b210e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64663957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.64663957
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2657377318
Short name T903
Test name
Test status
Simulation time 8306992176 ps
CPU time 7.14 seconds
Started Jun 02 02:42:41 PM PDT 24
Finished Jun 02 02:42:49 PM PDT 24
Peak memory 201992 kb
Host smart-bdfcc146-b7b8-4f5a-bf93-894cb3fa783d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657377318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.2657377318
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1862674353
Short name T899
Test name
Test status
Simulation time 297992749 ps
CPU time 0.95 seconds
Started Jun 02 02:42:56 PM PDT 24
Finished Jun 02 02:42:57 PM PDT 24
Peak memory 201652 kb
Host smart-4a451c56-446b-4992-96e6-260ca86f3838
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862674353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.1862674353
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.1577408715
Short name T807
Test name
Test status
Simulation time 479295980 ps
CPU time 1.09 seconds
Started Jun 02 02:42:54 PM PDT 24
Finished Jun 02 02:42:56 PM PDT 24
Peak memory 201652 kb
Host smart-4c9bb05b-9c6f-4d48-b797-6f4c3ae3b1d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577408715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.1577408715
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.3701272873
Short name T846
Test name
Test status
Simulation time 469857858 ps
CPU time 0.91 seconds
Started Jun 02 02:42:53 PM PDT 24
Finished Jun 02 02:42:55 PM PDT 24
Peak memory 201708 kb
Host smart-283ddab1-1d00-433c-a255-4bbb8ca7db12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701272873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.3701272873
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.1315374896
Short name T833
Test name
Test status
Simulation time 322139423 ps
CPU time 1.35 seconds
Started Jun 02 02:42:51 PM PDT 24
Finished Jun 02 02:42:53 PM PDT 24
Peak memory 201624 kb
Host smart-32ef6ed0-7848-4e5c-b4ab-ad253140e499
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315374896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.1315374896
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3939679147
Short name T803
Test name
Test status
Simulation time 426035932 ps
CPU time 0.92 seconds
Started Jun 02 02:42:55 PM PDT 24
Finished Jun 02 02:42:57 PM PDT 24
Peak memory 201668 kb
Host smart-163de5f4-07dd-4163-a2f1-e8c4224c3649
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939679147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.3939679147
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2014211694
Short name T857
Test name
Test status
Simulation time 354797745 ps
CPU time 0.83 seconds
Started Jun 02 02:42:57 PM PDT 24
Finished Jun 02 02:42:59 PM PDT 24
Peak memory 201660 kb
Host smart-679ff35c-5d56-46fa-8e9a-503b0549e156
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014211694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.2014211694
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.812925723
Short name T808
Test name
Test status
Simulation time 308501670 ps
CPU time 0.91 seconds
Started Jun 02 02:42:54 PM PDT 24
Finished Jun 02 02:42:56 PM PDT 24
Peak memory 201716 kb
Host smart-bf9a95c5-2fd1-4ce5-ac02-b8b02ab4c34e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812925723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.812925723
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.1387794413
Short name T853
Test name
Test status
Simulation time 451707413 ps
CPU time 0.9 seconds
Started Jun 02 02:42:53 PM PDT 24
Finished Jun 02 02:42:55 PM PDT 24
Peak memory 201640 kb
Host smart-cb09625c-c4b5-4c9f-8785-44ff6428d785
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387794413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.1387794413
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.990961205
Short name T911
Test name
Test status
Simulation time 416524223 ps
CPU time 1.04 seconds
Started Jun 02 02:42:54 PM PDT 24
Finished Jun 02 02:42:56 PM PDT 24
Peak memory 201684 kb
Host smart-d1bdae21-80ec-45c6-a8dc-c2835bcfe838
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990961205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.990961205
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.1534594821
Short name T812
Test name
Test status
Simulation time 382202462 ps
CPU time 1.54 seconds
Started Jun 02 02:42:53 PM PDT 24
Finished Jun 02 02:42:56 PM PDT 24
Peak memory 201688 kb
Host smart-a20a21f7-b453-4194-bd43-e4a0281a8f21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534594821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.1534594821
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1865697824
Short name T890
Test name
Test status
Simulation time 527547553 ps
CPU time 1.64 seconds
Started Jun 02 02:42:49 PM PDT 24
Finished Jun 02 02:42:51 PM PDT 24
Peak memory 201736 kb
Host smart-e53b022e-2087-4c6f-b4e9-b2ca0f3b2361
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865697824 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.1865697824
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.1030100177
Short name T47
Test name
Test status
Simulation time 406110485 ps
CPU time 1.73 seconds
Started Jun 02 02:42:49 PM PDT 24
Finished Jun 02 02:42:51 PM PDT 24
Peak memory 201704 kb
Host smart-1526ee7b-3b79-45c7-b25b-0214fa9b6044
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030100177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.1030100177
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3499633639
Short name T810
Test name
Test status
Simulation time 403347030 ps
CPU time 0.9 seconds
Started Jun 02 02:42:46 PM PDT 24
Finished Jun 02 02:42:47 PM PDT 24
Peak memory 201708 kb
Host smart-14851590-f6bf-4673-8e57-f42e522df8f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499633639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.3499633639
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3797568300
Short name T45
Test name
Test status
Simulation time 4250172530 ps
CPU time 13.84 seconds
Started Jun 02 02:42:49 PM PDT 24
Finished Jun 02 02:43:04 PM PDT 24
Peak memory 201916 kb
Host smart-9258fce6-2dc5-4242-b9d4-58d3ecee996e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797568300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.3797568300
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1816212354
Short name T829
Test name
Test status
Simulation time 650962275 ps
CPU time 2.41 seconds
Started Jun 02 02:42:44 PM PDT 24
Finished Jun 02 02:42:47 PM PDT 24
Peak memory 201936 kb
Host smart-357eb569-e730-4f45-b71b-5b176a8c551a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816212354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.1816212354
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.4286860495
Short name T66
Test name
Test status
Simulation time 3939668252 ps
CPU time 11.17 seconds
Started Jun 02 02:42:42 PM PDT 24
Finished Jun 02 02:42:54 PM PDT 24
Peak memory 201912 kb
Host smart-e164b304-158d-4093-926a-a619ad19bef8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286860495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.4286860495
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2557953465
Short name T68
Test name
Test status
Simulation time 539643397 ps
CPU time 2.28 seconds
Started Jun 02 02:42:52 PM PDT 24
Finished Jun 02 02:42:55 PM PDT 24
Peak memory 201776 kb
Host smart-0c3f989b-e914-4ea2-b738-2643558d73e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557953465 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.2557953465
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.1091443953
Short name T115
Test name
Test status
Simulation time 411993073 ps
CPU time 1.06 seconds
Started Jun 02 02:42:46 PM PDT 24
Finished Jun 02 02:42:48 PM PDT 24
Peak memory 201684 kb
Host smart-26169371-8016-4295-80ee-6a06c1879f85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091443953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.1091443953
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.600293707
Short name T843
Test name
Test status
Simulation time 402553723 ps
CPU time 1.58 seconds
Started Jun 02 02:42:49 PM PDT 24
Finished Jun 02 02:42:51 PM PDT 24
Peak memory 201660 kb
Host smart-2aff93de-4f72-4633-a348-365835397ea3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600293707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.600293707
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2685643262
Short name T858
Test name
Test status
Simulation time 5059654667 ps
CPU time 11.05 seconds
Started Jun 02 02:42:48 PM PDT 24
Finished Jun 02 02:43:00 PM PDT 24
Peak memory 201952 kb
Host smart-d0385fe6-f3b2-4a34-9af2-3c0a5005a590
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685643262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.2685643262
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.10738299
Short name T67
Test name
Test status
Simulation time 384580682 ps
CPU time 2.36 seconds
Started Jun 02 02:42:49 PM PDT 24
Finished Jun 02 02:42:52 PM PDT 24
Peak memory 202068 kb
Host smart-83e39ab7-c827-43f6-890e-10a996d8c74c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10738299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.10738299
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.502935962
Short name T919
Test name
Test status
Simulation time 4410167276 ps
CPU time 11.19 seconds
Started Jun 02 02:42:49 PM PDT 24
Finished Jun 02 02:43:01 PM PDT 24
Peak memory 201868 kb
Host smart-58b0a467-cedd-4b02-a14a-0f4446bb6640
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502935962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_int
g_err.502935962
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3154839618
Short name T913
Test name
Test status
Simulation time 514732550 ps
CPU time 1.55 seconds
Started Jun 02 02:42:47 PM PDT 24
Finished Jun 02 02:42:49 PM PDT 24
Peak memory 201744 kb
Host smart-d6e45422-10c1-459d-9277-9e67bd18020d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154839618 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.3154839618
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2828792732
Short name T120
Test name
Test status
Simulation time 519550582 ps
CPU time 1.04 seconds
Started Jun 02 02:42:51 PM PDT 24
Finished Jun 02 02:42:53 PM PDT 24
Peak memory 201912 kb
Host smart-aae9dd2e-3664-430d-a93b-7c0f6e01e9cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828792732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.2828792732
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2654978785
Short name T852
Test name
Test status
Simulation time 492248560 ps
CPU time 1.6 seconds
Started Jun 02 02:42:47 PM PDT 24
Finished Jun 02 02:42:49 PM PDT 24
Peak memory 201676 kb
Host smart-5e28ff9c-bb67-4932-9e66-8f01e34c3ec3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654978785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.2654978785
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2766504541
Short name T898
Test name
Test status
Simulation time 3857857001 ps
CPU time 9.49 seconds
Started Jun 02 02:42:48 PM PDT 24
Finished Jun 02 02:42:58 PM PDT 24
Peak memory 201988 kb
Host smart-92284f79-2a1f-46b7-82a8-7b4d84e60449
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766504541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.2766504541
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.715950026
Short name T839
Test name
Test status
Simulation time 680813646 ps
CPU time 2.54 seconds
Started Jun 02 02:42:50 PM PDT 24
Finished Jun 02 02:42:53 PM PDT 24
Peak memory 202040 kb
Host smart-6437c9a4-2c06-419c-89cc-1776a47b2a7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715950026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.715950026
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.4077817114
Short name T338
Test name
Test status
Simulation time 4971885274 ps
CPU time 7.45 seconds
Started Jun 02 02:42:47 PM PDT 24
Finished Jun 02 02:42:56 PM PDT 24
Peak memory 201756 kb
Host smart-fdd3eb70-077c-4f4b-87c5-83d57e365f04
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077817114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.4077817114
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.2034562014
Short name T840
Test name
Test status
Simulation time 605162727 ps
CPU time 1.3 seconds
Started Jun 02 02:42:47 PM PDT 24
Finished Jun 02 02:42:49 PM PDT 24
Peak memory 201764 kb
Host smart-acfcf984-990d-4f3c-a7fa-650324f56caa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034562014 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.2034562014
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3285298950
Short name T891
Test name
Test status
Simulation time 433855605 ps
CPU time 1.35 seconds
Started Jun 02 02:42:52 PM PDT 24
Finished Jun 02 02:42:54 PM PDT 24
Peak memory 201696 kb
Host smart-b035b014-dc53-4741-b435-051db8c2d1d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285298950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.3285298950
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.674787952
Short name T868
Test name
Test status
Simulation time 412332864 ps
CPU time 1.63 seconds
Started Jun 02 02:42:51 PM PDT 24
Finished Jun 02 02:42:53 PM PDT 24
Peak memory 201684 kb
Host smart-2dfd62fa-0aa7-40dc-8c96-5fcf5b64991b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674787952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.674787952
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1355182005
Short name T887
Test name
Test status
Simulation time 3968192760 ps
CPU time 2.78 seconds
Started Jun 02 02:42:52 PM PDT 24
Finished Jun 02 02:42:55 PM PDT 24
Peak memory 201952 kb
Host smart-dc24fc44-72de-43f0-a735-9382f378f059
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355182005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.1355182005
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3681086208
Short name T884
Test name
Test status
Simulation time 3937446590 ps
CPU time 10.85 seconds
Started Jun 02 02:42:47 PM PDT 24
Finished Jun 02 02:42:59 PM PDT 24
Peak memory 201972 kb
Host smart-bb254074-18a8-4222-910b-23b4295c8dd5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681086208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.3681086208
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2235232677
Short name T855
Test name
Test status
Simulation time 584830686 ps
CPU time 1.27 seconds
Started Jun 02 02:42:48 PM PDT 24
Finished Jun 02 02:42:50 PM PDT 24
Peak memory 201736 kb
Host smart-0a141d62-1bb9-4bed-a927-bc7a9096e229
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235232677 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.2235232677
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1891412140
Short name T861
Test name
Test status
Simulation time 443851379 ps
CPU time 1.88 seconds
Started Jun 02 02:42:48 PM PDT 24
Finished Jun 02 02:42:51 PM PDT 24
Peak memory 201676 kb
Host smart-96d4ad28-a42d-4529-9be1-ff60bd281e94
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891412140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.1891412140
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.1997334225
Short name T918
Test name
Test status
Simulation time 498184281 ps
CPU time 1.84 seconds
Started Jun 02 02:42:47 PM PDT 24
Finished Jun 02 02:42:50 PM PDT 24
Peak memory 201648 kb
Host smart-48fc7fc1-0d9b-4cd0-b71f-92979f2e9639
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997334225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.1997334225
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.3518264900
Short name T121
Test name
Test status
Simulation time 4260668537 ps
CPU time 11.34 seconds
Started Jun 02 02:42:49 PM PDT 24
Finished Jun 02 02:43:01 PM PDT 24
Peak memory 201924 kb
Host smart-8cfc5aa9-e9ef-4c20-b4e2-52ab50b8deb3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518264900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.3518264900
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1058704639
Short name T901
Test name
Test status
Simulation time 502056857 ps
CPU time 1.4 seconds
Started Jun 02 02:42:47 PM PDT 24
Finished Jun 02 02:42:49 PM PDT 24
Peak memory 201924 kb
Host smart-fc79a86f-1e3f-4b32-bfec-eef11433013f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058704639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.1058704639
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1861559331
Short name T50
Test name
Test status
Simulation time 5438321765 ps
CPU time 2.29 seconds
Started Jun 02 02:42:45 PM PDT 24
Finished Jun 02 02:42:48 PM PDT 24
Peak memory 201912 kb
Host smart-8dbd053a-979d-44c9-aee7-11eac1b1c35c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861559331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.1861559331
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.1172557758
Short name T498
Test name
Test status
Simulation time 306714625 ps
CPU time 1.37 seconds
Started Jun 02 02:45:19 PM PDT 24
Finished Jun 02 02:45:22 PM PDT 24
Peak memory 201472 kb
Host smart-1a471e5e-ede8-422e-96de-fdff8a63e35d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172557758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.1172557758
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.2020134759
Short name T746
Test name
Test status
Simulation time 389810408653 ps
CPU time 425.58 seconds
Started Jun 02 02:45:21 PM PDT 24
Finished Jun 02 02:52:27 PM PDT 24
Peak memory 201788 kb
Host smart-837d2104-d310-4caf-9a6c-73c451cc3076
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020134759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.2020134759
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.889548499
Short name T126
Test name
Test status
Simulation time 496259045922 ps
CPU time 129.86 seconds
Started Jun 02 02:45:22 PM PDT 24
Finished Jun 02 02:47:33 PM PDT 24
Peak memory 201760 kb
Host smart-79ea7e7a-c4c2-4726-bf84-87df3648f0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889548499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.889548499
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.1899524557
Short name T698
Test name
Test status
Simulation time 497009238421 ps
CPU time 209.75 seconds
Started Jun 02 02:45:49 PM PDT 24
Finished Jun 02 02:49:20 PM PDT 24
Peak memory 201744 kb
Host smart-b3d40306-4f8f-4c16-8300-c347e7c54a18
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899524557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.1899524557
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.925447595
Short name T674
Test name
Test status
Simulation time 161430669746 ps
CPU time 104.78 seconds
Started Jun 02 02:45:22 PM PDT 24
Finished Jun 02 02:47:07 PM PDT 24
Peak memory 201732 kb
Host smart-1591d064-a500-4757-8ae8-a968b3338357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925447595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.925447595
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.4104043166
Short name T351
Test name
Test status
Simulation time 165718713763 ps
CPU time 242.68 seconds
Started Jun 02 02:45:30 PM PDT 24
Finished Jun 02 02:49:34 PM PDT 24
Peak memory 201868 kb
Host smart-158e70fc-0cd1-4ce7-9c6a-3006737af0ac
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104043166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.4104043166
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.2297621297
Short name T184
Test name
Test status
Simulation time 528716904394 ps
CPU time 312.18 seconds
Started Jun 02 02:45:14 PM PDT 24
Finished Jun 02 02:50:29 PM PDT 24
Peak memory 201804 kb
Host smart-67665f04-09da-482f-9c72-816686540f5a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297621297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.2297621297
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.3590171631
Short name T402
Test name
Test status
Simulation time 195060462208 ps
CPU time 60.89 seconds
Started Jun 02 02:45:12 PM PDT 24
Finished Jun 02 02:46:15 PM PDT 24
Peak memory 201772 kb
Host smart-f9e49105-c77e-43e6-b5ce-338230d3a8a5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590171631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.3590171631
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.3567866460
Short name T427
Test name
Test status
Simulation time 89080786422 ps
CPU time 342.65 seconds
Started Jun 02 02:45:39 PM PDT 24
Finished Jun 02 02:51:22 PM PDT 24
Peak memory 202088 kb
Host smart-c7460128-7dcd-44b0-9296-105c2cd0461b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567866460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.3567866460
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.1049916917
Short name T707
Test name
Test status
Simulation time 35467218094 ps
CPU time 20.02 seconds
Started Jun 02 02:45:16 PM PDT 24
Finished Jun 02 02:45:39 PM PDT 24
Peak memory 201624 kb
Host smart-6655d80f-9aa7-473d-94d2-543448f7707a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049916917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.1049916917
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.2230474302
Short name T413
Test name
Test status
Simulation time 3091025774 ps
CPU time 7.28 seconds
Started Jun 02 02:45:18 PM PDT 24
Finished Jun 02 02:45:31 PM PDT 24
Peak memory 201536 kb
Host smart-36754d6a-b877-4e61-bb52-7235242dcab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230474302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.2230474302
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.2297359374
Short name T55
Test name
Test status
Simulation time 4361930676 ps
CPU time 2.23 seconds
Started Jun 02 02:45:11 PM PDT 24
Finished Jun 02 02:45:15 PM PDT 24
Peak memory 217472 kb
Host smart-eaf0106a-47e4-4426-9df1-8bc37ae0f896
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297359374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.2297359374
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.363272988
Short name T9
Test name
Test status
Simulation time 6132946251 ps
CPU time 4.23 seconds
Started Jun 02 02:45:18 PM PDT 24
Finished Jun 02 02:45:24 PM PDT 24
Peak memory 201548 kb
Host smart-e8db0910-e0aa-4d21-b941-c0f3aa2e2aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363272988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.363272988
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.2912985366
Short name T557
Test name
Test status
Simulation time 7168510160 ps
CPU time 9.28 seconds
Started Jun 02 02:45:17 PM PDT 24
Finished Jun 02 02:45:28 PM PDT 24
Peak memory 201568 kb
Host smart-d97002cb-f00c-4966-bfeb-1dca1d7fa29c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912985366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
2912985366
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.1187524468
Short name T752
Test name
Test status
Simulation time 47189659350 ps
CPU time 29.07 seconds
Started Jun 02 02:45:42 PM PDT 24
Finished Jun 02 02:46:12 PM PDT 24
Peak memory 201884 kb
Host smart-12e0531f-783c-4c9a-84e0-3b0308011b32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187524468 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.1187524468
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.2008634058
Short name T406
Test name
Test status
Simulation time 522954960 ps
CPU time 0.97 seconds
Started Jun 02 02:45:27 PM PDT 24
Finished Jun 02 02:45:29 PM PDT 24
Peak memory 201568 kb
Host smart-1dce7ff4-356d-4f6b-a8d4-a13c8a2f0ef3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008634058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.2008634058
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.2871952436
Short name T596
Test name
Test status
Simulation time 500102475755 ps
CPU time 349.06 seconds
Started Jun 02 02:45:47 PM PDT 24
Finished Jun 02 02:51:37 PM PDT 24
Peak memory 201756 kb
Host smart-69b79806-eb09-4b73-8a9e-a9a4264282aa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871952436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.2871952436
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.843947246
Short name T179
Test name
Test status
Simulation time 493792849813 ps
CPU time 207.46 seconds
Started Jun 02 02:45:44 PM PDT 24
Finished Jun 02 02:49:13 PM PDT 24
Peak memory 201768 kb
Host smart-712353a5-3a15-42ca-b04b-8f240c5df57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843947246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.843947246
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.3659745829
Short name T607
Test name
Test status
Simulation time 491927112983 ps
CPU time 588.98 seconds
Started Jun 02 02:45:20 PM PDT 24
Finished Jun 02 02:55:10 PM PDT 24
Peak memory 201776 kb
Host smart-783f5505-367a-43b6-8e76-d39dfb1425d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659745829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.3659745829
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.2581309552
Short name T496
Test name
Test status
Simulation time 164877773679 ps
CPU time 60.58 seconds
Started Jun 02 02:45:22 PM PDT 24
Finished Jun 02 02:46:32 PM PDT 24
Peak memory 201832 kb
Host smart-124dff98-2318-47fd-8ede-d19e10c04ecf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581309552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.2581309552
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.2312138982
Short name T261
Test name
Test status
Simulation time 375848231028 ps
CPU time 865.82 seconds
Started Jun 02 02:45:31 PM PDT 24
Finished Jun 02 02:59:58 PM PDT 24
Peak memory 201840 kb
Host smart-fd787100-abc9-42c9-98bb-4c615ca47438
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312138982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.2312138982
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.2868288347
Short name T408
Test name
Test status
Simulation time 204062831448 ps
CPU time 130.51 seconds
Started Jun 02 02:45:21 PM PDT 24
Finished Jun 02 02:47:33 PM PDT 24
Peak memory 201724 kb
Host smart-d7d5311c-99c2-4c86-9e52-9f2cb577a871
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868288347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.2868288347
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.3571372435
Short name T699
Test name
Test status
Simulation time 136382477432 ps
CPU time 703.83 seconds
Started Jun 02 02:45:16 PM PDT 24
Finished Jun 02 02:57:02 PM PDT 24
Peak memory 202156 kb
Host smart-29a14b06-5a14-4e88-82f9-bc5cf56900fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571372435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.3571372435
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.1452177299
Short name T372
Test name
Test status
Simulation time 24708863281 ps
CPU time 20.18 seconds
Started Jun 02 02:45:28 PM PDT 24
Finished Jun 02 02:45:49 PM PDT 24
Peak memory 201580 kb
Host smart-dc01665b-8b07-4fbd-8393-ac4da9243a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452177299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.1452177299
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.2675594515
Short name T444
Test name
Test status
Simulation time 4167979520 ps
CPU time 2.72 seconds
Started Jun 02 02:45:38 PM PDT 24
Finished Jun 02 02:45:41 PM PDT 24
Peak memory 201572 kb
Host smart-18b1c76c-eba2-45bf-a628-1532fabe67ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675594515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.2675594515
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.4238301657
Short name T73
Test name
Test status
Simulation time 7743703209 ps
CPU time 6.37 seconds
Started Jun 02 02:45:27 PM PDT 24
Finished Jun 02 02:45:35 PM PDT 24
Peak memory 217452 kb
Host smart-6c7f285d-cdf4-4fca-ba05-ff140d5f0f53
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238301657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.4238301657
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.3697124013
Short name T374
Test name
Test status
Simulation time 6036573921 ps
CPU time 8.13 seconds
Started Jun 02 02:45:45 PM PDT 24
Finished Jun 02 02:45:54 PM PDT 24
Peak memory 201528 kb
Host smart-bea3fb1d-0315-476e-b5b4-3e5f38b0ec0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697124013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.3697124013
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.1245474165
Short name T703
Test name
Test status
Simulation time 525320850547 ps
CPU time 286.39 seconds
Started Jun 02 02:45:16 PM PDT 24
Finished Jun 02 02:50:05 PM PDT 24
Peak memory 201780 kb
Host smart-e3b3b376-28a2-4871-a69e-a60465044ada
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245474165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
1245474165
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.3824885477
Short name T251
Test name
Test status
Simulation time 44482674834 ps
CPU time 54.83 seconds
Started Jun 02 02:45:16 PM PDT 24
Finished Jun 02 02:46:13 PM PDT 24
Peak memory 201952 kb
Host smart-44a120ab-75a0-4b07-96e5-103349cff8da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824885477 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.3824885477
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.1293066863
Short name T275
Test name
Test status
Simulation time 341063119501 ps
CPU time 201.07 seconds
Started Jun 02 02:46:01 PM PDT 24
Finished Jun 02 02:49:23 PM PDT 24
Peak memory 201700 kb
Host smart-b562bec5-9881-43e5-9207-da7fcf07f020
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293066863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.1293066863
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.1295960038
Short name T623
Test name
Test status
Simulation time 323369417928 ps
CPU time 782.89 seconds
Started Jun 02 02:45:54 PM PDT 24
Finished Jun 02 02:58:58 PM PDT 24
Peak memory 201924 kb
Host smart-5b3e9473-fd96-4c37-b254-5b08341adc54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295960038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.1295960038
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.4028303950
Short name T448
Test name
Test status
Simulation time 160365808891 ps
CPU time 390.21 seconds
Started Jun 02 02:45:50 PM PDT 24
Finished Jun 02 02:52:21 PM PDT 24
Peak memory 201740 kb
Host smart-7b6dd788-f32c-4627-a06e-f129ec0d9fda
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028303950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.4028303950
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.2783924718
Short name T758
Test name
Test status
Simulation time 163482921897 ps
CPU time 24.42 seconds
Started Jun 02 02:46:07 PM PDT 24
Finished Jun 02 02:46:34 PM PDT 24
Peak memory 201660 kb
Host smart-8c7638ac-abc7-472a-bbf7-84a4e47135a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783924718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.2783924718
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.978790974
Short name T629
Test name
Test status
Simulation time 322818714749 ps
CPU time 353.98 seconds
Started Jun 02 02:46:02 PM PDT 24
Finished Jun 02 02:51:57 PM PDT 24
Peak memory 201856 kb
Host smart-6ac87880-759f-4843-8b46-f7198b931afe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=978790974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fixe
d.978790974
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.1725392450
Short name T473
Test name
Test status
Simulation time 621980063012 ps
CPU time 191.28 seconds
Started Jun 02 02:46:05 PM PDT 24
Finished Jun 02 02:49:18 PM PDT 24
Peak memory 201776 kb
Host smart-69a51e6f-c51f-47b4-bbb1-4aaba4016ff3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725392450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.1725392450
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.2521399625
Short name T724
Test name
Test status
Simulation time 98832356976 ps
CPU time 575.45 seconds
Started Jun 02 02:46:02 PM PDT 24
Finished Jun 02 02:55:38 PM PDT 24
Peak memory 202072 kb
Host smart-42c64270-23a6-480f-bfd9-4cb7b503dec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521399625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.2521399625
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.621468135
Short name T430
Test name
Test status
Simulation time 44243542236 ps
CPU time 53.48 seconds
Started Jun 02 02:45:55 PM PDT 24
Finished Jun 02 02:46:49 PM PDT 24
Peak memory 201532 kb
Host smart-a3eba0a7-5f81-4774-b241-e0ee0a7aedcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621468135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.621468135
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.3034526399
Short name T353
Test name
Test status
Simulation time 4045603955 ps
CPU time 3.18 seconds
Started Jun 02 02:45:52 PM PDT 24
Finished Jun 02 02:45:56 PM PDT 24
Peak memory 201612 kb
Host smart-01ca1c86-9732-4d4d-b4b2-b163cd34f8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034526399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.3034526399
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.3247738589
Short name T572
Test name
Test status
Simulation time 5865395176 ps
CPU time 15.34 seconds
Started Jun 02 02:45:44 PM PDT 24
Finished Jun 02 02:46:00 PM PDT 24
Peak memory 201584 kb
Host smart-ae6c6c47-93c7-4144-acc8-502dd1c4b7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247738589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.3247738589
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.3429844734
Short name T259
Test name
Test status
Simulation time 166241424977 ps
CPU time 208.21 seconds
Started Jun 02 02:45:49 PM PDT 24
Finished Jun 02 02:49:18 PM PDT 24
Peak memory 201808 kb
Host smart-a0abd8a0-105f-4033-a5ab-8ed6650285c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429844734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.3429844734
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.3607056209
Short name T802
Test name
Test status
Simulation time 70351888574 ps
CPU time 169.62 seconds
Started Jun 02 02:45:51 PM PDT 24
Finished Jun 02 02:48:41 PM PDT 24
Peak memory 210176 kb
Host smart-af9eda9f-bd41-482e-89da-a578acb76d27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607056209 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.3607056209
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.2247321001
Short name T523
Test name
Test status
Simulation time 278002343 ps
CPU time 1.3 seconds
Started Jun 02 02:46:01 PM PDT 24
Finished Jun 02 02:46:03 PM PDT 24
Peak memory 201572 kb
Host smart-19fe8041-7646-4315-a50d-66e1ef730d43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247321001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.2247321001
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.1867489046
Short name T641
Test name
Test status
Simulation time 163506354158 ps
CPU time 379.87 seconds
Started Jun 02 02:45:45 PM PDT 24
Finished Jun 02 02:52:06 PM PDT 24
Peak memory 201796 kb
Host smart-620ae264-356b-471f-bfc4-78a6b38eedb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867489046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.1867489046
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.577608095
Short name T503
Test name
Test status
Simulation time 322454317964 ps
CPU time 639.56 seconds
Started Jun 02 02:45:39 PM PDT 24
Finished Jun 02 02:56:19 PM PDT 24
Peak memory 201752 kb
Host smart-bae81652-22d7-4d15-87d3-12ebe3002885
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=577608095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrup
t_fixed.577608095
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.3516607015
Short name T529
Test name
Test status
Simulation time 496670990943 ps
CPU time 424.23 seconds
Started Jun 02 02:45:54 PM PDT 24
Finished Jun 02 02:52:58 PM PDT 24
Peak memory 201856 kb
Host smart-5eaa7813-8229-43c4-b81f-0bddd4b805ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516607015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.3516607015
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.3980046301
Short name T421
Test name
Test status
Simulation time 326541256131 ps
CPU time 396.26 seconds
Started Jun 02 02:46:03 PM PDT 24
Finished Jun 02 02:52:40 PM PDT 24
Peak memory 201684 kb
Host smart-659c0319-4ba1-4619-8495-a7704b748f1e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980046301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.3980046301
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.1646226043
Short name T237
Test name
Test status
Simulation time 359753860833 ps
CPU time 858.65 seconds
Started Jun 02 02:46:00 PM PDT 24
Finished Jun 02 03:00:19 PM PDT 24
Peak memory 201860 kb
Host smart-510182a0-91e7-4603-9cce-c1a3f3796cee
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646226043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.1646226043
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.3862808897
Short name T546
Test name
Test status
Simulation time 200513364866 ps
CPU time 124.64 seconds
Started Jun 02 02:45:55 PM PDT 24
Finished Jun 02 02:48:00 PM PDT 24
Peak memory 201832 kb
Host smart-e3e97da4-72cc-470b-a991-1bc4457561b8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862808897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.3862808897
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.2907029740
Short name T778
Test name
Test status
Simulation time 68554726652 ps
CPU time 284.99 seconds
Started Jun 02 02:46:07 PM PDT 24
Finished Jun 02 02:50:54 PM PDT 24
Peak memory 202148 kb
Host smart-c0c1da46-32b1-4dd8-a33b-7c8f7ac4d842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907029740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.2907029740
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.265010724
Short name T506
Test name
Test status
Simulation time 26421716020 ps
CPU time 16.33 seconds
Started Jun 02 02:45:58 PM PDT 24
Finished Jun 02 02:46:16 PM PDT 24
Peak memory 201584 kb
Host smart-0b874938-9c25-4c46-b5f3-ab027e8d0bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265010724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.265010724
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.584439983
Short name T627
Test name
Test status
Simulation time 4876885122 ps
CPU time 3.76 seconds
Started Jun 02 02:45:48 PM PDT 24
Finished Jun 02 02:45:53 PM PDT 24
Peak memory 201612 kb
Host smart-115057a3-f157-41fd-a51f-cc78fa745a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584439983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.584439983
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.478924016
Short name T358
Test name
Test status
Simulation time 5633504563 ps
CPU time 13.62 seconds
Started Jun 02 02:45:52 PM PDT 24
Finished Jun 02 02:46:06 PM PDT 24
Peak memory 201604 kb
Host smart-601fa770-6236-4f0d-b095-3a2f270aa5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478924016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.478924016
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.941700435
Short name T311
Test name
Test status
Simulation time 600613431441 ps
CPU time 652.03 seconds
Started Jun 02 02:45:48 PM PDT 24
Finished Jun 02 02:56:41 PM PDT 24
Peak memory 211904 kb
Host smart-796f62bf-0bf9-402d-a2e3-3f3858fc9426
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941700435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all.
941700435
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.1863167786
Short name T31
Test name
Test status
Simulation time 95347478984 ps
CPU time 132.03 seconds
Started Jun 02 02:46:04 PM PDT 24
Finished Jun 02 02:48:16 PM PDT 24
Peak memory 217800 kb
Host smart-8d8db4c2-fca6-4b92-993d-416bfc2445e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863167786 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.1863167786
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.1394803267
Short name T558
Test name
Test status
Simulation time 514279616 ps
CPU time 0.9 seconds
Started Jun 02 02:45:54 PM PDT 24
Finished Jun 02 02:45:56 PM PDT 24
Peak memory 201440 kb
Host smart-adab1b62-02ce-49d8-b581-8aae3c8aacca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394803267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.1394803267
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.83188225
Short name T283
Test name
Test status
Simulation time 347895983428 ps
CPU time 370.24 seconds
Started Jun 02 02:45:52 PM PDT 24
Finished Jun 02 02:52:03 PM PDT 24
Peak memory 201780 kb
Host smart-e3e0ed7f-44bf-4d6e-95be-88844f7b26e4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83188225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gatin
g.83188225
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.3911182715
Short name T320
Test name
Test status
Simulation time 480599387515 ps
CPU time 310.07 seconds
Started Jun 02 02:46:06 PM PDT 24
Finished Jun 02 02:51:18 PM PDT 24
Peak memory 201844 kb
Host smart-7b161486-856d-4c52-b992-e1f4530e8ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911182715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.3911182715
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.3534805750
Short name T145
Test name
Test status
Simulation time 328041778435 ps
CPU time 198.86 seconds
Started Jun 02 02:45:40 PM PDT 24
Finished Jun 02 02:48:59 PM PDT 24
Peak memory 201720 kb
Host smart-b02a223a-6ac8-4b8c-be5a-cf718ed4fbc3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534805750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.3534805750
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.3667281238
Short name T631
Test name
Test status
Simulation time 483906271903 ps
CPU time 1088.08 seconds
Started Jun 02 02:46:22 PM PDT 24
Finished Jun 02 03:04:31 PM PDT 24
Peak memory 201628 kb
Host smart-13694f4c-191b-4ce0-9742-6326a909ec80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667281238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.3667281238
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.2490945675
Short name T445
Test name
Test status
Simulation time 321577189183 ps
CPU time 398.6 seconds
Started Jun 02 02:45:56 PM PDT 24
Finished Jun 02 02:52:35 PM PDT 24
Peak memory 201704 kb
Host smart-b18d13f0-373f-46e4-a2a1-2ff938810ada
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490945675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.2490945675
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.4102056296
Short name T715
Test name
Test status
Simulation time 605243705528 ps
CPU time 276.92 seconds
Started Jun 02 02:45:47 PM PDT 24
Finished Jun 02 02:50:25 PM PDT 24
Peak memory 201632 kb
Host smart-6ca77fca-dfbc-4d1d-a263-b16c118b28e8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102056296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.4102056296
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.4000276770
Short name T767
Test name
Test status
Simulation time 22891116093 ps
CPU time 13.67 seconds
Started Jun 02 02:46:00 PM PDT 24
Finished Jun 02 02:46:15 PM PDT 24
Peak memory 201604 kb
Host smart-ffd9404e-72b2-4d99-99de-03a02cfc3aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000276770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.4000276770
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.1099087427
Short name T159
Test name
Test status
Simulation time 3111342380 ps
CPU time 7.5 seconds
Started Jun 02 02:45:47 PM PDT 24
Finished Jun 02 02:45:56 PM PDT 24
Peak memory 201844 kb
Host smart-0a595c35-8b52-41d3-8f32-53a27f9f3106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099087427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.1099087427
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.1033611031
Short name T462
Test name
Test status
Simulation time 5609660705 ps
CPU time 13.43 seconds
Started Jun 02 02:46:03 PM PDT 24
Finished Jun 02 02:46:17 PM PDT 24
Peak memory 201368 kb
Host smart-03eeaf29-3f75-4583-8f51-aa2347d0c0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033611031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.1033611031
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.919998702
Short name T59
Test name
Test status
Simulation time 162470659843 ps
CPU time 46.78 seconds
Started Jun 02 02:45:56 PM PDT 24
Finished Jun 02 02:46:44 PM PDT 24
Peak memory 201764 kb
Host smart-ad34dd3b-f9ef-495b-b503-e0e1d2d949dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919998702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all.
919998702
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.1800861779
Short name T210
Test name
Test status
Simulation time 78916518833 ps
CPU time 234.47 seconds
Started Jun 02 02:46:01 PM PDT 24
Finished Jun 02 02:49:57 PM PDT 24
Peak memory 211460 kb
Host smart-86073351-0c91-4a74-9c8c-1dcd073b8bc6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800861779 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.1800861779
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.3432043250
Short name T726
Test name
Test status
Simulation time 517427859 ps
CPU time 0.87 seconds
Started Jun 02 02:46:00 PM PDT 24
Finished Jun 02 02:46:02 PM PDT 24
Peak memory 201500 kb
Host smart-3580b19b-3271-4fd5-9904-1fe0386805d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432043250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.3432043250
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.181286135
Short name T664
Test name
Test status
Simulation time 202100406159 ps
CPU time 426.68 seconds
Started Jun 02 02:46:07 PM PDT 24
Finished Jun 02 02:53:16 PM PDT 24
Peak memory 201796 kb
Host smart-0f821858-633e-4f4d-afe3-bad6552e49ee
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181286135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gati
ng.181286135
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.1410592977
Short name T747
Test name
Test status
Simulation time 492402312197 ps
CPU time 762.68 seconds
Started Jun 02 02:45:50 PM PDT 24
Finished Jun 02 02:58:33 PM PDT 24
Peak memory 201784 kb
Host smart-d3ce07c4-1512-4136-b058-d81fff3319c2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410592977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.1410592977
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.434942676
Short name T658
Test name
Test status
Simulation time 168000537910 ps
CPU time 49.69 seconds
Started Jun 02 02:46:01 PM PDT 24
Finished Jun 02 02:46:52 PM PDT 24
Peak memory 201696 kb
Host smart-73da22ca-4177-4bc7-9902-c183c314e892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434942676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.434942676
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.1506690520
Short name T162
Test name
Test status
Simulation time 497187829399 ps
CPU time 290.11 seconds
Started Jun 02 02:45:55 PM PDT 24
Finished Jun 02 02:50:46 PM PDT 24
Peak memory 201740 kb
Host smart-c25397ba-f823-4974-8d9b-36479c97f4bb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506690520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.1506690520
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.2582731545
Short name T474
Test name
Test status
Simulation time 601151677773 ps
CPU time 713.6 seconds
Started Jun 02 02:46:01 PM PDT 24
Finished Jun 02 02:57:56 PM PDT 24
Peak memory 201864 kb
Host smart-6b539b00-f1ce-4e49-8238-bc215935d4ad
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582731545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.2582731545
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.2109259317
Short name T681
Test name
Test status
Simulation time 90130139386 ps
CPU time 372.91 seconds
Started Jun 02 02:45:54 PM PDT 24
Finished Jun 02 02:52:08 PM PDT 24
Peak memory 202116 kb
Host smart-f8a275e2-3e16-4fae-8e36-edd276919b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109259317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.2109259317
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.377070753
Short name T382
Test name
Test status
Simulation time 36092324785 ps
CPU time 54.09 seconds
Started Jun 02 02:46:05 PM PDT 24
Finished Jun 02 02:47:00 PM PDT 24
Peak memory 201536 kb
Host smart-885b7308-852d-4385-a8ec-121baa0f1945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377070753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.377070753
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.1409100138
Short name T609
Test name
Test status
Simulation time 2932891696 ps
CPU time 1.67 seconds
Started Jun 02 02:46:00 PM PDT 24
Finished Jun 02 02:46:02 PM PDT 24
Peak memory 201560 kb
Host smart-9d36a737-6325-436c-bc2d-c667d1054e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409100138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.1409100138
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.1667155449
Short name T189
Test name
Test status
Simulation time 5704892736 ps
CPU time 12.4 seconds
Started Jun 02 02:45:47 PM PDT 24
Finished Jun 02 02:46:00 PM PDT 24
Peak memory 201584 kb
Host smart-f382e738-464d-4edd-af64-55a9084dad48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667155449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.1667155449
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.2489993080
Short name T640
Test name
Test status
Simulation time 328692599 ps
CPU time 0.71 seconds
Started Jun 02 02:45:45 PM PDT 24
Finished Jun 02 02:45:47 PM PDT 24
Peak memory 201420 kb
Host smart-98d15ece-18a2-4e2d-aa90-e729a11632d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489993080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.2489993080
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.3881458679
Short name T309
Test name
Test status
Simulation time 176819488370 ps
CPU time 211.75 seconds
Started Jun 02 02:45:54 PM PDT 24
Finished Jun 02 02:49:26 PM PDT 24
Peak memory 201752 kb
Host smart-0a59ea54-0dc3-40d4-8472-c80b38338427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881458679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.3881458679
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.2738136614
Short name T161
Test name
Test status
Simulation time 160947239867 ps
CPU time 264.24 seconds
Started Jun 02 02:45:47 PM PDT 24
Finished Jun 02 02:50:12 PM PDT 24
Peak memory 201724 kb
Host smart-99c263c2-cfdb-40f0-b2b6-b80ce4abec6a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738136614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.2738136614
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.2833964420
Short name T748
Test name
Test status
Simulation time 165335613220 ps
CPU time 207.74 seconds
Started Jun 02 02:45:55 PM PDT 24
Finished Jun 02 02:49:23 PM PDT 24
Peak memory 201752 kb
Host smart-fa3ca8d8-5810-4d7e-88b9-d60455fa9a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833964420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.2833964420
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.917213864
Short name T401
Test name
Test status
Simulation time 160911646740 ps
CPU time 394.23 seconds
Started Jun 02 02:46:06 PM PDT 24
Finished Jun 02 02:52:42 PM PDT 24
Peak memory 201764 kb
Host smart-8d910255-f119-4ed6-825e-6ae070c02d31
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=917213864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixe
d.917213864
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.3698880144
Short name T785
Test name
Test status
Simulation time 553623158831 ps
CPU time 1313.91 seconds
Started Jun 02 02:45:47 PM PDT 24
Finished Jun 02 03:07:41 PM PDT 24
Peak memory 201784 kb
Host smart-aa175f95-d5f1-48bc-96c0-aeb3a2b103ba
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698880144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.3698880144
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.4004580475
Short name T469
Test name
Test status
Simulation time 208837657407 ps
CPU time 118.74 seconds
Started Jun 02 02:45:55 PM PDT 24
Finished Jun 02 02:47:54 PM PDT 24
Peak memory 201768 kb
Host smart-af849d35-4d4f-4e0c-a08a-3efc7cb20781
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004580475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.4004580475
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.1935095725
Short name T196
Test name
Test status
Simulation time 92671701243 ps
CPU time 507.79 seconds
Started Jun 02 02:45:49 PM PDT 24
Finished Jun 02 02:54:18 PM PDT 24
Peak memory 202060 kb
Host smart-409a3d23-1bd0-4b94-8fb1-4596e4a504b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935095725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.1935095725
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.3077100588
Short name T497
Test name
Test status
Simulation time 23017515326 ps
CPU time 56.6 seconds
Started Jun 02 02:45:51 PM PDT 24
Finished Jun 02 02:46:48 PM PDT 24
Peak memory 201572 kb
Host smart-894c0464-7831-44a4-9444-a52f9c6af4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077100588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.3077100588
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.2102197182
Short name T659
Test name
Test status
Simulation time 4801931954 ps
CPU time 2.09 seconds
Started Jun 02 02:46:01 PM PDT 24
Finished Jun 02 02:46:09 PM PDT 24
Peak memory 201600 kb
Host smart-96f4e660-e737-43fc-badd-5ebf69a81da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102197182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.2102197182
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.2748672034
Short name T407
Test name
Test status
Simulation time 5864936252 ps
CPU time 8.22 seconds
Started Jun 02 02:45:48 PM PDT 24
Finished Jun 02 02:45:57 PM PDT 24
Peak memory 201568 kb
Host smart-4806ec97-329e-49b4-8aed-19355de626c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748672034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.2748672034
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.1880528249
Short name T786
Test name
Test status
Simulation time 329231790800 ps
CPU time 619.83 seconds
Started Jun 02 02:45:58 PM PDT 24
Finished Jun 02 02:56:19 PM PDT 24
Peak memory 201772 kb
Host smart-22cddeb6-38d1-41cb-b69c-936329b9d012
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880528249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.1880528249
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.2062466144
Short name T322
Test name
Test status
Simulation time 71710838801 ps
CPU time 269.13 seconds
Started Jun 02 02:46:05 PM PDT 24
Finished Jun 02 02:50:35 PM PDT 24
Peak memory 210644 kb
Host smart-ffa3a3bd-d305-4fe8-b09b-b3c38bf5653d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062466144 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.2062466144
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.1455902888
Short name T588
Test name
Test status
Simulation time 386995385 ps
CPU time 0.84 seconds
Started Jun 02 02:45:50 PM PDT 24
Finished Jun 02 02:45:52 PM PDT 24
Peak memory 201448 kb
Host smart-e54ba188-9066-439f-b858-79de68b62316
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455902888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.1455902888
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.2193173396
Short name T213
Test name
Test status
Simulation time 157769461045 ps
CPU time 103.14 seconds
Started Jun 02 02:46:02 PM PDT 24
Finished Jun 02 02:47:46 PM PDT 24
Peak memory 201840 kb
Host smart-69d54f6b-6912-481e-84a1-da5ccd30e8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193173396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.2193173396
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.3481676420
Short name T730
Test name
Test status
Simulation time 162446787461 ps
CPU time 301.36 seconds
Started Jun 02 02:45:59 PM PDT 24
Finished Jun 02 02:51:01 PM PDT 24
Peak memory 201708 kb
Host smart-3d32d5ed-4c8c-48a9-9b1e-3fe492aa16ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481676420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.3481676420
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.221899848
Short name T538
Test name
Test status
Simulation time 501529277210 ps
CPU time 1218.71 seconds
Started Jun 02 02:46:08 PM PDT 24
Finished Jun 02 03:06:29 PM PDT 24
Peak memory 201984 kb
Host smart-02bda2c5-8748-459b-bb52-a52023df80f8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=221899848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrup
t_fixed.221899848
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.1185326633
Short name T143
Test name
Test status
Simulation time 489328537781 ps
CPU time 1210.4 seconds
Started Jun 02 02:45:58 PM PDT 24
Finished Jun 02 03:06:09 PM PDT 24
Peak memory 202024 kb
Host smart-56de5c2b-3546-46ce-9ffb-9b5d79ecf035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185326633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.1185326633
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.1268065049
Short name T459
Test name
Test status
Simulation time 163029555302 ps
CPU time 199.84 seconds
Started Jun 02 02:46:04 PM PDT 24
Finished Jun 02 02:49:25 PM PDT 24
Peak memory 201796 kb
Host smart-7b199c51-31ed-47f9-8bd4-3e06d1248312
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268065049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.1268065049
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.2462215445
Short name T187
Test name
Test status
Simulation time 184024018835 ps
CPU time 54.1 seconds
Started Jun 02 02:45:57 PM PDT 24
Finished Jun 02 02:46:52 PM PDT 24
Peak memory 201744 kb
Host smart-a62765fc-3264-490a-85e9-afe2315390e9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462215445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.2462215445
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.1523718898
Short name T569
Test name
Test status
Simulation time 401226651925 ps
CPU time 246.25 seconds
Started Jun 02 02:45:58 PM PDT 24
Finished Jun 02 02:50:05 PM PDT 24
Peak memory 201800 kb
Host smart-c88e8253-9b65-455f-ba1a-ae13b04bf139
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523718898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.1523718898
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.2285647409
Short name T352
Test name
Test status
Simulation time 35374570222 ps
CPU time 22.46 seconds
Started Jun 02 02:46:02 PM PDT 24
Finished Jun 02 02:46:25 PM PDT 24
Peak memory 201540 kb
Host smart-db5426c3-9cde-45ed-be34-c595ba7a725c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285647409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.2285647409
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.2063368661
Short name T160
Test name
Test status
Simulation time 4936202440 ps
CPU time 13.11 seconds
Started Jun 02 02:46:01 PM PDT 24
Finished Jun 02 02:46:15 PM PDT 24
Peak memory 201584 kb
Host smart-bb385ef4-cbf2-42b0-b33b-f36925a00164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063368661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.2063368661
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.3532345399
Short name T4
Test name
Test status
Simulation time 5778531482 ps
CPU time 3.9 seconds
Started Jun 02 02:46:02 PM PDT 24
Finished Jun 02 02:46:06 PM PDT 24
Peak memory 201616 kb
Host smart-dbc33e06-fa28-448d-812a-b44ddb0be27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532345399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.3532345399
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.43991803
Short name T665
Test name
Test status
Simulation time 206667441540 ps
CPU time 504.24 seconds
Started Jun 02 02:46:08 PM PDT 24
Finished Jun 02 02:54:34 PM PDT 24
Peak memory 201804 kb
Host smart-b2a1a49b-2709-48fb-86bb-7c644a1ddacb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43991803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all.43991803
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.790512566
Short name T18
Test name
Test status
Simulation time 528863763759 ps
CPU time 316.49 seconds
Started Jun 02 02:45:46 PM PDT 24
Finished Jun 02 02:51:03 PM PDT 24
Peak memory 210392 kb
Host smart-ad964d19-6969-4a52-9486-02d125a881a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790512566 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.790512566
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.3434332637
Short name T595
Test name
Test status
Simulation time 497653758 ps
CPU time 0.74 seconds
Started Jun 02 02:46:07 PM PDT 24
Finished Jun 02 02:46:10 PM PDT 24
Peak memory 201464 kb
Host smart-34e8a8d9-e166-4a47-8b95-11c50cc2848e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434332637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.3434332637
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.1815554323
Short name T280
Test name
Test status
Simulation time 346393374952 ps
CPU time 795.64 seconds
Started Jun 02 02:46:04 PM PDT 24
Finished Jun 02 02:59:20 PM PDT 24
Peak memory 201780 kb
Host smart-2f324c8e-03c8-4727-a131-60976d7f6b10
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815554323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.1815554323
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.90939468
Short name T453
Test name
Test status
Simulation time 166907600538 ps
CPU time 410.25 seconds
Started Jun 02 02:46:01 PM PDT 24
Finished Jun 02 02:52:52 PM PDT 24
Peak memory 201720 kb
Host smart-99304a36-b2f5-4fcc-ad40-64493886e82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90939468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.90939468
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.1037770785
Short name T164
Test name
Test status
Simulation time 163767452108 ps
CPU time 103.58 seconds
Started Jun 02 02:46:07 PM PDT 24
Finished Jun 02 02:47:53 PM PDT 24
Peak memory 201780 kb
Host smart-09e285b9-b80f-4d05-8ddd-0b43ac666756
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037770785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.1037770785
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.3962059925
Short name T484
Test name
Test status
Simulation time 164417580338 ps
CPU time 388.7 seconds
Started Jun 02 02:46:06 PM PDT 24
Finished Jun 02 02:52:36 PM PDT 24
Peak memory 201776 kb
Host smart-9e6370fc-e68f-428a-8b47-5c1779b5d8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962059925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.3962059925
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.901849459
Short name T505
Test name
Test status
Simulation time 488814065239 ps
CPU time 185.33 seconds
Started Jun 02 02:46:07 PM PDT 24
Finished Jun 02 02:49:15 PM PDT 24
Peak memory 201860 kb
Host smart-07ed0bd9-dbca-448d-bd24-d403dd09f4a3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=901849459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fixe
d.901849459
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.713285267
Short name T167
Test name
Test status
Simulation time 588376927836 ps
CPU time 204.99 seconds
Started Jun 02 02:46:13 PM PDT 24
Finished Jun 02 02:49:38 PM PDT 24
Peak memory 201720 kb
Host smart-e00cf56d-ec15-4e71-b788-a26ee6060a04
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713285267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_
wakeup.713285267
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.90270975
Short name T348
Test name
Test status
Simulation time 595276678699 ps
CPU time 668.16 seconds
Started Jun 02 02:45:59 PM PDT 24
Finished Jun 02 02:57:07 PM PDT 24
Peak memory 201844 kb
Host smart-6ad72b5b-aa6f-4df2-84ff-dd9cb31c129d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90270975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.a
dc_ctrl_filters_wakeup_fixed.90270975
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.369124013
Short name T479
Test name
Test status
Simulation time 129528408327 ps
CPU time 686.58 seconds
Started Jun 02 02:45:58 PM PDT 24
Finished Jun 02 02:57:25 PM PDT 24
Peak memory 202136 kb
Host smart-58fe574b-0731-4d17-9271-1ecf40004e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369124013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.369124013
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.4272191211
Short name T177
Test name
Test status
Simulation time 37576203419 ps
CPU time 19.54 seconds
Started Jun 02 02:45:56 PM PDT 24
Finished Jun 02 02:46:15 PM PDT 24
Peak memory 201616 kb
Host smart-8cc82211-9ccf-4226-82b5-7bb949de4aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272191211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.4272191211
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.2380055749
Short name T710
Test name
Test status
Simulation time 4531855679 ps
CPU time 6.81 seconds
Started Jun 02 02:45:59 PM PDT 24
Finished Jun 02 02:46:07 PM PDT 24
Peak memory 201720 kb
Host smart-8e79d1c5-3a11-4919-b2ef-d0f74647299a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380055749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.2380055749
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.2425511960
Short name T347
Test name
Test status
Simulation time 5870882023 ps
CPU time 4.57 seconds
Started Jun 02 02:45:56 PM PDT 24
Finished Jun 02 02:46:01 PM PDT 24
Peak memory 201624 kb
Host smart-55e7baf9-13fe-4e3d-be62-641a3679095e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425511960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.2425511960
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.118443843
Short name T576
Test name
Test status
Simulation time 654944071421 ps
CPU time 1160.58 seconds
Started Jun 02 02:46:07 PM PDT 24
Finished Jun 02 03:05:29 PM PDT 24
Peak memory 201716 kb
Host smart-683a7374-3610-4fcd-a75f-b010a0ed3a2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118443843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all.
118443843
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.519299351
Short name T303
Test name
Test status
Simulation time 218901120953 ps
CPU time 271.53 seconds
Started Jun 02 02:45:52 PM PDT 24
Finished Jun 02 02:50:24 PM PDT 24
Peak memory 210112 kb
Host smart-2fb18dbb-af90-45c9-98db-8051433bfa28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519299351 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.519299351
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.1644712681
Short name T361
Test name
Test status
Simulation time 533274342 ps
CPU time 1.21 seconds
Started Jun 02 02:45:51 PM PDT 24
Finished Jun 02 02:45:53 PM PDT 24
Peak memory 201508 kb
Host smart-7dfeec51-c40a-4ba9-a7da-ba5fb0e0a5fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644712681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.1644712681
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.494735616
Short name T798
Test name
Test status
Simulation time 321930093675 ps
CPU time 595.96 seconds
Started Jun 02 02:46:03 PM PDT 24
Finished Jun 02 02:55:59 PM PDT 24
Peak memory 201836 kb
Host smart-f611eee4-8f57-46f5-b2a8-cd42de61c65a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494735616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gati
ng.494735616
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.737842240
Short name T249
Test name
Test status
Simulation time 160905384655 ps
CPU time 359.81 seconds
Started Jun 02 02:46:07 PM PDT 24
Finished Jun 02 02:52:09 PM PDT 24
Peak memory 201772 kb
Host smart-5e3aa816-2678-40b9-8468-506a7dabbf6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737842240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.737842240
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.4013865241
Short name T511
Test name
Test status
Simulation time 169132819572 ps
CPU time 214.15 seconds
Started Jun 02 02:46:06 PM PDT 24
Finished Jun 02 02:49:41 PM PDT 24
Peak memory 201744 kb
Host smart-a3d9720c-f540-4d22-ac78-b0ae5e1e7907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013865241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.4013865241
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.2394038037
Short name T713
Test name
Test status
Simulation time 496445640872 ps
CPU time 625.53 seconds
Started Jun 02 02:45:57 PM PDT 24
Finished Jun 02 02:56:23 PM PDT 24
Peak memory 201536 kb
Host smart-a14a103d-edd0-4950-b43b-8e5825a2aee6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394038037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.2394038037
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.1420438560
Short name T183
Test name
Test status
Simulation time 333511754134 ps
CPU time 190.76 seconds
Started Jun 02 02:46:02 PM PDT 24
Finished Jun 02 02:49:20 PM PDT 24
Peak memory 201700 kb
Host smart-a3e7104a-402b-4934-bb70-454ce410064e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420438560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.1420438560
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.1999548803
Short name T613
Test name
Test status
Simulation time 167517369948 ps
CPU time 94.81 seconds
Started Jun 02 02:45:56 PM PDT 24
Finished Jun 02 02:47:32 PM PDT 24
Peak memory 201752 kb
Host smart-bc0a6970-7b22-4261-99d7-17f6bdae16e3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999548803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.1999548803
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.212059897
Short name T323
Test name
Test status
Simulation time 602765782053 ps
CPU time 1258.58 seconds
Started Jun 02 02:46:01 PM PDT 24
Finished Jun 02 03:07:00 PM PDT 24
Peak memory 201804 kb
Host smart-fbf4e250-5729-4c5d-a911-a292bac1b4e8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212059897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_
wakeup.212059897
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.3999549316
Short name T147
Test name
Test status
Simulation time 600464706052 ps
CPU time 345.02 seconds
Started Jun 02 02:45:59 PM PDT 24
Finished Jun 02 02:51:44 PM PDT 24
Peak memory 201996 kb
Host smart-3d29cd89-0b2c-477b-b75e-a8b41b760a37
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999549316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.3999549316
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.925330257
Short name T207
Test name
Test status
Simulation time 71901734831 ps
CPU time 275.04 seconds
Started Jun 02 02:46:12 PM PDT 24
Finished Jun 02 02:50:48 PM PDT 24
Peak memory 202064 kb
Host smart-a481af82-cdbe-4996-8740-f2a5aa818344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925330257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.925330257
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.726654495
Short name T449
Test name
Test status
Simulation time 39452707762 ps
CPU time 27.22 seconds
Started Jun 02 02:46:08 PM PDT 24
Finished Jun 02 02:46:37 PM PDT 24
Peak memory 201528 kb
Host smart-a34933c7-c032-46bd-9a3e-13f410610c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726654495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.726654495
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.415063569
Short name T634
Test name
Test status
Simulation time 4854726169 ps
CPU time 3.48 seconds
Started Jun 02 02:46:02 PM PDT 24
Finished Jun 02 02:46:06 PM PDT 24
Peak memory 201608 kb
Host smart-09eae677-f7d7-4878-9d18-eeb39433e11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415063569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.415063569
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.1034928826
Short name T97
Test name
Test status
Simulation time 5794832739 ps
CPU time 4.46 seconds
Started Jun 02 02:45:58 PM PDT 24
Finished Jun 02 02:46:03 PM PDT 24
Peak memory 201620 kb
Host smart-ce2b05c6-065c-4a5e-b9a9-c1ab1a4b6858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034928826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.1034928826
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.374660538
Short name T229
Test name
Test status
Simulation time 173638991244 ps
CPU time 100.43 seconds
Started Jun 02 02:46:06 PM PDT 24
Finished Jun 02 02:47:49 PM PDT 24
Peak memory 201788 kb
Host smart-838c2b16-ce34-48ad-9284-4b1eef50c8f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374660538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all.
374660538
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.253066332
Short name T329
Test name
Test status
Simulation time 592097810015 ps
CPU time 384.57 seconds
Started Jun 02 02:46:10 PM PDT 24
Finished Jun 02 02:52:36 PM PDT 24
Peak memory 210412 kb
Host smart-5fe468f0-f21d-4076-a215-e76c6b182e37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253066332 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.253066332
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.3747632895
Short name T716
Test name
Test status
Simulation time 358776899 ps
CPU time 1.02 seconds
Started Jun 02 02:45:58 PM PDT 24
Finished Jun 02 02:46:00 PM PDT 24
Peak memory 201472 kb
Host smart-6882cb4d-5088-40c9-8cc7-62b018d7c264
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747632895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.3747632895
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.2285254078
Short name T512
Test name
Test status
Simulation time 177376163932 ps
CPU time 24.4 seconds
Started Jun 02 02:46:06 PM PDT 24
Finished Jun 02 02:46:32 PM PDT 24
Peak memory 201684 kb
Host smart-616aaf63-aadf-41c8-875a-f82821d95d69
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285254078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.2285254078
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.1272835887
Short name T515
Test name
Test status
Simulation time 164738010471 ps
CPU time 185.42 seconds
Started Jun 02 02:45:54 PM PDT 24
Finished Jun 02 02:48:59 PM PDT 24
Peak memory 201844 kb
Host smart-42ae3293-d269-45b4-a324-88da090986f4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272835887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.1272835887
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.3069438264
Short name T424
Test name
Test status
Simulation time 165259267850 ps
CPU time 31.61 seconds
Started Jun 02 02:45:56 PM PDT 24
Finished Jun 02 02:46:28 PM PDT 24
Peak memory 201776 kb
Host smart-d1a71994-c065-4134-a72c-c5c7330ad584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069438264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.3069438264
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.1445371993
Short name T764
Test name
Test status
Simulation time 501354357313 ps
CPU time 311.82 seconds
Started Jun 02 02:45:57 PM PDT 24
Finished Jun 02 02:51:10 PM PDT 24
Peak memory 201760 kb
Host smart-1850b874-98ce-4224-9004-d138e2d644f0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445371993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.1445371993
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.2701481284
Short name T757
Test name
Test status
Simulation time 606512490977 ps
CPU time 386.57 seconds
Started Jun 02 02:46:06 PM PDT 24
Finished Jun 02 02:52:34 PM PDT 24
Peak memory 201788 kb
Host smart-1e89b2a7-f1f2-4a7d-860f-63f376823d40
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701481284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.2701481284
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.3185673014
Short name T195
Test name
Test status
Simulation time 98651141934 ps
CPU time 384.51 seconds
Started Jun 02 02:46:05 PM PDT 24
Finished Jun 02 02:52:31 PM PDT 24
Peak memory 202064 kb
Host smart-e9316256-9f72-42a8-b971-8947e4e43e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185673014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.3185673014
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.1554514135
Short name T432
Test name
Test status
Simulation time 23860551501 ps
CPU time 53.15 seconds
Started Jun 02 02:46:04 PM PDT 24
Finished Jun 02 02:46:58 PM PDT 24
Peak memory 201496 kb
Host smart-5258d0bb-16a3-448f-933e-a8378d98338f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554514135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.1554514135
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.3687275113
Short name T501
Test name
Test status
Simulation time 3523876914 ps
CPU time 5 seconds
Started Jun 02 02:45:57 PM PDT 24
Finished Jun 02 02:46:02 PM PDT 24
Peak memory 201528 kb
Host smart-43198e82-9132-46db-af37-21cc248fb2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687275113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.3687275113
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.193760055
Short name T593
Test name
Test status
Simulation time 6074409137 ps
CPU time 4.95 seconds
Started Jun 02 02:46:08 PM PDT 24
Finished Jun 02 02:46:15 PM PDT 24
Peak memory 201608 kb
Host smart-63ba28c9-2d1f-4434-8d1c-41b1c7c92ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193760055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.193760055
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.864759818
Short name T328
Test name
Test status
Simulation time 71232927955 ps
CPU time 105.4 seconds
Started Jun 02 02:46:20 PM PDT 24
Finished Jun 02 02:48:07 PM PDT 24
Peak memory 210296 kb
Host smart-f59217c0-78c6-4e4a-a03f-d3f5079e594d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864759818 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.864759818
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.3382025762
Short name T411
Test name
Test status
Simulation time 333837777 ps
CPU time 0.98 seconds
Started Jun 02 02:46:08 PM PDT 24
Finished Jun 02 02:46:11 PM PDT 24
Peak memory 201476 kb
Host smart-eeda1259-fc79-44db-86d6-e5069bdec765
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382025762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.3382025762
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.48347594
Short name T779
Test name
Test status
Simulation time 184507959397 ps
CPU time 188.17 seconds
Started Jun 02 02:46:10 PM PDT 24
Finished Jun 02 02:49:20 PM PDT 24
Peak memory 201744 kb
Host smart-0476f0bc-4188-49c9-b2b2-c3e2e9bbda95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48347594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.48347594
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.287131426
Short name T399
Test name
Test status
Simulation time 164219909988 ps
CPU time 112.92 seconds
Started Jun 02 02:46:00 PM PDT 24
Finished Jun 02 02:47:53 PM PDT 24
Peak memory 201880 kb
Host smart-7bb53b91-b0c3-49cd-932a-6bb4a38dee86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287131426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.287131426
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.1715616831
Short name T586
Test name
Test status
Simulation time 325504652311 ps
CPU time 59.37 seconds
Started Jun 02 02:46:08 PM PDT 24
Finished Jun 02 02:47:10 PM PDT 24
Peak memory 201704 kb
Host smart-f7467442-4218-4c83-a6fa-78da08902332
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715616831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.1715616831
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.3854171045
Short name T176
Test name
Test status
Simulation time 488997471411 ps
CPU time 1081.26 seconds
Started Jun 02 02:46:07 PM PDT 24
Finished Jun 02 03:04:10 PM PDT 24
Peak memory 201776 kb
Host smart-ecebdd3f-84c8-41ee-b38d-b822a522b402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854171045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.3854171045
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.792152273
Short name T773
Test name
Test status
Simulation time 327396437710 ps
CPU time 194.37 seconds
Started Jun 02 02:46:08 PM PDT 24
Finished Jun 02 02:49:24 PM PDT 24
Peak memory 201824 kb
Host smart-6e30fcd5-5f16-4069-8d6f-135941c17fe9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=792152273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fixe
d.792152273
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.1865115811
Short name T624
Test name
Test status
Simulation time 169608802066 ps
CPU time 99.57 seconds
Started Jun 02 02:46:04 PM PDT 24
Finished Jun 02 02:47:44 PM PDT 24
Peak memory 201796 kb
Host smart-06ffa014-f946-41bf-adc9-0e21caf50d49
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865115811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.1865115811
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.1978670673
Short name T499
Test name
Test status
Simulation time 609332558093 ps
CPU time 383.26 seconds
Started Jun 02 02:46:08 PM PDT 24
Finished Jun 02 02:52:34 PM PDT 24
Peak memory 201704 kb
Host smart-3405effe-d69a-4e00-b400-c8773db190b2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978670673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.1978670673
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.2638119724
Short name T420
Test name
Test status
Simulation time 92816069451 ps
CPU time 504.47 seconds
Started Jun 02 02:46:05 PM PDT 24
Finished Jun 02 02:54:31 PM PDT 24
Peak memory 202040 kb
Host smart-3192912f-3606-40b6-98e0-0c069d142bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638119724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.2638119724
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.1666613325
Short name T494
Test name
Test status
Simulation time 23296490295 ps
CPU time 14.84 seconds
Started Jun 02 02:46:10 PM PDT 24
Finished Jun 02 02:46:27 PM PDT 24
Peak memory 201576 kb
Host smart-aac46079-0a89-4e32-af41-2f2ba2e87100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666613325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.1666613325
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.621003730
Short name T82
Test name
Test status
Simulation time 3296371272 ps
CPU time 8.29 seconds
Started Jun 02 02:46:05 PM PDT 24
Finished Jun 02 02:46:14 PM PDT 24
Peak memory 201504 kb
Host smart-c8c31aca-043d-4138-8763-56d4724f9b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621003730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.621003730
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.2458758326
Short name T504
Test name
Test status
Simulation time 5589345689 ps
CPU time 7.49 seconds
Started Jun 02 02:46:07 PM PDT 24
Finished Jun 02 02:46:16 PM PDT 24
Peak memory 201592 kb
Host smart-3aa0528a-3501-48b1-8bd1-a139d76896ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458758326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.2458758326
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.1178893286
Short name T791
Test name
Test status
Simulation time 81654547334 ps
CPU time 291.68 seconds
Started Jun 02 02:46:13 PM PDT 24
Finished Jun 02 02:51:05 PM PDT 24
Peak memory 218440 kb
Host smart-cc56b374-ed97-40e0-ad8a-ccd7a899d7eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178893286 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.1178893286
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.2023457164
Short name T721
Test name
Test status
Simulation time 419697680 ps
CPU time 0.8 seconds
Started Jun 02 02:45:41 PM PDT 24
Finished Jun 02 02:45:43 PM PDT 24
Peak memory 201476 kb
Host smart-5f9e15cb-4873-4b76-b6a1-51ab986d2ea9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023457164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.2023457164
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.2584293215
Short name T577
Test name
Test status
Simulation time 329327076696 ps
CPU time 370.78 seconds
Started Jun 02 02:45:16 PM PDT 24
Finished Jun 02 02:51:29 PM PDT 24
Peak memory 201792 kb
Host smart-1789c08c-55bd-4a01-ac1a-aa7d83cd9126
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584293215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.2584293215
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.1692070998
Short name T765
Test name
Test status
Simulation time 160372988155 ps
CPU time 201.37 seconds
Started Jun 02 02:45:16 PM PDT 24
Finished Jun 02 02:48:40 PM PDT 24
Peak memory 201776 kb
Host smart-f783f926-26b6-48ab-9cf3-09696d16ef78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692070998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.1692070998
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.790386247
Short name T369
Test name
Test status
Simulation time 329175004495 ps
CPU time 359.87 seconds
Started Jun 02 02:45:14 PM PDT 24
Finished Jun 02 02:51:16 PM PDT 24
Peak memory 201756 kb
Host smart-348f0614-f48b-4d6b-9878-6653443d3d94
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=790386247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt
_fixed.790386247
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.3330971714
Short name T150
Test name
Test status
Simulation time 331459807922 ps
CPU time 213.47 seconds
Started Jun 02 02:45:27 PM PDT 24
Finished Jun 02 02:49:01 PM PDT 24
Peak memory 201928 kb
Host smart-69be735e-a5bc-4185-8728-5da69592df39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330971714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.3330971714
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.1603796978
Short name T535
Test name
Test status
Simulation time 165545314356 ps
CPU time 63.09 seconds
Started Jun 02 02:45:17 PM PDT 24
Finished Jun 02 02:46:22 PM PDT 24
Peak memory 201764 kb
Host smart-8cc8ca78-9777-4c96-8f4b-f6f2dcc894f6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603796978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.1603796978
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.785686551
Short name T133
Test name
Test status
Simulation time 239503150067 ps
CPU time 143.79 seconds
Started Jun 02 02:45:15 PM PDT 24
Finished Jun 02 02:47:45 PM PDT 24
Peak memory 201780 kb
Host smart-9d53bd2e-2741-456e-966b-500066b84fd2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785686551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_w
akeup.785686551
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.781919962
Short name T346
Test name
Test status
Simulation time 203600948409 ps
CPU time 476.42 seconds
Started Jun 02 02:45:28 PM PDT 24
Finished Jun 02 02:53:26 PM PDT 24
Peak memory 201676 kb
Host smart-e35d782a-4f03-4dc3-b17b-7eba6e313c9f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781919962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.a
dc_ctrl_filters_wakeup_fixed.781919962
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.901711500
Short name T362
Test name
Test status
Simulation time 25935287901 ps
CPU time 30.64 seconds
Started Jun 02 02:45:26 PM PDT 24
Finished Jun 02 02:45:58 PM PDT 24
Peak memory 201532 kb
Host smart-6b1e1284-42b8-4a19-886e-2d0453244cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901711500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.901711500
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.3464739472
Short name T379
Test name
Test status
Simulation time 5108374448 ps
CPU time 3.29 seconds
Started Jun 02 02:45:14 PM PDT 24
Finished Jun 02 02:45:20 PM PDT 24
Peak memory 201572 kb
Host smart-43195466-06f8-4b39-a6b7-6e4b23bf9ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464739472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.3464739472
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.906096261
Short name T591
Test name
Test status
Simulation time 5982868021 ps
CPU time 15.21 seconds
Started Jun 02 02:45:42 PM PDT 24
Finished Jun 02 02:45:57 PM PDT 24
Peak memory 201584 kb
Host smart-71204d22-d298-4de0-af32-e74dbdf69574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906096261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.906096261
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.3990697125
Short name T288
Test name
Test status
Simulation time 168162272390 ps
CPU time 91.67 seconds
Started Jun 02 02:45:43 PM PDT 24
Finished Jun 02 02:47:15 PM PDT 24
Peak memory 201780 kb
Host smart-fcf1ad18-364b-4fd0-ae3f-13debdca1c34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990697125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
3990697125
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.603792783
Short name T219
Test name
Test status
Simulation time 46332538614 ps
CPU time 80.31 seconds
Started Jun 02 02:45:15 PM PDT 24
Finished Jun 02 02:46:38 PM PDT 24
Peak memory 210436 kb
Host smart-2fd5adcd-2d58-419e-8a23-7ca5da3047d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603792783 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.603792783
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.152613445
Short name T735
Test name
Test status
Simulation time 484938955 ps
CPU time 0.85 seconds
Started Jun 02 02:46:06 PM PDT 24
Finished Jun 02 02:46:09 PM PDT 24
Peak memory 201472 kb
Host smart-38848ccb-9609-49dd-bcb1-4185e12acff0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152613445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.152613445
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.3724115004
Short name T702
Test name
Test status
Simulation time 368709562934 ps
CPU time 732.63 seconds
Started Jun 02 02:46:07 PM PDT 24
Finished Jun 02 02:58:21 PM PDT 24
Peak memory 201768 kb
Host smart-2176b61e-deb3-4d29-b793-74d323256f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724115004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.3724115004
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.2037423996
Short name T796
Test name
Test status
Simulation time 320795699138 ps
CPU time 267.41 seconds
Started Jun 02 02:46:06 PM PDT 24
Finished Jun 02 02:50:35 PM PDT 24
Peak memory 201848 kb
Host smart-f0f825f2-f7ea-4752-8f02-8757bcd56789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037423996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.2037423996
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.2217935778
Short name T450
Test name
Test status
Simulation time 492019717207 ps
CPU time 1088.09 seconds
Started Jun 02 02:46:27 PM PDT 24
Finished Jun 02 03:04:35 PM PDT 24
Peak memory 201700 kb
Host smart-177e34ca-1b01-48d1-bcb0-a0d83d2715e5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217935778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.2217935778
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.556506810
Short name T616
Test name
Test status
Simulation time 324867123565 ps
CPU time 728.21 seconds
Started Jun 02 02:46:07 PM PDT 24
Finished Jun 02 02:58:18 PM PDT 24
Peak memory 201712 kb
Host smart-d2733201-49c9-48ab-b9d2-70b8a4ed483d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556506810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.556506810
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.424672714
Short name T632
Test name
Test status
Simulation time 160093921864 ps
CPU time 241.14 seconds
Started Jun 02 02:46:05 PM PDT 24
Finished Jun 02 02:50:07 PM PDT 24
Peak memory 201772 kb
Host smart-c2a78dff-0b73-4df3-9a61-68c5f71792ed
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=424672714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fixe
d.424672714
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.3571445089
Short name T37
Test name
Test status
Simulation time 524199325082 ps
CPU time 333.34 seconds
Started Jun 02 02:46:06 PM PDT 24
Finished Jun 02 02:51:41 PM PDT 24
Peak memory 201992 kb
Host smart-744fe517-5c60-4221-97bf-7f4951272028
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571445089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.3571445089
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.1367264628
Short name T180
Test name
Test status
Simulation time 188021100566 ps
CPU time 103.23 seconds
Started Jun 02 02:46:03 PM PDT 24
Finished Jun 02 02:47:47 PM PDT 24
Peak memory 201736 kb
Host smart-e54d9174-0911-4560-9e4f-2b24c94a1702
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367264628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.1367264628
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.4214533396
Short name T40
Test name
Test status
Simulation time 75137920859 ps
CPU time 236 seconds
Started Jun 02 02:46:06 PM PDT 24
Finished Jun 02 02:50:04 PM PDT 24
Peak memory 202068 kb
Host smart-ad11a03e-7c17-4ab2-a7c4-72e591dd0ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214533396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.4214533396
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.830180158
Short name T783
Test name
Test status
Simulation time 29386262227 ps
CPU time 15.8 seconds
Started Jun 02 02:46:05 PM PDT 24
Finished Jun 02 02:46:22 PM PDT 24
Peak memory 201560 kb
Host smart-17db22f1-2d2a-47f7-adf2-1ac32b5def3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830180158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.830180158
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.3051750757
Short name T396
Test name
Test status
Simulation time 3003749144 ps
CPU time 4.62 seconds
Started Jun 02 02:46:06 PM PDT 24
Finished Jun 02 02:46:12 PM PDT 24
Peak memory 201612 kb
Host smart-ad4ba2ce-c76e-4b6f-830e-c15e32e2cbf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051750757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.3051750757
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.578467554
Short name T564
Test name
Test status
Simulation time 5937260177 ps
CPU time 14.11 seconds
Started Jun 02 02:46:07 PM PDT 24
Finished Jun 02 02:46:23 PM PDT 24
Peak memory 201592 kb
Host smart-c97467c4-27d4-4418-b6c6-6433b71a9b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578467554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.578467554
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.4016057655
Short name T729
Test name
Test status
Simulation time 165627479884 ps
CPU time 367.41 seconds
Started Jun 02 02:46:07 PM PDT 24
Finished Jun 02 02:52:16 PM PDT 24
Peak memory 201680 kb
Host smart-25a4260f-1979-463f-9b1b-dbdc538f18be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016057655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.4016057655
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.2713519652
Short name T705
Test name
Test status
Simulation time 155099880643 ps
CPU time 180.4 seconds
Started Jun 02 02:46:03 PM PDT 24
Finished Jun 02 02:49:04 PM PDT 24
Peak memory 210604 kb
Host smart-10bf4580-414c-4dee-8364-3be0ca9fee6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713519652 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.2713519652
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.3195404345
Short name T368
Test name
Test status
Simulation time 355738866 ps
CPU time 0.81 seconds
Started Jun 02 02:46:05 PM PDT 24
Finished Jun 02 02:46:08 PM PDT 24
Peak memory 201376 kb
Host smart-34e8faf1-1102-4577-85e0-95fd7f68c1fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195404345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.3195404345
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.3418738895
Short name T273
Test name
Test status
Simulation time 156950147320 ps
CPU time 103.75 seconds
Started Jun 02 02:46:05 PM PDT 24
Finished Jun 02 02:47:50 PM PDT 24
Peak memory 201748 kb
Host smart-6c1aec51-5025-4254-9517-79f9a1051108
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418738895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.3418738895
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.4097692446
Short name T220
Test name
Test status
Simulation time 345697333591 ps
CPU time 202.35 seconds
Started Jun 02 02:46:15 PM PDT 24
Finished Jun 02 02:49:38 PM PDT 24
Peak memory 201728 kb
Host smart-792344e2-659d-42bd-994c-3b57e88897fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097692446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.4097692446
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.2315650230
Short name T403
Test name
Test status
Simulation time 328670157466 ps
CPU time 388.24 seconds
Started Jun 02 02:46:08 PM PDT 24
Finished Jun 02 02:52:39 PM PDT 24
Peak memory 201728 kb
Host smart-0bd4e9d6-4526-462a-9364-bc1613a8dc4c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315650230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.2315650230
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.3413146819
Short name T489
Test name
Test status
Simulation time 322641827992 ps
CPU time 764.79 seconds
Started Jun 02 02:46:06 PM PDT 24
Finished Jun 02 02:58:53 PM PDT 24
Peak memory 201828 kb
Host smart-b24fb281-76da-4305-b9df-842c105adc1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413146819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.3413146819
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.4210438139
Short name T662
Test name
Test status
Simulation time 490545647627 ps
CPU time 562.19 seconds
Started Jun 02 02:46:13 PM PDT 24
Finished Jun 02 02:55:36 PM PDT 24
Peak memory 201656 kb
Host smart-b4929744-4812-4686-92f2-00cc380984e5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210438139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.4210438139
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.977567115
Short name T718
Test name
Test status
Simulation time 269553005041 ps
CPU time 157.23 seconds
Started Jun 02 02:46:09 PM PDT 24
Finished Jun 02 02:48:49 PM PDT 24
Peak memory 201752 kb
Host smart-867311eb-c06b-4960-a9ab-71fabaccddb8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977567115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_
wakeup.977567115
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.661984490
Short name T670
Test name
Test status
Simulation time 599251263165 ps
CPU time 385.11 seconds
Started Jun 02 02:46:15 PM PDT 24
Finished Jun 02 02:52:41 PM PDT 24
Peak memory 201672 kb
Host smart-9c8f0b3c-a92e-4196-9624-087164e87a1e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661984490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
adc_ctrl_filters_wakeup_fixed.661984490
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.3793927881
Short name T425
Test name
Test status
Simulation time 98257838916 ps
CPU time 408.09 seconds
Started Jun 02 02:46:19 PM PDT 24
Finished Jun 02 02:53:08 PM PDT 24
Peak memory 202092 kb
Host smart-9a00efd5-38a3-458e-9bf3-91bef890b401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793927881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.3793927881
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.3596546034
Short name T24
Test name
Test status
Simulation time 24188356529 ps
CPU time 60.49 seconds
Started Jun 02 02:46:14 PM PDT 24
Finished Jun 02 02:47:15 PM PDT 24
Peak memory 201588 kb
Host smart-dff76e70-8c54-4fff-8c59-eea980d88cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596546034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.3596546034
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.152895568
Short name T708
Test name
Test status
Simulation time 5300247872 ps
CPU time 13.14 seconds
Started Jun 02 02:46:29 PM PDT 24
Finished Jun 02 02:46:42 PM PDT 24
Peak memory 201540 kb
Host smart-094e7ee9-076b-4a7a-bcdc-ee62287db34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152895568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.152895568
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.248348977
Short name T376
Test name
Test status
Simulation time 6007226134 ps
CPU time 15.86 seconds
Started Jun 02 02:46:00 PM PDT 24
Finished Jun 02 02:46:17 PM PDT 24
Peak memory 201496 kb
Host smart-2f2b7487-e75a-4394-9194-450053f0ca5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248348977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.248348977
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.2056908614
Short name T566
Test name
Test status
Simulation time 499178147220 ps
CPU time 183.27 seconds
Started Jun 02 02:46:08 PM PDT 24
Finished Jun 02 02:49:13 PM PDT 24
Peak memory 201708 kb
Host smart-550e886f-1862-41e3-bb02-29f5b0322232
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056908614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.2056908614
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.3802490747
Short name T438
Test name
Test status
Simulation time 175987724763 ps
CPU time 107.65 seconds
Started Jun 02 02:46:03 PM PDT 24
Finished Jun 02 02:47:52 PM PDT 24
Peak memory 210432 kb
Host smart-6bd7fb4a-3473-419a-a34f-75d0076a5f75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802490747 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.3802490747
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.1444305575
Short name T549
Test name
Test status
Simulation time 508065726 ps
CPU time 0.94 seconds
Started Jun 02 02:46:10 PM PDT 24
Finished Jun 02 02:46:13 PM PDT 24
Peak memory 201468 kb
Host smart-06b3aeff-8635-4090-a2c6-f93ee5709463
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444305575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.1444305575
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.2123835866
Short name T326
Test name
Test status
Simulation time 173405114778 ps
CPU time 193.32 seconds
Started Jun 02 02:46:07 PM PDT 24
Finished Jun 02 02:49:22 PM PDT 24
Peak memory 201776 kb
Host smart-3e36badc-52f0-4a9d-8543-5176772b2bf7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123835866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.2123835866
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.2001578792
Short name T267
Test name
Test status
Simulation time 510070384469 ps
CPU time 1209.22 seconds
Started Jun 02 02:46:04 PM PDT 24
Finished Jun 02 03:06:15 PM PDT 24
Peak memory 201760 kb
Host smart-e8737c53-5188-4208-9218-c76bba543548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001578792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.2001578792
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.417025335
Short name T621
Test name
Test status
Simulation time 162531788057 ps
CPU time 98 seconds
Started Jun 02 02:46:19 PM PDT 24
Finished Jun 02 02:47:58 PM PDT 24
Peak memory 201788 kb
Host smart-65be41f4-b19d-42fd-8c87-b4368725352e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=417025335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrup
t_fixed.417025335
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.207245362
Short name T155
Test name
Test status
Simulation time 327591720031 ps
CPU time 784.98 seconds
Started Jun 02 02:46:09 PM PDT 24
Finished Jun 02 02:59:16 PM PDT 24
Peak memory 201760 kb
Host smart-c0afd08f-a238-46cd-b583-f466b4b2d305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207245362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.207245362
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.2349078469
Short name T742
Test name
Test status
Simulation time 494354939523 ps
CPU time 192.3 seconds
Started Jun 02 02:46:08 PM PDT 24
Finished Jun 02 02:49:23 PM PDT 24
Peak memory 201732 kb
Host smart-baa9da97-2207-48b7-b5a1-b103305129d8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349078469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.2349078469
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.2565306724
Short name T318
Test name
Test status
Simulation time 375716919202 ps
CPU time 185.21 seconds
Started Jun 02 02:46:14 PM PDT 24
Finished Jun 02 02:49:19 PM PDT 24
Peak memory 201864 kb
Host smart-c111002d-7afc-4c30-b496-7b4b292ff6ce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565306724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.2565306724
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.3166888744
Short name T375
Test name
Test status
Simulation time 618007329647 ps
CPU time 801.72 seconds
Started Jun 02 02:46:19 PM PDT 24
Finished Jun 02 02:59:42 PM PDT 24
Peak memory 201768 kb
Host smart-ff038c24-468d-42d6-8d70-fa4977dcfd28
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166888744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.3166888744
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.2721033886
Short name T711
Test name
Test status
Simulation time 121922927455 ps
CPU time 649.97 seconds
Started Jun 02 02:46:30 PM PDT 24
Finished Jun 02 02:57:21 PM PDT 24
Peak memory 202136 kb
Host smart-29f4e207-d620-44da-9e34-c1897f9910c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721033886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.2721033886
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.90019471
Short name T763
Test name
Test status
Simulation time 42032878380 ps
CPU time 89.72 seconds
Started Jun 02 02:46:12 PM PDT 24
Finished Jun 02 02:47:43 PM PDT 24
Peak memory 201548 kb
Host smart-2c2969ef-ee6f-4296-88b8-7e3c03d83651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90019471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.90019471
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.1690187930
Short name T429
Test name
Test status
Simulation time 5271038752 ps
CPU time 11.47 seconds
Started Jun 02 02:46:07 PM PDT 24
Finished Jun 02 02:46:20 PM PDT 24
Peak memory 201600 kb
Host smart-20706e22-b2a9-4328-bc57-8f0eb7db6242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690187930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.1690187930
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.306416281
Short name T780
Test name
Test status
Simulation time 5984067986 ps
CPU time 14.46 seconds
Started Jun 02 02:46:09 PM PDT 24
Finished Jun 02 02:46:26 PM PDT 24
Peak memory 201584 kb
Host smart-f03fb5e6-d960-4064-ae9a-cda06e84dfdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306416281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.306416281
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.2695851808
Short name T743
Test name
Test status
Simulation time 337618257243 ps
CPU time 192.35 seconds
Started Jun 02 02:46:13 PM PDT 24
Finished Jun 02 02:49:26 PM PDT 24
Peak memory 201836 kb
Host smart-e965f045-f940-40e2-ada5-588d379aad10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695851808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.2695851808
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.1031636827
Short name T15
Test name
Test status
Simulation time 120846034218 ps
CPU time 148.9 seconds
Started Jun 02 02:46:09 PM PDT 24
Finished Jun 02 02:48:40 PM PDT 24
Peak memory 218388 kb
Host smart-81f0da53-d12a-4210-9929-615d01565426
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031636827 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.1031636827
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.2098760301
Short name T689
Test name
Test status
Simulation time 444919534 ps
CPU time 0.94 seconds
Started Jun 02 02:46:05 PM PDT 24
Finished Jun 02 02:46:08 PM PDT 24
Peak memory 201468 kb
Host smart-43c6f229-56da-4892-bf9b-9cfbc3cfe44f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098760301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.2098760301
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.305167584
Short name T254
Test name
Test status
Simulation time 162415987568 ps
CPU time 47.41 seconds
Started Jun 02 02:46:14 PM PDT 24
Finished Jun 02 02:47:02 PM PDT 24
Peak memory 201848 kb
Host smart-54b914c1-4cc6-48ac-99ce-ae86785243c2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305167584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gati
ng.305167584
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.2961889563
Short name T725
Test name
Test status
Simulation time 160947531242 ps
CPU time 201.07 seconds
Started Jun 02 02:46:14 PM PDT 24
Finished Jun 02 02:49:36 PM PDT 24
Peak memory 201764 kb
Host smart-146ad94a-a9f3-4a9c-be54-47171cbe11c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961889563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.2961889563
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.1464935901
Short name T720
Test name
Test status
Simulation time 332524001574 ps
CPU time 154.31 seconds
Started Jun 02 02:46:10 PM PDT 24
Finished Jun 02 02:48:46 PM PDT 24
Peak memory 201780 kb
Host smart-722491eb-37f6-4223-bc13-c9e174ccaf63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464935901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.1464935901
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.3973100936
Short name T464
Test name
Test status
Simulation time 329063152140 ps
CPU time 248.87 seconds
Started Jun 02 02:46:17 PM PDT 24
Finished Jun 02 02:50:26 PM PDT 24
Peak memory 201768 kb
Host smart-73ac4ecf-7b4f-4f20-9707-f6b508e581bb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973100936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.3973100936
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.2578950401
Short name T153
Test name
Test status
Simulation time 331812527107 ps
CPU time 46.6 seconds
Started Jun 02 02:46:04 PM PDT 24
Finished Jun 02 02:46:52 PM PDT 24
Peak memory 201740 kb
Host smart-96d3c568-0119-401b-b100-001b47f1dc60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578950401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.2578950401
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.564362294
Short name T519
Test name
Test status
Simulation time 161227387007 ps
CPU time 48.74 seconds
Started Jun 02 02:46:06 PM PDT 24
Finished Jun 02 02:46:57 PM PDT 24
Peak memory 201736 kb
Host smart-d1669672-2ab3-4aba-a987-6c3c1682d0ed
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=564362294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fixe
d.564362294
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.456584172
Short name T291
Test name
Test status
Simulation time 393845014971 ps
CPU time 889.43 seconds
Started Jun 02 02:46:09 PM PDT 24
Finished Jun 02 03:01:01 PM PDT 24
Peak memory 201740 kb
Host smart-5fb20d98-326b-4d07-a265-ebdfad974515
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456584172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_
wakeup.456584172
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.372238787
Short name T597
Test name
Test status
Simulation time 200378459649 ps
CPU time 471.1 seconds
Started Jun 02 02:46:08 PM PDT 24
Finished Jun 02 02:54:01 PM PDT 24
Peak memory 201748 kb
Host smart-b5671273-d0a2-499f-a7c1-912a737a2b65
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372238787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
adc_ctrl_filters_wakeup_fixed.372238787
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.611632730
Short name T193
Test name
Test status
Simulation time 132904082677 ps
CPU time 420.55 seconds
Started Jun 02 02:46:11 PM PDT 24
Finished Jun 02 02:53:13 PM PDT 24
Peak memory 202048 kb
Host smart-9e8f9adb-86ea-49a4-8d3c-55cd467d7388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611632730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.611632730
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.531876055
Short name T414
Test name
Test status
Simulation time 35811893516 ps
CPU time 23.95 seconds
Started Jun 02 02:46:10 PM PDT 24
Finished Jun 02 02:46:36 PM PDT 24
Peak memory 201580 kb
Host smart-142e7040-1711-42b0-94c0-ce25b030449e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531876055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.531876055
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.3608463033
Short name T585
Test name
Test status
Simulation time 3721731280 ps
CPU time 1.96 seconds
Started Jun 02 02:46:10 PM PDT 24
Finished Jun 02 02:46:14 PM PDT 24
Peak memory 201584 kb
Host smart-4ca09c40-499d-446c-b732-b87f9ca9856e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608463033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.3608463033
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.2700341863
Short name T443
Test name
Test status
Simulation time 5722509615 ps
CPU time 15.98 seconds
Started Jun 02 02:46:06 PM PDT 24
Finished Jun 02 02:46:23 PM PDT 24
Peak memory 201604 kb
Host smart-0edae478-6e92-45a2-ad8f-b7dbdd7bb00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700341863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.2700341863
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.780242743
Short name T562
Test name
Test status
Simulation time 965032898518 ps
CPU time 729.18 seconds
Started Jun 02 02:46:06 PM PDT 24
Finished Jun 02 02:58:17 PM PDT 24
Peak memory 210284 kb
Host smart-76c3281a-3f41-49c5-8e11-c4f785dbcf2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780242743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all.
780242743
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.68001441
Short name T324
Test name
Test status
Simulation time 26697232038 ps
CPU time 74.99 seconds
Started Jun 02 02:46:28 PM PDT 24
Finished Jun 02 02:47:44 PM PDT 24
Peak memory 210388 kb
Host smart-dc0f1183-5d99-4fc5-ba97-6ce8a8e6dabc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68001441 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.68001441
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.2899821406
Short name T397
Test name
Test status
Simulation time 343072103 ps
CPU time 0.76 seconds
Started Jun 02 02:46:07 PM PDT 24
Finished Jun 02 02:46:09 PM PDT 24
Peak memory 201468 kb
Host smart-e9ce037c-57bb-4b57-8347-9621be49c009
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899821406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.2899821406
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.2675998173
Short name T142
Test name
Test status
Simulation time 528810131048 ps
CPU time 1126.04 seconds
Started Jun 02 02:46:08 PM PDT 24
Finished Jun 02 03:04:56 PM PDT 24
Peak memory 201704 kb
Host smart-5ccd5754-445e-4f47-8c79-0c77ba5ca697
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675998173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.2675998173
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.158619305
Short name T83
Test name
Test status
Simulation time 167784392709 ps
CPU time 110.9 seconds
Started Jun 02 02:46:09 PM PDT 24
Finished Jun 02 02:48:02 PM PDT 24
Peak memory 201748 kb
Host smart-d5a67302-38a7-4fe2-b5c1-6e38822e478c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=158619305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrup
t_fixed.158619305
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.4238079459
Short name T516
Test name
Test status
Simulation time 165650152714 ps
CPU time 361.61 seconds
Started Jun 02 02:46:10 PM PDT 24
Finished Jun 02 02:52:14 PM PDT 24
Peak memory 201776 kb
Host smart-ca08689f-16f0-4d57-b090-f8f12a67af5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238079459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.4238079459
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.2724100023
Short name T737
Test name
Test status
Simulation time 169124120623 ps
CPU time 199.26 seconds
Started Jun 02 02:46:15 PM PDT 24
Finished Jun 02 02:49:35 PM PDT 24
Peak memory 201784 kb
Host smart-d553a609-8d04-4b8c-928d-f4be7f2b0b35
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724100023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.2724100023
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.4031451116
Short name T775
Test name
Test status
Simulation time 173456742487 ps
CPU time 207.44 seconds
Started Jun 02 02:46:07 PM PDT 24
Finished Jun 02 02:49:37 PM PDT 24
Peak memory 201840 kb
Host smart-b9d75055-6d1d-4fb7-a2ac-a16f86e352f4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031451116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.4031451116
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.716359835
Short name T527
Test name
Test status
Simulation time 605288601692 ps
CPU time 1399.52 seconds
Started Jun 02 02:46:06 PM PDT 24
Finished Jun 02 03:09:28 PM PDT 24
Peak memory 201796 kb
Host smart-1ce99f4a-e6a7-4e58-861d-9e5994c35d3d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716359835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
adc_ctrl_filters_wakeup_fixed.716359835
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.2744039811
Short name T454
Test name
Test status
Simulation time 91250174368 ps
CPU time 437.91 seconds
Started Jun 02 02:46:10 PM PDT 24
Finished Jun 02 02:53:30 PM PDT 24
Peak memory 202124 kb
Host smart-29e577b2-bd99-4418-bbbb-7a23e87bda50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744039811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.2744039811
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.3092366623
Short name T717
Test name
Test status
Simulation time 42007713846 ps
CPU time 91.75 seconds
Started Jun 02 02:46:04 PM PDT 24
Finished Jun 02 02:47:38 PM PDT 24
Peak memory 201588 kb
Host smart-996a2b2d-156d-4f9f-818c-1fd6183d53a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092366623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.3092366623
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.2387248062
Short name T10
Test name
Test status
Simulation time 3444084150 ps
CPU time 7.72 seconds
Started Jun 02 02:46:09 PM PDT 24
Finished Jun 02 02:46:19 PM PDT 24
Peak memory 201564 kb
Host smart-7bb94d7c-9793-4933-95ad-55673287a745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387248062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.2387248062
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.1510316914
Short name T777
Test name
Test status
Simulation time 5907711778 ps
CPU time 4.61 seconds
Started Jun 02 02:46:14 PM PDT 24
Finished Jun 02 02:46:20 PM PDT 24
Peak memory 201608 kb
Host smart-22abd9ed-85ec-4554-beeb-42c826bd05a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510316914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.1510316914
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.3287660642
Short name T270
Test name
Test status
Simulation time 328070661431 ps
CPU time 69.29 seconds
Started Jun 02 02:46:27 PM PDT 24
Finished Jun 02 02:47:37 PM PDT 24
Peak memory 201724 kb
Host smart-97a0eaa3-dfb8-4481-911e-9860e50cd3bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287660642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.3287660642
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.3505058444
Short name T517
Test name
Test status
Simulation time 24102391576 ps
CPU time 19.31 seconds
Started Jun 02 02:46:06 PM PDT 24
Finished Jun 02 02:46:27 PM PDT 24
Peak memory 202172 kb
Host smart-4b8d2de4-e984-4c85-8469-3a7c034478f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505058444 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.3505058444
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.1592260375
Short name T367
Test name
Test status
Simulation time 368508579 ps
CPU time 0.72 seconds
Started Jun 02 02:46:24 PM PDT 24
Finished Jun 02 02:46:25 PM PDT 24
Peak memory 201492 kb
Host smart-27e87fe3-d81e-478b-bd78-6e341dfe7116
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592260375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.1592260375
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.3708661962
Short name T222
Test name
Test status
Simulation time 620763645550 ps
CPU time 1027.54 seconds
Started Jun 02 02:46:21 PM PDT 24
Finished Jun 02 03:03:30 PM PDT 24
Peak memory 201916 kb
Host smart-639ef2db-dba6-49a4-95c2-1bde3579068b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708661962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.3708661962
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.2817169729
Short name T319
Test name
Test status
Simulation time 492094787522 ps
CPU time 921.77 seconds
Started Jun 02 02:46:07 PM PDT 24
Finished Jun 02 03:01:31 PM PDT 24
Peak memory 201724 kb
Host smart-bbc5e234-9a65-44c3-ba0b-88d0eb0a94e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817169729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.2817169729
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.3829108595
Short name T533
Test name
Test status
Simulation time 161614661546 ps
CPU time 92.8 seconds
Started Jun 02 02:46:07 PM PDT 24
Finished Jun 02 02:47:42 PM PDT 24
Peak memory 201756 kb
Host smart-f2e3d607-f483-4370-9af3-038495194114
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829108595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.3829108595
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.731216636
Short name T619
Test name
Test status
Simulation time 333510003062 ps
CPU time 124.01 seconds
Started Jun 02 02:46:18 PM PDT 24
Finished Jun 02 02:48:23 PM PDT 24
Peak memory 201692 kb
Host smart-121df9f7-966e-4070-83a6-ba5d6fa25368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731216636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.731216636
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.2956355523
Short name T653
Test name
Test status
Simulation time 167384586810 ps
CPU time 371.7 seconds
Started Jun 02 02:46:07 PM PDT 24
Finished Jun 02 02:52:20 PM PDT 24
Peak memory 201736 kb
Host smart-8701f9a3-9b45-4097-804d-2fc4c98f70af
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956355523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.2956355523
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.248174492
Short name T667
Test name
Test status
Simulation time 519548457248 ps
CPU time 258.68 seconds
Started Jun 02 02:46:09 PM PDT 24
Finished Jun 02 02:50:29 PM PDT 24
Peak memory 201780 kb
Host smart-1fae6793-89d9-43ff-b7e4-0b576080d7c4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248174492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_
wakeup.248174492
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.3858978299
Short name T463
Test name
Test status
Simulation time 407392496703 ps
CPU time 889.79 seconds
Started Jun 02 02:46:08 PM PDT 24
Finished Jun 02 03:01:00 PM PDT 24
Peak memory 201764 kb
Host smart-1f408677-217b-4979-b2ad-15cc5cafaf61
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858978299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.3858978299
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.3415414532
Short name T762
Test name
Test status
Simulation time 34104275660 ps
CPU time 74.15 seconds
Started Jun 02 02:46:10 PM PDT 24
Finished Jun 02 02:47:26 PM PDT 24
Peak memory 201596 kb
Host smart-20fb90dd-0aa3-427b-947a-ee0713e13eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415414532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.3415414532
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.997768003
Short name T509
Test name
Test status
Simulation time 4514160802 ps
CPU time 3.92 seconds
Started Jun 02 02:46:23 PM PDT 24
Finished Jun 02 02:46:27 PM PDT 24
Peak memory 201584 kb
Host smart-27c682ef-5a08-403e-93c7-dec183566b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997768003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.997768003
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.2266450103
Short name T722
Test name
Test status
Simulation time 5906430797 ps
CPU time 3.82 seconds
Started Jun 02 02:46:10 PM PDT 24
Finished Jun 02 02:46:15 PM PDT 24
Peak memory 201300 kb
Host smart-3ad0c5a3-4221-429a-96e2-e4a2f60580df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266450103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.2266450103
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.4002081392
Short name T302
Test name
Test status
Simulation time 292357470732 ps
CPU time 990.89 seconds
Started Jun 02 02:46:14 PM PDT 24
Finished Jun 02 03:02:45 PM PDT 24
Peak memory 212592 kb
Host smart-4f31044d-6491-44ec-8ae4-657b4f0590ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002081392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.4002081392
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.697932903
Short name T32
Test name
Test status
Simulation time 129383375245 ps
CPU time 142.85 seconds
Started Jun 02 02:46:12 PM PDT 24
Finished Jun 02 02:48:36 PM PDT 24
Peak memory 216412 kb
Host smart-e36954c8-9588-44b5-a1c2-e16b4e9f154a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697932903 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.697932903
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.2442614334
Short name T706
Test name
Test status
Simulation time 509400291 ps
CPU time 0.92 seconds
Started Jun 02 02:46:07 PM PDT 24
Finished Jun 02 02:46:10 PM PDT 24
Peak memory 201448 kb
Host smart-8490f0e5-1e0d-424d-a7d9-1aafd9eb2e87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442614334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.2442614334
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.382771008
Short name T188
Test name
Test status
Simulation time 536859873971 ps
CPU time 300.58 seconds
Started Jun 02 02:46:10 PM PDT 24
Finished Jun 02 02:51:13 PM PDT 24
Peak memory 201756 kb
Host smart-484782fc-5941-4565-8d5b-e29bdf8d30e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382771008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.382771008
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.1572835726
Short name T332
Test name
Test status
Simulation time 320686301074 ps
CPU time 197.37 seconds
Started Jun 02 02:46:08 PM PDT 24
Finished Jun 02 02:49:28 PM PDT 24
Peak memory 201768 kb
Host smart-86b6c1f8-d181-4c6e-86a5-3fd9f2b41669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572835726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.1572835726
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.1030798291
Short name T390
Test name
Test status
Simulation time 497447967111 ps
CPU time 339.74 seconds
Started Jun 02 02:46:15 PM PDT 24
Finished Jun 02 02:51:55 PM PDT 24
Peak memory 201764 kb
Host smart-1e533ec4-9051-4a8c-9592-cdd8a30cffb8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030798291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.1030798291
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.1908087916
Short name T93
Test name
Test status
Simulation time 160874443915 ps
CPU time 247.14 seconds
Started Jun 02 02:46:06 PM PDT 24
Finished Jun 02 02:50:15 PM PDT 24
Peak memory 201752 kb
Host smart-88a651d9-9c84-49b4-bf43-60e84b65ca75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908087916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.1908087916
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.4214240421
Short name T788
Test name
Test status
Simulation time 323006175141 ps
CPU time 163.27 seconds
Started Jun 02 02:46:10 PM PDT 24
Finished Jun 02 02:48:55 PM PDT 24
Peak memory 201772 kb
Host smart-4780f8b3-885c-4426-80d0-d3a6ef917f57
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214240421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.4214240421
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.3530770380
Short name T137
Test name
Test status
Simulation time 367218129571 ps
CPU time 189.87 seconds
Started Jun 02 02:46:07 PM PDT 24
Finished Jun 02 02:49:18 PM PDT 24
Peak memory 201728 kb
Host smart-4839d8d8-b0ef-4b0a-971d-e2298448e241
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530770380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.3530770380
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.977543807
Short name T354
Test name
Test status
Simulation time 207361477568 ps
CPU time 504.99 seconds
Started Jun 02 02:46:14 PM PDT 24
Finished Jun 02 02:54:40 PM PDT 24
Peak memory 201760 kb
Host smart-1ca8ca46-45b6-4ad3-a19b-9a80f4e29de0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977543807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
adc_ctrl_filters_wakeup_fixed.977543807
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.1258703774
Short name T199
Test name
Test status
Simulation time 131732897424 ps
CPU time 511.81 seconds
Started Jun 02 02:46:06 PM PDT 24
Finished Jun 02 02:54:39 PM PDT 24
Peak memory 202100 kb
Host smart-f545ef2a-fb0a-473f-9146-485aa06f4a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258703774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.1258703774
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.2171054251
Short name T398
Test name
Test status
Simulation time 26365166997 ps
CPU time 16.8 seconds
Started Jun 02 02:46:15 PM PDT 24
Finished Jun 02 02:46:33 PM PDT 24
Peak memory 201528 kb
Host smart-88b4153b-3ea2-42a6-9050-34ea8c570553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171054251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.2171054251
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.3689012867
Short name T672
Test name
Test status
Simulation time 2967292841 ps
CPU time 7.32 seconds
Started Jun 02 02:46:16 PM PDT 24
Finished Jun 02 02:46:24 PM PDT 24
Peak memory 201512 kb
Host smart-449a6e0a-eab4-4b1f-b2ec-3a94ce90ce3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689012867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.3689012867
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.2553620478
Short name T537
Test name
Test status
Simulation time 5715173770 ps
CPU time 15.42 seconds
Started Jun 02 02:46:16 PM PDT 24
Finished Jun 02 02:46:32 PM PDT 24
Peak memory 201552 kb
Host smart-3e65d9d7-cb66-41c8-ba56-6c67dd52cfd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553620478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.2553620478
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.557480507
Short name T175
Test name
Test status
Simulation time 283048154435 ps
CPU time 663.27 seconds
Started Jun 02 02:46:20 PM PDT 24
Finished Jun 02 02:57:24 PM PDT 24
Peak memory 202088 kb
Host smart-66562e46-8f65-4319-9a60-7992740d7a2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557480507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all.
557480507
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.1804846419
Short name T27
Test name
Test status
Simulation time 93252903047 ps
CPU time 64.41 seconds
Started Jun 02 02:46:19 PM PDT 24
Finished Jun 02 02:47:24 PM PDT 24
Peak memory 210200 kb
Host smart-16c1abad-f319-4ad6-aaa8-2fb98193e133
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804846419 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.1804846419
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.3930384779
Short name T643
Test name
Test status
Simulation time 385521924 ps
CPU time 1.54 seconds
Started Jun 02 02:46:10 PM PDT 24
Finished Jun 02 02:46:13 PM PDT 24
Peak memory 201264 kb
Host smart-e0fe751f-f154-455e-b3ea-b4edb244c313
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930384779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.3930384779
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.1670049301
Short name T327
Test name
Test status
Simulation time 317394956657 ps
CPU time 743.12 seconds
Started Jun 02 02:46:25 PM PDT 24
Finished Jun 02 02:58:49 PM PDT 24
Peak memory 201704 kb
Host smart-5a59ec82-8924-42ee-a8d7-2b7db698b901
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670049301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.1670049301
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.1005496015
Short name T334
Test name
Test status
Simulation time 490273944371 ps
CPU time 1100.26 seconds
Started Jun 02 02:46:10 PM PDT 24
Finished Jun 02 03:04:32 PM PDT 24
Peak memory 201716 kb
Host smart-ff2c1d0a-0a54-457b-b311-bbabd7e58b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005496015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.1005496015
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.1514789729
Short name T521
Test name
Test status
Simulation time 167699618018 ps
CPU time 405.74 seconds
Started Jun 02 02:46:16 PM PDT 24
Finished Jun 02 02:53:02 PM PDT 24
Peak memory 201712 kb
Host smart-71694b4e-3645-4a8f-8211-36b1cce8a1e5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514789729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.1514789729
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.3719469201
Short name T603
Test name
Test status
Simulation time 163606850125 ps
CPU time 269 seconds
Started Jun 02 02:46:26 PM PDT 24
Finished Jun 02 02:50:56 PM PDT 24
Peak memory 201736 kb
Host smart-4c72ccbf-6b50-446e-ae0e-624848a0d0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719469201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.3719469201
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.3056800737
Short name T637
Test name
Test status
Simulation time 160214899280 ps
CPU time 93.33 seconds
Started Jun 02 02:46:29 PM PDT 24
Finished Jun 02 02:48:03 PM PDT 24
Peak memory 201700 kb
Host smart-a522e60f-2015-461d-b185-a7a397298e17
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056800737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.3056800737
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.1466236596
Short name T428
Test name
Test status
Simulation time 203908251762 ps
CPU time 454.03 seconds
Started Jun 02 02:46:08 PM PDT 24
Finished Jun 02 02:53:44 PM PDT 24
Peak memory 201752 kb
Host smart-9606c648-3d41-4647-975c-d19b816906e5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466236596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.1466236596
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.1162914938
Short name T801
Test name
Test status
Simulation time 72453728016 ps
CPU time 249.55 seconds
Started Jun 02 02:46:11 PM PDT 24
Finished Jun 02 02:50:22 PM PDT 24
Peak memory 202080 kb
Host smart-a8f009d5-f604-4d5a-9224-9a375906cebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162914938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.1162914938
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.1870271336
Short name T404
Test name
Test status
Simulation time 44645880580 ps
CPU time 71.73 seconds
Started Jun 02 02:46:10 PM PDT 24
Finished Jun 02 02:47:24 PM PDT 24
Peak memory 201604 kb
Host smart-cd61ec94-b16f-45a3-807c-0c5613aaed5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870271336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.1870271336
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.3254155786
Short name T686
Test name
Test status
Simulation time 3356090029 ps
CPU time 8.36 seconds
Started Jun 02 02:46:08 PM PDT 24
Finished Jun 02 02:46:19 PM PDT 24
Peak memory 201508 kb
Host smart-29cd0ed6-a229-48f3-af30-f48751a4c095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254155786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.3254155786
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.3546999278
Short name T476
Test name
Test status
Simulation time 5870242795 ps
CPU time 10.13 seconds
Started Jun 02 02:46:07 PM PDT 24
Finished Jun 02 02:46:19 PM PDT 24
Peak memory 201552 kb
Host smart-fd2ed7bf-1c70-44e9-81e9-44c827f70f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546999278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.3546999278
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.1545769606
Short name T25
Test name
Test status
Simulation time 54748053328 ps
CPU time 79.67 seconds
Started Jun 02 02:46:05 PM PDT 24
Finished Jun 02 02:47:26 PM PDT 24
Peak memory 210456 kb
Host smart-593ea4f3-7e06-4194-86e6-3d42578659cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545769606 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.1545769606
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.3519703511
Short name T660
Test name
Test status
Simulation time 332456959 ps
CPU time 0.82 seconds
Started Jun 02 02:46:10 PM PDT 24
Finished Jun 02 02:46:13 PM PDT 24
Peak memory 201500 kb
Host smart-b1ff5139-d072-41e9-9c43-5738e8234f0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519703511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.3519703511
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.648744386
Short name T224
Test name
Test status
Simulation time 181163000085 ps
CPU time 379.42 seconds
Started Jun 02 02:46:11 PM PDT 24
Finished Jun 02 02:52:32 PM PDT 24
Peak memory 201796 kb
Host smart-8c2f4bba-b98d-4c94-bcc1-29e4e860cf16
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648744386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gati
ng.648744386
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.1353260946
Short name T442
Test name
Test status
Simulation time 490204785193 ps
CPU time 1189.76 seconds
Started Jun 02 02:46:10 PM PDT 24
Finished Jun 02 03:06:02 PM PDT 24
Peak memory 201684 kb
Host smart-83551fdf-86b9-4aa0-9796-77b863a0d3ca
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353260946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.1353260946
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.3789625721
Short name T134
Test name
Test status
Simulation time 480793460569 ps
CPU time 1086.7 seconds
Started Jun 02 02:46:21 PM PDT 24
Finished Jun 02 03:04:29 PM PDT 24
Peak memory 201824 kb
Host smart-ce8295cd-84e9-4efd-a048-a64ecf73a7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789625721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.3789625721
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.2834655075
Short name T400
Test name
Test status
Simulation time 164948674058 ps
CPU time 88.41 seconds
Started Jun 02 02:46:22 PM PDT 24
Finished Jun 02 02:47:51 PM PDT 24
Peak memory 201828 kb
Host smart-509aade5-88ea-4387-92f6-714410645372
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834655075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.2834655075
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.3951912755
Short name T212
Test name
Test status
Simulation time 170908785511 ps
CPU time 209.29 seconds
Started Jun 02 02:46:06 PM PDT 24
Finished Jun 02 02:49:36 PM PDT 24
Peak memory 201836 kb
Host smart-17a4d0ad-5189-4170-841b-0686b9a8bacb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951912755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.3951912755
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.1986013449
Short name T77
Test name
Test status
Simulation time 589993708049 ps
CPU time 1310.37 seconds
Started Jun 02 02:46:26 PM PDT 24
Finished Jun 02 03:08:17 PM PDT 24
Peak memory 201716 kb
Host smart-0d6ba575-4292-46bd-8499-f9dc4c64f5fb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986013449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.1986013449
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.3591186593
Short name T470
Test name
Test status
Simulation time 141157010112 ps
CPU time 544.88 seconds
Started Jun 02 02:46:22 PM PDT 24
Finished Jun 02 02:55:27 PM PDT 24
Peak memory 202084 kb
Host smart-c348acd0-45ab-4838-b35c-c4c386d2474a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591186593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.3591186593
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.2720514357
Short name T542
Test name
Test status
Simulation time 34446944821 ps
CPU time 75.61 seconds
Started Jun 02 02:46:05 PM PDT 24
Finished Jun 02 02:47:21 PM PDT 24
Peak memory 201496 kb
Host smart-ccd2425f-8656-4f79-b977-553e2742d697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720514357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.2720514357
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.2131513203
Short name T605
Test name
Test status
Simulation time 5116285363 ps
CPU time 7.25 seconds
Started Jun 02 02:46:31 PM PDT 24
Finished Jun 02 02:46:39 PM PDT 24
Peak memory 201536 kb
Host smart-8419e711-632b-4fec-819f-ff95b5cce36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131513203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.2131513203
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.3471355975
Short name T415
Test name
Test status
Simulation time 6011316228 ps
CPU time 3.01 seconds
Started Jun 02 02:46:04 PM PDT 24
Finished Jun 02 02:46:09 PM PDT 24
Peak memory 201640 kb
Host smart-b6b5fd72-7166-4beb-8fe7-a9d088ac5fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471355975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.3471355975
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.504427991
Short name T79
Test name
Test status
Simulation time 123549757756 ps
CPU time 502.23 seconds
Started Jun 02 02:46:08 PM PDT 24
Finished Jun 02 02:54:33 PM PDT 24
Peak memory 218248 kb
Host smart-84947a3a-9cbd-4ff7-a3d9-65d8e2b022b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504427991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all.
504427991
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.1318680063
Short name T62
Test name
Test status
Simulation time 372312116 ps
CPU time 0.91 seconds
Started Jun 02 02:46:09 PM PDT 24
Finished Jun 02 02:46:12 PM PDT 24
Peak memory 201432 kb
Host smart-4e4155b0-f447-48a7-927b-2e0689cbef99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318680063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.1318680063
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.159784130
Short name T541
Test name
Test status
Simulation time 161696084696 ps
CPU time 336.83 seconds
Started Jun 02 02:46:28 PM PDT 24
Finished Jun 02 02:52:05 PM PDT 24
Peak memory 201772 kb
Host smart-e4255dd4-247f-4c61-85c9-f9b3994c179f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159784130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gati
ng.159784130
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.795100494
Short name T163
Test name
Test status
Simulation time 495541502320 ps
CPU time 527.74 seconds
Started Jun 02 02:46:07 PM PDT 24
Finished Jun 02 02:54:57 PM PDT 24
Peak memory 201716 kb
Host smart-1ccf5a30-f5ef-4e8a-85bb-66b29e64334d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795100494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.795100494
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.183357505
Short name T178
Test name
Test status
Simulation time 334945694483 ps
CPU time 775.95 seconds
Started Jun 02 02:46:05 PM PDT 24
Finished Jun 02 02:59:02 PM PDT 24
Peak memory 201888 kb
Host smart-5bf7d767-827e-45f5-8a33-5d98619b086e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183357505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.183357505
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.1526421360
Short name T522
Test name
Test status
Simulation time 332216530648 ps
CPU time 251.89 seconds
Started Jun 02 02:46:24 PM PDT 24
Finished Jun 02 02:50:36 PM PDT 24
Peak memory 201692 kb
Host smart-16299fce-84f6-4489-8e4c-62effe9dcc0d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526421360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.1526421360
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.1479115240
Short name T657
Test name
Test status
Simulation time 495799984664 ps
CPU time 948.39 seconds
Started Jun 02 02:46:07 PM PDT 24
Finished Jun 02 03:01:57 PM PDT 24
Peak memory 201776 kb
Host smart-5e3ab4f1-d867-4c8a-adf0-afdfe2f7d8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479115240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.1479115240
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.2086885470
Short name T520
Test name
Test status
Simulation time 332186308007 ps
CPU time 346.44 seconds
Started Jun 02 02:46:20 PM PDT 24
Finished Jun 02 02:52:08 PM PDT 24
Peak memory 201700 kb
Host smart-112a53f5-ab94-49f9-83de-883838c8e732
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086885470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.2086885470
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.1762561435
Short name T568
Test name
Test status
Simulation time 202345793170 ps
CPU time 54.01 seconds
Started Jun 02 02:46:23 PM PDT 24
Finished Jun 02 02:47:18 PM PDT 24
Peak memory 201760 kb
Host smart-a9153e48-1eb8-4cb4-b11a-894ed0908df5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762561435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.1762561435
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.3637879101
Short name T360
Test name
Test status
Simulation time 388187981532 ps
CPU time 225.65 seconds
Started Jun 02 02:46:05 PM PDT 24
Finished Jun 02 02:49:52 PM PDT 24
Peak memory 201732 kb
Host smart-4db2dea3-e0d3-4419-90a6-e7ab575ce7ce
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637879101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.3637879101
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.2285982858
Short name T600
Test name
Test status
Simulation time 103583270492 ps
CPU time 337.41 seconds
Started Jun 02 02:46:06 PM PDT 24
Finished Jun 02 02:51:45 PM PDT 24
Peak memory 202068 kb
Host smart-fd1d58b4-7bdf-49f1-ab90-9ab8ebc0a615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285982858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.2285982858
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.2791191141
Short name T633
Test name
Test status
Simulation time 35119659902 ps
CPU time 23.13 seconds
Started Jun 02 02:46:17 PM PDT 24
Finished Jun 02 02:46:41 PM PDT 24
Peak memory 201536 kb
Host smart-ab46ec83-c3bc-42dc-a834-2fb8a907f1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791191141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.2791191141
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.102546011
Short name T384
Test name
Test status
Simulation time 4150375812 ps
CPU time 2.89 seconds
Started Jun 02 02:46:08 PM PDT 24
Finished Jun 02 02:46:13 PM PDT 24
Peak memory 201584 kb
Host smart-9fcc471f-6fb5-4b48-a923-6308981913d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102546011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.102546011
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.2189433216
Short name T378
Test name
Test status
Simulation time 6093371504 ps
CPU time 4 seconds
Started Jun 02 02:46:08 PM PDT 24
Finished Jun 02 02:46:14 PM PDT 24
Peak memory 201584 kb
Host smart-20d165fd-2f45-4833-aec0-0ab67164c06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189433216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.2189433216
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.2181906614
Short name T493
Test name
Test status
Simulation time 428378524591 ps
CPU time 1321.46 seconds
Started Jun 02 02:46:08 PM PDT 24
Finished Jun 02 03:08:12 PM PDT 24
Peak memory 201992 kb
Host smart-6f6f9e70-a967-4576-b20f-f219d0e378ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181906614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.2181906614
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.4145619871
Short name T335
Test name
Test status
Simulation time 199825921710 ps
CPU time 133.36 seconds
Started Jun 02 02:46:13 PM PDT 24
Finished Jun 02 02:48:27 PM PDT 24
Peak memory 210416 kb
Host smart-0e0d34bb-57f1-4947-b2f3-d176a17f5c48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145619871 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.4145619871
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.4136690515
Short name T543
Test name
Test status
Simulation time 358773328 ps
CPU time 1.35 seconds
Started Jun 02 02:45:13 PM PDT 24
Finished Jun 02 02:45:16 PM PDT 24
Peak memory 201464 kb
Host smart-9d10c5f4-dbad-4a3b-804d-64dc76f60e51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136690515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.4136690515
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.2613494076
Short name T236
Test name
Test status
Simulation time 162705054745 ps
CPU time 94.53 seconds
Started Jun 02 02:45:41 PM PDT 24
Finished Jun 02 02:47:16 PM PDT 24
Peak memory 201740 kb
Host smart-3c533fb7-9f89-4334-bb8a-ba34472ecfa8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613494076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.2613494076
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.2981039414
Short name T266
Test name
Test status
Simulation time 168273437692 ps
CPU time 111.54 seconds
Started Jun 02 02:45:40 PM PDT 24
Finished Jun 02 02:47:32 PM PDT 24
Peak memory 201696 kb
Host smart-f6f8d8b8-c4c1-4fa5-951d-89129d8e77df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981039414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.2981039414
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.667832852
Short name T154
Test name
Test status
Simulation time 498513002267 ps
CPU time 132.94 seconds
Started Jun 02 02:45:26 PM PDT 24
Finished Jun 02 02:47:41 PM PDT 24
Peak memory 201720 kb
Host smart-b613fabe-97bd-42b7-b309-441198e1e97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667832852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.667832852
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.2876137849
Short name T409
Test name
Test status
Simulation time 165374971581 ps
CPU time 92.6 seconds
Started Jun 02 02:45:50 PM PDT 24
Finished Jun 02 02:47:24 PM PDT 24
Peak memory 201776 kb
Host smart-af5b3b79-e4c3-4ffa-b184-a3786295e744
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876137849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.2876137849
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.288106169
Short name T144
Test name
Test status
Simulation time 489839120340 ps
CPU time 150.76 seconds
Started Jun 02 02:45:49 PM PDT 24
Finished Jun 02 02:48:20 PM PDT 24
Peak memory 201780 kb
Host smart-3ce9cafc-8741-4b54-bb95-b9950787eee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288106169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.288106169
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.4066484089
Short name T457
Test name
Test status
Simulation time 324549101767 ps
CPU time 167.93 seconds
Started Jun 02 02:45:44 PM PDT 24
Finished Jun 02 02:48:33 PM PDT 24
Peak memory 201728 kb
Host smart-a32471e7-d7eb-4538-a8e8-e7d29318e4b9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066484089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.4066484089
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.3500074756
Short name T241
Test name
Test status
Simulation time 171248552425 ps
CPU time 58.2 seconds
Started Jun 02 02:45:31 PM PDT 24
Finished Jun 02 02:46:30 PM PDT 24
Peak memory 201844 kb
Host smart-d574832f-6b9f-4d01-abec-5d8b3ff80c25
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500074756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.3500074756
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.3221685987
Short name T377
Test name
Test status
Simulation time 403641165858 ps
CPU time 839.47 seconds
Started Jun 02 02:45:43 PM PDT 24
Finished Jun 02 02:59:44 PM PDT 24
Peak memory 201740 kb
Host smart-5e35b38b-053a-463c-be8e-43cd052845cd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221685987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.3221685987
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.3731716370
Short name T206
Test name
Test status
Simulation time 87163697860 ps
CPU time 346.92 seconds
Started Jun 02 02:45:22 PM PDT 24
Finished Jun 02 02:51:10 PM PDT 24
Peak memory 201932 kb
Host smart-b48eb6a8-2298-40cf-883e-3a7a237f13ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731716370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.3731716370
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.2870567662
Short name T599
Test name
Test status
Simulation time 32575434841 ps
CPU time 21.06 seconds
Started Jun 02 02:45:13 PM PDT 24
Finished Jun 02 02:45:36 PM PDT 24
Peak memory 201572 kb
Host smart-06467268-bc50-431b-ab95-6b5de4cc00f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870567662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.2870567662
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.173431372
Short name T701
Test name
Test status
Simulation time 4270516002 ps
CPU time 5.64 seconds
Started Jun 02 02:45:12 PM PDT 24
Finished Jun 02 02:45:20 PM PDT 24
Peak memory 201532 kb
Host smart-15fddafd-7ee7-4aee-91ef-9161de139a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173431372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.173431372
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.474598744
Short name T56
Test name
Test status
Simulation time 4094607866 ps
CPU time 10.69 seconds
Started Jun 02 02:45:27 PM PDT 24
Finished Jun 02 02:45:39 PM PDT 24
Peak memory 217448 kb
Host smart-aae15b3b-19ef-46a8-bcde-655c9b1493b4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474598744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.474598744
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.547095342
Short name T530
Test name
Test status
Simulation time 5924165815 ps
CPU time 3.66 seconds
Started Jun 02 02:45:35 PM PDT 24
Finished Jun 02 02:45:40 PM PDT 24
Peak memory 201548 kb
Host smart-cdd3e28e-5299-4b42-b382-b9601114dcc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547095342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.547095342
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.3094475845
Short name T677
Test name
Test status
Simulation time 160297664205 ps
CPU time 157.73 seconds
Started Jun 02 02:45:41 PM PDT 24
Finished Jun 02 02:48:19 PM PDT 24
Peak memory 201712 kb
Host smart-a418f447-815e-4a2a-878a-cc10a0a5f778
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094475845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
3094475845
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.2393264464
Short name T17
Test name
Test status
Simulation time 1030485380127 ps
CPU time 262.95 seconds
Started Jun 02 02:45:38 PM PDT 24
Finished Jun 02 02:50:01 PM PDT 24
Peak memory 210320 kb
Host smart-2d95379b-6141-48f0-aa2d-61d50841c1f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393264464 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.2393264464
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.2635551903
Short name T380
Test name
Test status
Simulation time 413291776 ps
CPU time 1.07 seconds
Started Jun 02 02:46:19 PM PDT 24
Finished Jun 02 02:46:21 PM PDT 24
Peak memory 201572 kb
Host smart-d6cbcf87-301b-4d2c-9dcd-49c305b210bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635551903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.2635551903
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.1530432534
Short name T87
Test name
Test status
Simulation time 325972877567 ps
CPU time 248.72 seconds
Started Jun 02 02:46:20 PM PDT 24
Finished Jun 02 02:50:29 PM PDT 24
Peak memory 201788 kb
Host smart-19f359ac-d0fb-4fbc-b433-374044919ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530432534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.1530432534
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.1196931304
Short name T170
Test name
Test status
Simulation time 501465406661 ps
CPU time 72.71 seconds
Started Jun 02 02:46:23 PM PDT 24
Finished Jun 02 02:47:36 PM PDT 24
Peak memory 201756 kb
Host smart-0f6d4edc-308a-4e4d-b30b-0992ee4fe394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196931304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.1196931304
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.4226122043
Short name T455
Test name
Test status
Simulation time 161967288505 ps
CPU time 65.94 seconds
Started Jun 02 02:46:25 PM PDT 24
Finished Jun 02 02:47:31 PM PDT 24
Peak memory 201704 kb
Host smart-0669676b-80d3-4dfe-8915-1b87ba6b349f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226122043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.4226122043
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.2271213273
Short name T741
Test name
Test status
Simulation time 329026759127 ps
CPU time 205.66 seconds
Started Jun 02 02:46:08 PM PDT 24
Finished Jun 02 02:49:36 PM PDT 24
Peak memory 201856 kb
Host smart-7b9f5460-c251-422a-af82-9f958d8dc826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271213273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.2271213273
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.2555366007
Short name T612
Test name
Test status
Simulation time 163979745477 ps
CPU time 364.64 seconds
Started Jun 02 02:46:23 PM PDT 24
Finished Jun 02 02:52:28 PM PDT 24
Peak memory 201872 kb
Host smart-62f13b62-40dc-42c4-9937-a396bbdc3309
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555366007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.2555366007
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.554308416
Short name T186
Test name
Test status
Simulation time 189605311784 ps
CPU time 113.76 seconds
Started Jun 02 02:46:22 PM PDT 24
Finished Jun 02 02:48:16 PM PDT 24
Peak memory 201784 kb
Host smart-bc109621-9c14-4243-9d52-318f0334d92d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554308416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_
wakeup.554308416
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.3286668235
Short name T437
Test name
Test status
Simulation time 200211206649 ps
CPU time 291.69 seconds
Started Jun 02 02:46:07 PM PDT 24
Finished Jun 02 02:51:01 PM PDT 24
Peak memory 201772 kb
Host smart-f17129d8-cdc2-48d8-8b60-ed68923b87d5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286668235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.3286668235
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.1515045353
Short name T95
Test name
Test status
Simulation time 111348727651 ps
CPU time 378.74 seconds
Started Jun 02 02:46:25 PM PDT 24
Finished Jun 02 02:52:44 PM PDT 24
Peak memory 202052 kb
Host smart-01fca882-7e45-4f1a-afca-24249e975da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515045353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.1515045353
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.2949956270
Short name T458
Test name
Test status
Simulation time 28063900661 ps
CPU time 65.75 seconds
Started Jun 02 02:46:07 PM PDT 24
Finished Jun 02 02:47:15 PM PDT 24
Peak memory 201592 kb
Host smart-5958e3cd-f015-49e7-8125-1dbe957399b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949956270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.2949956270
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.3680301185
Short name T389
Test name
Test status
Simulation time 4497426372 ps
CPU time 11.09 seconds
Started Jun 02 02:46:26 PM PDT 24
Finished Jun 02 02:46:37 PM PDT 24
Peak memory 201528 kb
Host smart-0975a640-29ef-4e91-97c5-f68048697df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680301185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.3680301185
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.837412527
Short name T756
Test name
Test status
Simulation time 5656572777 ps
CPU time 13.33 seconds
Started Jun 02 02:46:07 PM PDT 24
Finished Jun 02 02:46:22 PM PDT 24
Peak memory 201568 kb
Host smart-2ca3bd3c-3d75-40d0-b72f-b755a9c7e913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837412527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.837412527
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.2258682059
Short name T28
Test name
Test status
Simulation time 145232099462 ps
CPU time 86.35 seconds
Started Jun 02 02:46:17 PM PDT 24
Finished Jun 02 02:47:43 PM PDT 24
Peak memory 210152 kb
Host smart-e9cca237-2f13-40f2-9b37-ca53d8bd2cb9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258682059 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.2258682059
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.1527100476
Short name T583
Test name
Test status
Simulation time 373272130 ps
CPU time 0.83 seconds
Started Jun 02 02:46:18 PM PDT 24
Finished Jun 02 02:46:20 PM PDT 24
Peak memory 201464 kb
Host smart-e354f6e7-d933-4dee-bcf0-a5a47bedaec3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527100476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.1527100476
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.533163478
Short name T223
Test name
Test status
Simulation time 343673547499 ps
CPU time 632.66 seconds
Started Jun 02 02:46:10 PM PDT 24
Finished Jun 02 02:56:44 PM PDT 24
Peak memory 201688 kb
Host smart-1edde717-3b99-4089-b2cd-445fd7d50519
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533163478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gati
ng.533163478
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.264741775
Short name T552
Test name
Test status
Simulation time 165576224642 ps
CPU time 111.46 seconds
Started Jun 02 02:46:10 PM PDT 24
Finished Jun 02 02:48:04 PM PDT 24
Peak memory 201764 kb
Host smart-67890763-c257-47c4-bf08-65a75e69a4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264741775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.264741775
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.2709390726
Short name T771
Test name
Test status
Simulation time 493947974456 ps
CPU time 572.37 seconds
Started Jun 02 02:46:10 PM PDT 24
Finished Jun 02 02:55:44 PM PDT 24
Peak memory 201668 kb
Host smart-b6289b9d-b4a9-45ab-a979-ba1f2c4b425d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709390726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.2709390726
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.4103242160
Short name T648
Test name
Test status
Simulation time 496258175662 ps
CPU time 322.47 seconds
Started Jun 02 02:46:11 PM PDT 24
Finished Jun 02 02:51:35 PM PDT 24
Peak memory 201728 kb
Host smart-6a1d388e-5722-413c-8eda-6af4186f094e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103242160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.4103242160
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.480914902
Short name T768
Test name
Test status
Simulation time 321704278296 ps
CPU time 685.3 seconds
Started Jun 02 02:46:06 PM PDT 24
Finished Jun 02 02:57:33 PM PDT 24
Peak memory 201824 kb
Host smart-7fb4e3ad-7e0e-40f4-b5c9-11f9054f1ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480914902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.480914902
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.1008524162
Short name T190
Test name
Test status
Simulation time 327606509925 ps
CPU time 392.49 seconds
Started Jun 02 02:46:09 PM PDT 24
Finished Jun 02 02:52:44 PM PDT 24
Peak memory 201760 kb
Host smart-90a2c920-e7c8-40af-87c4-57d3020e83ed
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008524162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.1008524162
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.1397913807
Short name T795
Test name
Test status
Simulation time 193402554759 ps
CPU time 130.8 seconds
Started Jun 02 02:46:21 PM PDT 24
Finished Jun 02 02:48:33 PM PDT 24
Peak memory 201728 kb
Host smart-3daaa9d6-2325-4b3d-8187-634026efcc4f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397913807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.1397913807
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.3880337311
Short name T544
Test name
Test status
Simulation time 598438004018 ps
CPU time 1458.98 seconds
Started Jun 02 02:46:20 PM PDT 24
Finished Jun 02 03:10:39 PM PDT 24
Peak memory 201696 kb
Host smart-e2b798d2-ca75-4fdc-87f7-3f00163daf16
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880337311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.3880337311
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.22242891
Short name T343
Test name
Test status
Simulation time 78297207035 ps
CPU time 303.41 seconds
Started Jun 02 02:46:12 PM PDT 24
Finished Jun 02 02:51:16 PM PDT 24
Peak memory 202084 kb
Host smart-7573e4f9-72d4-44c8-9903-6d3c0955df6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22242891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.22242891
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.3344234164
Short name T477
Test name
Test status
Simulation time 24806523302 ps
CPU time 29.84 seconds
Started Jun 02 02:46:16 PM PDT 24
Finished Jun 02 02:46:46 PM PDT 24
Peak memory 201520 kb
Host smart-670ed9c2-e0ae-4481-bbce-6794a2cec6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344234164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.3344234164
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.3453792620
Short name T534
Test name
Test status
Simulation time 3506317882 ps
CPU time 8.59 seconds
Started Jun 02 02:46:05 PM PDT 24
Finished Jun 02 02:46:15 PM PDT 24
Peak memory 201592 kb
Host smart-2f930106-8d16-4b9b-86ed-6aea57924609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453792620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.3453792620
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.2664642859
Short name T751
Test name
Test status
Simulation time 5615573804 ps
CPU time 4.34 seconds
Started Jun 02 02:46:07 PM PDT 24
Finished Jun 02 02:46:14 PM PDT 24
Peak memory 201604 kb
Host smart-e1e14171-ecaa-402f-986c-92fbdd762937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664642859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.2664642859
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.1734361802
Short name T26
Test name
Test status
Simulation time 163066166149 ps
CPU time 354.48 seconds
Started Jun 02 02:46:22 PM PDT 24
Finished Jun 02 02:52:17 PM PDT 24
Peak memory 201724 kb
Host smart-d340acc3-dc57-4263-a93e-32f03cfc7dde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734361802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.1734361802
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.1922725122
Short name T16
Test name
Test status
Simulation time 245758671392 ps
CPU time 261.63 seconds
Started Jun 02 02:46:21 PM PDT 24
Finished Jun 02 02:50:43 PM PDT 24
Peak memory 217908 kb
Host smart-da93466b-9122-4a0b-980d-ef5a2872cbdc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922725122 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.1922725122
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.1493269261
Short name T387
Test name
Test status
Simulation time 323018984 ps
CPU time 0.8 seconds
Started Jun 02 02:46:25 PM PDT 24
Finished Jun 02 02:46:27 PM PDT 24
Peak memory 201408 kb
Host smart-c42887e2-bb9a-4b46-9471-b64fe81ec2a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493269261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.1493269261
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.3623849973
Short name T260
Test name
Test status
Simulation time 511386604046 ps
CPU time 835.48 seconds
Started Jun 02 02:46:21 PM PDT 24
Finished Jun 02 03:00:18 PM PDT 24
Peak memory 201772 kb
Host smart-4f9a1fb2-2ada-427e-bc79-2c6039ad476c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623849973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.3623849973
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.809279879
Short name T263
Test name
Test status
Simulation time 511478842733 ps
CPU time 324.98 seconds
Started Jun 02 02:46:20 PM PDT 24
Finished Jun 02 02:51:46 PM PDT 24
Peak memory 201824 kb
Host smart-2e706bde-f13c-4527-a6cb-8cb242999969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809279879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.809279879
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.1171383853
Short name T697
Test name
Test status
Simulation time 166722987112 ps
CPU time 379.24 seconds
Started Jun 02 02:46:16 PM PDT 24
Finished Jun 02 02:52:36 PM PDT 24
Peak memory 201848 kb
Host smart-e4b9c4ce-ca71-4804-a766-c80a78a6468e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171383853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.1171383853
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.2499536202
Short name T551
Test name
Test status
Simulation time 492414580787 ps
CPU time 1174.87 seconds
Started Jun 02 02:46:10 PM PDT 24
Finished Jun 02 03:05:47 PM PDT 24
Peak memory 201664 kb
Host smart-25c2bafc-f40a-4b8a-8d52-8c176d683f03
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499536202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.2499536202
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.3202114585
Short name T271
Test name
Test status
Simulation time 331306149153 ps
CPU time 492.21 seconds
Started Jun 02 02:46:15 PM PDT 24
Finished Jun 02 02:54:27 PM PDT 24
Peak memory 201688 kb
Host smart-cf9c46ed-b165-4342-b886-e6bcdd22405e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202114585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.3202114585
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.2304907255
Short name T536
Test name
Test status
Simulation time 494747576824 ps
CPU time 250.9 seconds
Started Jun 02 02:46:07 PM PDT 24
Finished Jun 02 02:50:21 PM PDT 24
Peak memory 201696 kb
Host smart-5cc6e905-f633-4be2-a036-4ae65ea97913
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304907255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.2304907255
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.165637164
Short name T310
Test name
Test status
Simulation time 365956862389 ps
CPU time 629.67 seconds
Started Jun 02 02:46:25 PM PDT 24
Finished Jun 02 02:56:56 PM PDT 24
Peak memory 201792 kb
Host smart-18402675-c9b3-4924-9ab4-17091258eefa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165637164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_
wakeup.165637164
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.4111078588
Short name T447
Test name
Test status
Simulation time 413992370833 ps
CPU time 530.89 seconds
Started Jun 02 02:46:26 PM PDT 24
Finished Jun 02 02:55:17 PM PDT 24
Peak memory 201844 kb
Host smart-a2481305-e389-4e03-a9eb-c07407f05e63
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111078588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.4111078588
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.2699404283
Short name T475
Test name
Test status
Simulation time 113208863740 ps
CPU time 469 seconds
Started Jun 02 02:46:34 PM PDT 24
Finished Jun 02 02:54:24 PM PDT 24
Peak memory 202136 kb
Host smart-c28c9ab2-a129-446d-aa4d-540217e4da48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699404283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.2699404283
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.2985536727
Short name T673
Test name
Test status
Simulation time 41748337280 ps
CPU time 106.82 seconds
Started Jun 02 02:46:10 PM PDT 24
Finished Jun 02 02:47:59 PM PDT 24
Peak memory 201612 kb
Host smart-6a990ab3-ea44-40b2-99dc-ff944cd8739c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985536727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.2985536727
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.4272334320
Short name T745
Test name
Test status
Simulation time 3484744021 ps
CPU time 7.27 seconds
Started Jun 02 02:46:20 PM PDT 24
Finished Jun 02 02:46:28 PM PDT 24
Peak memory 201692 kb
Host smart-34c0997f-b009-4674-b286-7af7be40bb18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272334320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.4272334320
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.146008348
Short name T75
Test name
Test status
Simulation time 6120703967 ps
CPU time 3.3 seconds
Started Jun 02 02:46:25 PM PDT 24
Finished Jun 02 02:46:29 PM PDT 24
Peak memory 201752 kb
Host smart-2f974705-e32e-4a43-b3ba-9617b11301cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146008348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.146008348
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.1098604924
Short name T491
Test name
Test status
Simulation time 282203494043 ps
CPU time 437.31 seconds
Started Jun 02 02:46:30 PM PDT 24
Finished Jun 02 02:53:48 PM PDT 24
Peak memory 202140 kb
Host smart-c2478f8a-075a-43be-ac13-3a4f729a0375
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098604924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.1098604924
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.817559971
Short name T30
Test name
Test status
Simulation time 242968301406 ps
CPU time 284.8 seconds
Started Jun 02 02:46:32 PM PDT 24
Finished Jun 02 02:51:17 PM PDT 24
Peak memory 210400 kb
Host smart-2614c985-4ba7-43b3-8a25-a72dfb1501e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817559971 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.817559971
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.2198064555
Short name T532
Test name
Test status
Simulation time 381076847 ps
CPU time 0.71 seconds
Started Jun 02 02:46:34 PM PDT 24
Finished Jun 02 02:46:36 PM PDT 24
Peak memory 201392 kb
Host smart-53064f26-6636-423d-a4de-1513ae6cf271
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198064555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.2198064555
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.2328376504
Short name T740
Test name
Test status
Simulation time 518860568333 ps
CPU time 358.6 seconds
Started Jun 02 02:46:26 PM PDT 24
Finished Jun 02 02:52:25 PM PDT 24
Peak memory 201768 kb
Host smart-71895e35-9395-4fd0-81d3-a9c1527330dd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328376504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.2328376504
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.1919143629
Short name T138
Test name
Test status
Simulation time 179984067035 ps
CPU time 33 seconds
Started Jun 02 02:46:24 PM PDT 24
Finished Jun 02 02:46:57 PM PDT 24
Peak memory 201620 kb
Host smart-7821d382-a249-453f-ba10-9f3b432cd63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919143629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.1919143629
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.890138172
Short name T92
Test name
Test status
Simulation time 486994873976 ps
CPU time 589.39 seconds
Started Jun 02 02:46:31 PM PDT 24
Finished Jun 02 02:56:21 PM PDT 24
Peak memory 201832 kb
Host smart-04ced201-2306-40dd-ae4c-97fc26baaa94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890138172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.890138172
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.2589502273
Short name T678
Test name
Test status
Simulation time 491767677091 ps
CPU time 585.92 seconds
Started Jun 02 02:46:26 PM PDT 24
Finished Jun 02 02:56:13 PM PDT 24
Peak memory 201772 kb
Host smart-2e1b7714-b0b9-4768-a245-e3bb1eaf0238
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589502273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.2589502273
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.2793896991
Short name T547
Test name
Test status
Simulation time 487839141187 ps
CPU time 747.98 seconds
Started Jun 02 02:46:35 PM PDT 24
Finished Jun 02 02:59:03 PM PDT 24
Peak memory 201680 kb
Host smart-0dffa2f9-83aa-42b1-a487-16abc7e2fbed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793896991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.2793896991
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.1559195017
Short name T495
Test name
Test status
Simulation time 489333503352 ps
CPU time 255.98 seconds
Started Jun 02 02:46:27 PM PDT 24
Finished Jun 02 02:50:43 PM PDT 24
Peak memory 201692 kb
Host smart-8a6f9a88-f4c9-4029-bf6d-1232cadb4d01
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559195017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.1559195017
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.3901458763
Short name T297
Test name
Test status
Simulation time 613539544728 ps
CPU time 1490.08 seconds
Started Jun 02 02:46:35 PM PDT 24
Finished Jun 02 03:11:26 PM PDT 24
Peak memory 201804 kb
Host smart-2efbcc1a-2e77-43b1-9e00-57f16bcaa0f3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901458763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.3901458763
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.3986287036
Short name T446
Test name
Test status
Simulation time 403424102648 ps
CPU time 235.99 seconds
Started Jun 02 02:46:21 PM PDT 24
Finished Jun 02 02:50:18 PM PDT 24
Peak memory 201764 kb
Host smart-582f8418-42f6-4601-8897-ed1ca29f55f1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986287036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.3986287036
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.1561509788
Short name T570
Test name
Test status
Simulation time 109535761077 ps
CPU time 590 seconds
Started Jun 02 02:46:16 PM PDT 24
Finished Jun 02 02:56:07 PM PDT 24
Peak memory 202124 kb
Host smart-b8fc3cad-de99-406d-b0a7-67128c06bc4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561509788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.1561509788
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.3896701038
Short name T451
Test name
Test status
Simulation time 45130263153 ps
CPU time 114.43 seconds
Started Jun 02 02:46:19 PM PDT 24
Finished Jun 02 02:48:14 PM PDT 24
Peak memory 201600 kb
Host smart-64ec5e2a-dc27-4e20-95c9-da747607c371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896701038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.3896701038
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.3099785370
Short name T88
Test name
Test status
Simulation time 3670931014 ps
CPU time 5.19 seconds
Started Jun 02 02:46:37 PM PDT 24
Finished Jun 02 02:46:42 PM PDT 24
Peak memory 201568 kb
Host smart-e365684c-4c60-48fb-85d5-e135cde06330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099785370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.3099785370
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.3915842166
Short name T357
Test name
Test status
Simulation time 5759663304 ps
CPU time 14.36 seconds
Started Jun 02 02:46:19 PM PDT 24
Finished Jun 02 02:46:34 PM PDT 24
Peak memory 201580 kb
Host smart-c4a1e181-d724-4f37-bd31-cb77f56fe03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915842166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.3915842166
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.2943580143
Short name T269
Test name
Test status
Simulation time 365198197554 ps
CPU time 833.24 seconds
Started Jun 02 02:46:21 PM PDT 24
Finished Jun 02 03:00:16 PM PDT 24
Peak memory 201820 kb
Host smart-91924d73-b1b3-4edb-bd83-fd8e364051ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943580143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.2943580143
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.219087057
Short name T731
Test name
Test status
Simulation time 561527444 ps
CPU time 0.96 seconds
Started Jun 02 02:46:34 PM PDT 24
Finished Jun 02 02:46:36 PM PDT 24
Peak memory 201416 kb
Host smart-beb1489a-2f97-4757-b1ce-cb4d86244fb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219087057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.219087057
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.1565241954
Short name T299
Test name
Test status
Simulation time 525811538296 ps
CPU time 199.34 seconds
Started Jun 02 02:46:31 PM PDT 24
Finished Jun 02 02:49:51 PM PDT 24
Peak memory 201812 kb
Host smart-8cd2d134-6a17-4056-af89-5d5f85e64f2c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565241954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.1565241954
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.750042717
Short name T692
Test name
Test status
Simulation time 162151437283 ps
CPU time 99.79 seconds
Started Jun 02 02:46:29 PM PDT 24
Finished Jun 02 02:48:10 PM PDT 24
Peak memory 201760 kb
Host smart-c89a5dfd-fc67-4a18-ac0d-7ae3f9050cd7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=750042717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrup
t_fixed.750042717
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.1226999494
Short name T553
Test name
Test status
Simulation time 165527698404 ps
CPU time 197.9 seconds
Started Jun 02 02:46:24 PM PDT 24
Finished Jun 02 02:49:42 PM PDT 24
Peak memory 202068 kb
Host smart-8155ef62-1569-40d5-a705-67ad510ebbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226999494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.1226999494
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.504931259
Short name T539
Test name
Test status
Simulation time 326894577548 ps
CPU time 204.61 seconds
Started Jun 02 02:46:32 PM PDT 24
Finished Jun 02 02:49:57 PM PDT 24
Peak memory 201828 kb
Host smart-7a5201f3-dfdf-4023-8557-1dbe276e2326
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=504931259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fixe
d.504931259
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.2911574810
Short name T545
Test name
Test status
Simulation time 390023356896 ps
CPU time 167.37 seconds
Started Jun 02 02:46:23 PM PDT 24
Finished Jun 02 02:49:11 PM PDT 24
Peak memory 202096 kb
Host smart-ce7b0f0e-5e2b-48ea-be8e-c6f5e0b3bdcb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911574810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.2911574810
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.2180622639
Short name T465
Test name
Test status
Simulation time 583951615484 ps
CPU time 352.42 seconds
Started Jun 02 02:46:25 PM PDT 24
Finished Jun 02 02:52:18 PM PDT 24
Peak memory 201848 kb
Host smart-fb48158c-3072-4d0d-b981-7f727482e2cc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180622639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.2180622639
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.3441909347
Short name T205
Test name
Test status
Simulation time 119628585841 ps
CPU time 639.9 seconds
Started Jun 02 02:46:38 PM PDT 24
Finished Jun 02 02:57:18 PM PDT 24
Peak memory 202172 kb
Host smart-1d49a592-caaf-4a0d-826f-359acc5de276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441909347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.3441909347
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.1143942112
Short name T776
Test name
Test status
Simulation time 43370739703 ps
CPU time 94.64 seconds
Started Jun 02 02:46:24 PM PDT 24
Finished Jun 02 02:47:59 PM PDT 24
Peak memory 201564 kb
Host smart-f0406163-bfe3-46eb-a35e-e5dfda6ea606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143942112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.1143942112
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.1921952978
Short name T394
Test name
Test status
Simulation time 3974385287 ps
CPU time 2.98 seconds
Started Jun 02 02:46:23 PM PDT 24
Finished Jun 02 02:46:26 PM PDT 24
Peak memory 201556 kb
Host smart-4e4f24e8-4433-4ef3-950f-211060f45a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921952978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.1921952978
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.954678971
Short name T761
Test name
Test status
Simulation time 6173730973 ps
CPU time 2.98 seconds
Started Jun 02 02:46:21 PM PDT 24
Finished Jun 02 02:46:25 PM PDT 24
Peak memory 201628 kb
Host smart-114807cc-c45e-40a2-b1d6-b4f6f9b2a5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954678971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.954678971
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.486049064
Short name T392
Test name
Test status
Simulation time 307396903 ps
CPU time 0.8 seconds
Started Jun 02 02:46:35 PM PDT 24
Finished Jun 02 02:46:37 PM PDT 24
Peak memory 201436 kb
Host smart-7ee8206d-a7db-49ec-826c-bd50804969c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486049064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.486049064
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.2156257776
Short name T80
Test name
Test status
Simulation time 334090297511 ps
CPU time 111.41 seconds
Started Jun 02 02:46:34 PM PDT 24
Finished Jun 02 02:48:26 PM PDT 24
Peak memory 201776 kb
Host smart-d9f17d5d-e5e7-47b8-acd1-9c1cfd9273a0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156257776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.2156257776
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.886959913
Short name T169
Test name
Test status
Simulation time 322766571045 ps
CPU time 190.16 seconds
Started Jun 02 02:46:37 PM PDT 24
Finished Jun 02 02:49:48 PM PDT 24
Peak memory 201864 kb
Host smart-d49ead6b-ac54-40a5-a0c0-aebfed209612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886959913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.886959913
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.1965286059
Short name T393
Test name
Test status
Simulation time 505046662201 ps
CPU time 723.87 seconds
Started Jun 02 02:46:27 PM PDT 24
Finished Jun 02 02:58:32 PM PDT 24
Peak memory 201712 kb
Host smart-62b62fef-6f66-40b0-9dce-f17bbb14a2dc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965286059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.1965286059
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.2637073866
Short name T766
Test name
Test status
Simulation time 489218379503 ps
CPU time 1118 seconds
Started Jun 02 02:46:27 PM PDT 24
Finished Jun 02 03:05:06 PM PDT 24
Peak memory 201776 kb
Host smart-8cb37d96-efe8-434c-9cf8-a3d634797d14
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637073866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.2637073866
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.3040180603
Short name T127
Test name
Test status
Simulation time 354785402873 ps
CPU time 901.63 seconds
Started Jun 02 02:46:37 PM PDT 24
Finished Jun 02 03:01:39 PM PDT 24
Peak memory 201788 kb
Host smart-9a6e87f2-4db6-4a57-9592-b192b6e41af6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040180603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.3040180603
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.3246912104
Short name T688
Test name
Test status
Simulation time 605295557741 ps
CPU time 691.28 seconds
Started Jun 02 02:46:34 PM PDT 24
Finished Jun 02 02:58:06 PM PDT 24
Peak memory 201788 kb
Host smart-da399980-65f4-4585-994e-35ec30f852d5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246912104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.3246912104
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.2573386629
Short name T342
Test name
Test status
Simulation time 93535163323 ps
CPU time 462.1 seconds
Started Jun 02 02:46:40 PM PDT 24
Finished Jun 02 02:54:22 PM PDT 24
Peak memory 202180 kb
Host smart-66febd50-d08d-42ee-9ed3-24d23217e57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573386629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.2573386629
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.712022193
Short name T636
Test name
Test status
Simulation time 23226394028 ps
CPU time 28.26 seconds
Started Jun 02 02:46:33 PM PDT 24
Finished Jun 02 02:47:01 PM PDT 24
Peak memory 201852 kb
Host smart-b790a969-d56f-46d4-b7ab-b711f9ebbdc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712022193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.712022193
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.3169793026
Short name T790
Test name
Test status
Simulation time 3071618570 ps
CPU time 8.23 seconds
Started Jun 02 02:46:34 PM PDT 24
Finished Jun 02 02:46:43 PM PDT 24
Peak memory 201540 kb
Host smart-1b3e2405-4c04-48ce-9463-701868ebc378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169793026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.3169793026
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.1795181913
Short name T682
Test name
Test status
Simulation time 5894992720 ps
CPU time 14.61 seconds
Started Jun 02 02:46:39 PM PDT 24
Finished Jun 02 02:46:54 PM PDT 24
Peak memory 201600 kb
Host smart-849ea8f4-4069-4928-a050-d0e12275a3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795181913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.1795181913
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.992998047
Short name T238
Test name
Test status
Simulation time 390757312153 ps
CPU time 232.12 seconds
Started Jun 02 02:46:35 PM PDT 24
Finished Jun 02 02:50:28 PM PDT 24
Peak memory 201764 kb
Host smart-09ef3a18-9ceb-4190-bcf7-9554e876bb27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992998047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all.
992998047
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.4211988207
Short name T646
Test name
Test status
Simulation time 59955608250 ps
CPU time 104.15 seconds
Started Jun 02 02:46:37 PM PDT 24
Finished Jun 02 02:48:22 PM PDT 24
Peak memory 210460 kb
Host smart-9b1d48d1-2de4-4d07-a3ab-86200cecb041
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211988207 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.4211988207
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.4003865914
Short name T439
Test name
Test status
Simulation time 352297675 ps
CPU time 1.02 seconds
Started Jun 02 02:46:43 PM PDT 24
Finished Jun 02 02:46:45 PM PDT 24
Peak memory 201464 kb
Host smart-abb92e08-39aa-4640-90a2-69900066230f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003865914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.4003865914
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.2307556906
Short name T651
Test name
Test status
Simulation time 332046116179 ps
CPU time 375.65 seconds
Started Jun 02 02:46:39 PM PDT 24
Finished Jun 02 02:52:55 PM PDT 24
Peak memory 201808 kb
Host smart-f0f159bb-91a1-4ab6-878b-369f1e01e3c6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307556906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.2307556906
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.1762515756
Short name T12
Test name
Test status
Simulation time 325884924303 ps
CPU time 753.5 seconds
Started Jun 02 02:46:39 PM PDT 24
Finished Jun 02 02:59:13 PM PDT 24
Peak memory 201740 kb
Host smart-c4774183-816f-4fbc-93a4-ddc50de5a5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762515756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.1762515756
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.4180310271
Short name T7
Test name
Test status
Simulation time 171602438703 ps
CPU time 98.09 seconds
Started Jun 02 02:46:39 PM PDT 24
Finished Jun 02 02:48:18 PM PDT 24
Peak memory 201848 kb
Host smart-9eb547d7-ff59-4820-b10e-64e824b6bed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180310271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.4180310271
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.2859220215
Short name T694
Test name
Test status
Simulation time 320541095471 ps
CPU time 774.23 seconds
Started Jun 02 02:46:39 PM PDT 24
Finished Jun 02 02:59:34 PM PDT 24
Peak memory 201784 kb
Host smart-148eee22-d1a5-4c2e-acf1-38d238404ddf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859220215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.2859220215
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.2545893478
Short name T650
Test name
Test status
Simulation time 338455233372 ps
CPU time 125.54 seconds
Started Jun 02 02:46:45 PM PDT 24
Finished Jun 02 02:48:51 PM PDT 24
Peak memory 201736 kb
Host smart-9b2d3a7f-2d0e-4c65-b007-dc1b69f440c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545893478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.2545893478
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.3852096067
Short name T146
Test name
Test status
Simulation time 321564103547 ps
CPU time 99.63 seconds
Started Jun 02 02:46:38 PM PDT 24
Finished Jun 02 02:48:18 PM PDT 24
Peak memory 201840 kb
Host smart-a23d7aa4-7d90-47dc-bf09-94e832b499a2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852096067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.3852096067
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.400562690
Short name T610
Test name
Test status
Simulation time 364533515487 ps
CPU time 409.58 seconds
Started Jun 02 02:46:42 PM PDT 24
Finished Jun 02 02:53:32 PM PDT 24
Peak memory 201764 kb
Host smart-f6a6e99f-b26f-4ed2-8140-89d9d2e99199
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400562690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_
wakeup.400562690
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.1499645331
Short name T759
Test name
Test status
Simulation time 128895578132 ps
CPU time 676.55 seconds
Started Jun 02 02:46:44 PM PDT 24
Finished Jun 02 02:58:01 PM PDT 24
Peak memory 202132 kb
Host smart-ed4487de-a38d-411a-829f-9bfd6c5770c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499645331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.1499645331
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.3626492769
Short name T614
Test name
Test status
Simulation time 24050752888 ps
CPU time 13.93 seconds
Started Jun 02 02:46:44 PM PDT 24
Finished Jun 02 02:46:59 PM PDT 24
Peak memory 201536 kb
Host smart-dc85f1d7-a599-48bf-9958-7f31877b1ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626492769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.3626492769
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.4051002015
Short name T728
Test name
Test status
Simulation time 5141051575 ps
CPU time 12.62 seconds
Started Jun 02 02:46:39 PM PDT 24
Finished Jun 02 02:46:52 PM PDT 24
Peak memory 201588 kb
Host smart-9f223a8d-087e-45f5-a336-b196afb4bc38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051002015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.4051002015
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.2812600274
Short name T683
Test name
Test status
Simulation time 6003890377 ps
CPU time 3.86 seconds
Started Jun 02 02:46:43 PM PDT 24
Finished Jun 02 02:46:47 PM PDT 24
Peak memory 201564 kb
Host smart-39ed19fc-d0a5-41ab-a425-abff6dc17fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812600274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.2812600274
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.3980822097
Short name T601
Test name
Test status
Simulation time 342835453456 ps
CPU time 399.32 seconds
Started Jun 02 02:46:47 PM PDT 24
Finished Jun 02 02:53:27 PM PDT 24
Peak memory 201768 kb
Host smart-48ae08ec-0164-4d43-986e-708a5c3af166
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980822097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.3980822097
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.2293036010
Short name T500
Test name
Test status
Simulation time 537816439 ps
CPU time 1.09 seconds
Started Jun 02 02:46:50 PM PDT 24
Finished Jun 02 02:46:52 PM PDT 24
Peak memory 201500 kb
Host smart-d70fbb30-abd0-48dc-9420-6f315b202988
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293036010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.2293036010
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.2406880468
Short name T704
Test name
Test status
Simulation time 166826324762 ps
CPU time 142.74 seconds
Started Jun 02 02:46:49 PM PDT 24
Finished Jun 02 02:49:12 PM PDT 24
Peak memory 201868 kb
Host smart-2dad28c9-a4d7-4475-a03c-062a4ca3d329
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406880468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.2406880468
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.1041559963
Short name T135
Test name
Test status
Simulation time 327700115925 ps
CPU time 791 seconds
Started Jun 02 02:46:44 PM PDT 24
Finished Jun 02 02:59:55 PM PDT 24
Peak memory 201776 kb
Host smart-8a11a630-b3d0-4ae2-80b4-2b00f18f9c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041559963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.1041559963
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.1450977694
Short name T417
Test name
Test status
Simulation time 499713222720 ps
CPU time 1134.69 seconds
Started Jun 02 02:46:47 PM PDT 24
Finished Jun 02 03:05:43 PM PDT 24
Peak memory 201752 kb
Host smart-4119a999-7852-429e-8dcb-bf441bd0c99d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450977694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.1450977694
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.801159046
Short name T571
Test name
Test status
Simulation time 485884902721 ps
CPU time 1205.68 seconds
Started Jun 02 02:46:47 PM PDT 24
Finished Jun 02 03:06:53 PM PDT 24
Peak memory 201740 kb
Host smart-0d0dcbfb-6a04-4136-bba4-1d12a8907068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801159046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.801159046
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.1167736623
Short name T171
Test name
Test status
Simulation time 485059091767 ps
CPU time 1182.39 seconds
Started Jun 02 02:46:44 PM PDT 24
Finished Jun 02 03:06:27 PM PDT 24
Peak memory 201664 kb
Host smart-fe4f43a6-d2c2-4ea9-99b9-de1aeeed30c2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167736623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.1167736623
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.3386864795
Short name T227
Test name
Test status
Simulation time 192623662289 ps
CPU time 99.42 seconds
Started Jun 02 02:46:47 PM PDT 24
Finished Jun 02 02:48:27 PM PDT 24
Peak memory 201836 kb
Host smart-3d34152f-705c-4ccc-bc79-90583ce7756e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386864795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.3386864795
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.907035171
Short name T76
Test name
Test status
Simulation time 196398327864 ps
CPU time 449.88 seconds
Started Jun 02 02:46:46 PM PDT 24
Finished Jun 02 02:54:16 PM PDT 24
Peak memory 201772 kb
Host smart-e22e7567-21a9-4449-b3ac-ce390f05fe8a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907035171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
adc_ctrl_filters_wakeup_fixed.907035171
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.4179215398
Short name T628
Test name
Test status
Simulation time 97056641395 ps
CPU time 496.51 seconds
Started Jun 02 02:46:51 PM PDT 24
Finished Jun 02 02:55:08 PM PDT 24
Peak memory 202080 kb
Host smart-9bfc8361-3c81-43d4-bc02-20abbd8ed564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179215398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.4179215398
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.3108691619
Short name T592
Test name
Test status
Simulation time 23508449301 ps
CPU time 57.17 seconds
Started Jun 02 02:46:50 PM PDT 24
Finished Jun 02 02:47:48 PM PDT 24
Peak memory 201576 kb
Host smart-29c6359d-4463-4fc6-839b-558ca4f0fb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108691619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.3108691619
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.1248716222
Short name T513
Test name
Test status
Simulation time 3676041837 ps
CPU time 1.37 seconds
Started Jun 02 02:46:54 PM PDT 24
Finished Jun 02 02:46:56 PM PDT 24
Peak memory 201568 kb
Host smart-07ce7f4f-41ba-4125-92eb-12dda45dee4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248716222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.1248716222
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.79796304
Short name T789
Test name
Test status
Simulation time 5764842336 ps
CPU time 4.1 seconds
Started Jun 02 02:46:44 PM PDT 24
Finished Jun 02 02:46:48 PM PDT 24
Peak memory 201532 kb
Host smart-da35b951-976b-4420-96ee-cddb62b4c990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79796304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.79796304
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.358138781
Short name T685
Test name
Test status
Simulation time 288203198213 ps
CPU time 624.94 seconds
Started Jun 02 02:46:49 PM PDT 24
Finished Jun 02 02:57:15 PM PDT 24
Peak memory 202100 kb
Host smart-5cdfce77-159e-43d5-8dd6-2206c121d2a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358138781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all.
358138781
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.1479356729
Short name T85
Test name
Test status
Simulation time 254327150344 ps
CPU time 247.9 seconds
Started Jun 02 02:46:51 PM PDT 24
Finished Jun 02 02:51:00 PM PDT 24
Peak memory 210688 kb
Host smart-018a88ed-9391-4b9d-a9d4-40e475608f97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479356729 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.1479356729
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.496378612
Short name T561
Test name
Test status
Simulation time 391597466 ps
CPU time 1.46 seconds
Started Jun 02 02:46:51 PM PDT 24
Finished Jun 02 02:46:53 PM PDT 24
Peak memory 201468 kb
Host smart-bbbbb5e0-e223-4a24-937c-881824a10efb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496378612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.496378612
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.1404896911
Short name T590
Test name
Test status
Simulation time 263553186545 ps
CPU time 295.02 seconds
Started Jun 02 02:46:50 PM PDT 24
Finished Jun 02 02:51:45 PM PDT 24
Peak memory 201760 kb
Host smart-7ad5efa6-eee3-4664-9ef6-231df3596f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404896911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.1404896911
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.634654559
Short name T3
Test name
Test status
Simulation time 162951021063 ps
CPU time 154.31 seconds
Started Jun 02 02:46:51 PM PDT 24
Finished Jun 02 02:49:26 PM PDT 24
Peak memory 201876 kb
Host smart-94b704fa-948c-477e-948f-efbde042ef1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634654559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.634654559
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.2457431801
Short name T456
Test name
Test status
Simulation time 170916809095 ps
CPU time 401.89 seconds
Started Jun 02 02:46:55 PM PDT 24
Finished Jun 02 02:53:38 PM PDT 24
Peak memory 201744 kb
Host smart-2dbf01b6-3e64-4f1e-b90b-38bfc1ebd372
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457431801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.2457431801
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.3258496528
Short name T733
Test name
Test status
Simulation time 332739121973 ps
CPU time 748.15 seconds
Started Jun 02 02:46:51 PM PDT 24
Finished Jun 02 02:59:20 PM PDT 24
Peak memory 201948 kb
Host smart-d24c6d6d-3d64-4526-a7c2-a81914f05a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258496528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.3258496528
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.1564661208
Short name T349
Test name
Test status
Simulation time 161761626202 ps
CPU time 334.68 seconds
Started Jun 02 02:46:50 PM PDT 24
Finished Jun 02 02:52:26 PM PDT 24
Peak memory 201724 kb
Host smart-4dd62003-917c-4e7b-8692-88f400dbce69
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564661208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.1564661208
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.1165704656
Short name T594
Test name
Test status
Simulation time 353198937640 ps
CPU time 292.74 seconds
Started Jun 02 02:46:53 PM PDT 24
Finished Jun 02 02:51:46 PM PDT 24
Peak memory 201804 kb
Host smart-1a7d3434-4995-40aa-980b-93a3f9facd4d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165704656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.1165704656
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.1224663601
Short name T405
Test name
Test status
Simulation time 608658170606 ps
CPU time 1311.78 seconds
Started Jun 02 02:46:52 PM PDT 24
Finished Jun 02 03:08:45 PM PDT 24
Peak memory 201704 kb
Host smart-8540ead5-a27d-43b0-a9e8-56bf214068cb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224663601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.1224663601
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.182705913
Short name T200
Test name
Test status
Simulation time 84256756071 ps
CPU time 281.49 seconds
Started Jun 02 02:46:54 PM PDT 24
Finished Jun 02 02:51:36 PM PDT 24
Peak memory 202104 kb
Host smart-5bebeb6a-b5f4-4fbf-8557-6151d927a381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182705913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.182705913
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.3905886806
Short name T192
Test name
Test status
Simulation time 27746854310 ps
CPU time 61.01 seconds
Started Jun 02 02:46:52 PM PDT 24
Finished Jun 02 02:47:53 PM PDT 24
Peak memory 201568 kb
Host smart-db74b288-6c18-42ea-808f-7e58cf7c4c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905886806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.3905886806
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.2800527516
Short name T727
Test name
Test status
Simulation time 5353761467 ps
CPU time 13.37 seconds
Started Jun 02 02:46:52 PM PDT 24
Finished Jun 02 02:47:06 PM PDT 24
Peak memory 201596 kb
Host smart-cdb624ae-581d-4f0f-bcd2-08bec8870d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800527516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.2800527516
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.797390932
Short name T526
Test name
Test status
Simulation time 6095525417 ps
CPU time 7.7 seconds
Started Jun 02 02:46:50 PM PDT 24
Finished Jun 02 02:46:59 PM PDT 24
Peak memory 201500 kb
Host smart-fb198488-7dca-4af0-a030-871e7834bda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797390932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.797390932
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.3175493243
Short name T598
Test name
Test status
Simulation time 169440210709 ps
CPU time 397.92 seconds
Started Jun 02 02:46:52 PM PDT 24
Finished Jun 02 02:53:31 PM PDT 24
Peak memory 201708 kb
Host smart-88fbfd52-ac14-4024-bb32-f77ff27cd2ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175493243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.3175493243
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.1417183767
Short name T760
Test name
Test status
Simulation time 158034693319 ps
CPU time 510.47 seconds
Started Jun 02 02:46:54 PM PDT 24
Finished Jun 02 02:55:25 PM PDT 24
Peak memory 210480 kb
Host smart-ec3bd5b8-a499-4481-8eae-a0ba44c0a8eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417183767 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.1417183767
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.873749312
Short name T700
Test name
Test status
Simulation time 554155094 ps
CPU time 0.97 seconds
Started Jun 02 02:46:58 PM PDT 24
Finished Jun 02 02:46:59 PM PDT 24
Peak memory 201392 kb
Host smart-579b76a3-e4b6-42f9-9a6e-aa4bebfc8f1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873749312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.873749312
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.3399740411
Short name T487
Test name
Test status
Simulation time 380137683450 ps
CPU time 702.21 seconds
Started Jun 02 02:46:58 PM PDT 24
Finished Jun 02 02:58:41 PM PDT 24
Peak memory 201724 kb
Host smart-7caf973a-83f6-4cc7-b97d-b0d6d23be243
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399740411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.3399740411
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.2814072735
Short name T232
Test name
Test status
Simulation time 161268023086 ps
CPU time 85.01 seconds
Started Jun 02 02:46:55 PM PDT 24
Finished Jun 02 02:48:21 PM PDT 24
Peak memory 201764 kb
Host smart-9eb2d065-c37c-4873-8dd8-55693ac64f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814072735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.2814072735
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.4178506606
Short name T268
Test name
Test status
Simulation time 332138668348 ps
CPU time 756.2 seconds
Started Jun 02 02:46:51 PM PDT 24
Finished Jun 02 02:59:28 PM PDT 24
Peak memory 201780 kb
Host smart-88b81b6e-f481-4f65-b388-bf22523ea727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178506606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.4178506606
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.1263596413
Short name T738
Test name
Test status
Simulation time 326947994685 ps
CPU time 191.31 seconds
Started Jun 02 02:46:50 PM PDT 24
Finished Jun 02 02:50:02 PM PDT 24
Peak memory 201792 kb
Host smart-9425f618-4d45-44d2-9787-efebd65c8173
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263596413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.1263596413
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.3261618435
Short name T524
Test name
Test status
Simulation time 161000382317 ps
CPU time 123.9 seconds
Started Jun 02 02:46:49 PM PDT 24
Finished Jun 02 02:48:54 PM PDT 24
Peak memory 201856 kb
Host smart-d8a20558-4ed1-48d9-9d77-4e35781e0fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261618435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.3261618435
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.1342109743
Short name T589
Test name
Test status
Simulation time 484875206467 ps
CPU time 677.44 seconds
Started Jun 02 02:46:51 PM PDT 24
Finished Jun 02 02:58:10 PM PDT 24
Peak memory 201728 kb
Host smart-e5bede6d-2ec2-40f1-8147-7fa6c19ffb06
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342109743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.1342109743
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.2804967945
Short name T800
Test name
Test status
Simulation time 610097108539 ps
CPU time 300.1 seconds
Started Jun 02 02:46:56 PM PDT 24
Finished Jun 02 02:51:57 PM PDT 24
Peak memory 201864 kb
Host smart-1ce4bd5c-b3a9-4e6a-a4c0-329277fcd708
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804967945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.2804967945
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.709413922
Short name T339
Test name
Test status
Simulation time 93015982222 ps
CPU time 363.77 seconds
Started Jun 02 02:46:58 PM PDT 24
Finished Jun 02 02:53:02 PM PDT 24
Peak memory 202140 kb
Host smart-dab1acfd-220a-49c1-959c-b7e780cebf71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709413922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.709413922
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.1577635697
Short name T350
Test name
Test status
Simulation time 39032015372 ps
CPU time 20.86 seconds
Started Jun 02 02:46:56 PM PDT 24
Finished Jun 02 02:47:17 PM PDT 24
Peak memory 201584 kb
Host smart-1ed1f489-12b7-499d-8dda-3fbe7faea02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577635697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.1577635697
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.2053352312
Short name T381
Test name
Test status
Simulation time 5008467675 ps
CPU time 13.11 seconds
Started Jun 02 02:46:56 PM PDT 24
Finished Jun 02 02:47:10 PM PDT 24
Peak memory 201532 kb
Host smart-3b029b44-a344-421c-970a-da1e85cbed21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053352312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.2053352312
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.1130616358
Short name T158
Test name
Test status
Simulation time 6095525404 ps
CPU time 7.59 seconds
Started Jun 02 02:46:55 PM PDT 24
Finished Jun 02 02:47:03 PM PDT 24
Peak memory 201588 kb
Host smart-5425c839-be07-45cc-b456-5557b4d5a29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130616358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.1130616358
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.3498655055
Short name T139
Test name
Test status
Simulation time 205777093035 ps
CPU time 58.9 seconds
Started Jun 02 02:46:55 PM PDT 24
Finished Jun 02 02:47:55 PM PDT 24
Peak memory 201784 kb
Host smart-a9aeb620-f3af-4608-969e-b89046dcd9b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498655055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.3498655055
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.1453727476
Short name T567
Test name
Test status
Simulation time 104304586103 ps
CPU time 180.83 seconds
Started Jun 02 02:46:54 PM PDT 24
Finished Jun 02 02:49:56 PM PDT 24
Peak memory 210376 kb
Host smart-4ff2a9d5-5796-4ad7-b014-aad48b3ae7fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453727476 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.1453727476
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.2788828019
Short name T64
Test name
Test status
Simulation time 318524151 ps
CPU time 1.43 seconds
Started Jun 02 02:45:49 PM PDT 24
Finished Jun 02 02:45:56 PM PDT 24
Peak memory 201472 kb
Host smart-4cb7aa50-076b-4ba3-a848-c70bca1b7600
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788828019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.2788828019
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.3403380419
Short name T793
Test name
Test status
Simulation time 163457460032 ps
CPU time 63.25 seconds
Started Jun 02 02:45:23 PM PDT 24
Finished Jun 02 02:46:27 PM PDT 24
Peak memory 201628 kb
Host smart-82dcf262-4d6f-4211-be3d-1ad27528260c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403380419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.3403380419
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.1790535252
Short name T128
Test name
Test status
Simulation time 336228281199 ps
CPU time 391.64 seconds
Started Jun 02 02:45:35 PM PDT 24
Finished Jun 02 02:52:07 PM PDT 24
Peak memory 201756 kb
Host smart-ba37b6da-e1c4-42f4-a3a4-2fe18c3c539c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790535252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.1790535252
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.381260968
Short name T130
Test name
Test status
Simulation time 491689558020 ps
CPU time 315.23 seconds
Started Jun 02 02:45:45 PM PDT 24
Finished Jun 02 02:51:01 PM PDT 24
Peak memory 201760 kb
Host smart-841d4215-450f-4b65-b622-4d198327a881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381260968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.381260968
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.1468908981
Short name T355
Test name
Test status
Simulation time 493227121757 ps
CPU time 247.06 seconds
Started Jun 02 02:45:14 PM PDT 24
Finished Jun 02 02:49:24 PM PDT 24
Peak memory 202012 kb
Host smart-33f3d7ca-63c5-4950-aa7a-2684f3527a4e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468908981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.1468908981
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.145838365
Short name T100
Test name
Test status
Simulation time 340604036030 ps
CPU time 190.05 seconds
Started Jun 02 02:45:16 PM PDT 24
Finished Jun 02 02:48:28 PM PDT 24
Peak memory 201848 kb
Host smart-459429d4-8c1e-486f-b911-e472e8bff71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145838365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.145838365
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.2355795199
Short name T78
Test name
Test status
Simulation time 329044159691 ps
CPU time 119.03 seconds
Started Jun 02 02:45:31 PM PDT 24
Finished Jun 02 02:47:31 PM PDT 24
Peak memory 201756 kb
Host smart-591a27ed-a2c3-4727-8ec4-a4e65ca15e4e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355795199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.2355795199
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.1897071946
Short name T36
Test name
Test status
Simulation time 518961729913 ps
CPU time 242.77 seconds
Started Jun 02 02:45:37 PM PDT 24
Finished Jun 02 02:49:40 PM PDT 24
Peak memory 201848 kb
Host smart-1a1d6bcd-d094-4b13-87e2-081218b5a216
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897071946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.1897071946
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.903243901
Short name T781
Test name
Test status
Simulation time 213500074026 ps
CPU time 246.52 seconds
Started Jun 02 02:45:49 PM PDT 24
Finished Jun 02 02:49:56 PM PDT 24
Peak memory 201700 kb
Host smart-09bb398a-14bb-4d8a-8ec9-a4870a684d2f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903243901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.a
dc_ctrl_filters_wakeup_fixed.903243901
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.2443686722
Short name T622
Test name
Test status
Simulation time 86279727765 ps
CPU time 444.97 seconds
Started Jun 02 02:45:15 PM PDT 24
Finished Jun 02 02:52:43 PM PDT 24
Peak memory 202180 kb
Host smart-9e26636b-a61c-4a4e-ab58-4454334a338d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443686722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.2443686722
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.4088085810
Short name T732
Test name
Test status
Simulation time 31111064580 ps
CPU time 67.88 seconds
Started Jun 02 02:45:27 PM PDT 24
Finished Jun 02 02:46:36 PM PDT 24
Peak memory 201580 kb
Host smart-8a129d13-c2a5-4eda-a48a-37261e482503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088085810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.4088085810
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.2669519761
Short name T371
Test name
Test status
Simulation time 5361983516 ps
CPU time 15.18 seconds
Started Jun 02 02:45:47 PM PDT 24
Finished Jun 02 02:46:03 PM PDT 24
Peak memory 201572 kb
Host smart-f234e983-05e6-4f38-8c51-868d74654df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669519761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.2669519761
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.3656292448
Short name T74
Test name
Test status
Simulation time 8394051252 ps
CPU time 11.2 seconds
Started Jun 02 02:45:26 PM PDT 24
Finished Jun 02 02:45:38 PM PDT 24
Peak memory 218452 kb
Host smart-eb5aa7a7-3125-4106-bd27-52dc17f9cab2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656292448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.3656292448
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.3602642187
Short name T550
Test name
Test status
Simulation time 5875934665 ps
CPU time 5.68 seconds
Started Jun 02 02:45:26 PM PDT 24
Finished Jun 02 02:45:33 PM PDT 24
Peak memory 201608 kb
Host smart-e52b288e-3d37-4f24-8b83-f846182d7a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602642187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.3602642187
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.4179185635
Short name T754
Test name
Test status
Simulation time 306080494166 ps
CPU time 68.82 seconds
Started Jun 02 02:45:31 PM PDT 24
Finished Jun 02 02:46:40 PM PDT 24
Peak memory 201868 kb
Host smart-30e84499-8092-4bdc-89a5-d72e7849d912
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179185635 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.4179185635
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.27092294
Short name T652
Test name
Test status
Simulation time 323576046 ps
CPU time 0.8 seconds
Started Jun 02 02:47:02 PM PDT 24
Finished Jun 02 02:47:04 PM PDT 24
Peak memory 201400 kb
Host smart-63140a11-5579-4325-a025-9064f177e64b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27092294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.27092294
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.221580880
Short name T744
Test name
Test status
Simulation time 522672514069 ps
CPU time 1172.8 seconds
Started Jun 02 02:47:01 PM PDT 24
Finished Jun 02 03:06:35 PM PDT 24
Peak memory 201860 kb
Host smart-b5140e50-09e7-4d2d-a02d-ccbb138c8900
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221580880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gati
ng.221580880
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.1397702206
Short name T676
Test name
Test status
Simulation time 520526735043 ps
CPU time 272.06 seconds
Started Jun 02 02:47:03 PM PDT 24
Finished Jun 02 02:51:36 PM PDT 24
Peak memory 201840 kb
Host smart-07f1f05b-c83c-49f4-ac60-2c9c3bafa663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397702206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.1397702206
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.3934112513
Short name T787
Test name
Test status
Simulation time 159672640547 ps
CPU time 200.54 seconds
Started Jun 02 02:46:56 PM PDT 24
Finished Jun 02 02:50:17 PM PDT 24
Peak memory 201856 kb
Host smart-4c5fe468-3d41-4ba7-8a75-e1a64dad0126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934112513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.3934112513
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.1978558078
Short name T559
Test name
Test status
Simulation time 162075586701 ps
CPU time 95.66 seconds
Started Jun 02 02:46:54 PM PDT 24
Finished Jun 02 02:48:30 PM PDT 24
Peak memory 201768 kb
Host smart-7f582a1c-da68-494e-8744-f8a3084a18a2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978558078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.1978558078
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.1360134382
Short name T555
Test name
Test status
Simulation time 172655322906 ps
CPU time 383.21 seconds
Started Jun 02 02:46:57 PM PDT 24
Finished Jun 02 02:53:21 PM PDT 24
Peak memory 201748 kb
Host smart-6e441150-ebd7-45b7-8e36-da2a6539b24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360134382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.1360134382
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.4219486955
Short name T422
Test name
Test status
Simulation time 487025196426 ps
CPU time 298.99 seconds
Started Jun 02 02:46:56 PM PDT 24
Finished Jun 02 02:51:56 PM PDT 24
Peak memory 201656 kb
Host smart-d734f951-b007-4b88-af2e-39278ca61fa1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219486955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.4219486955
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.4060562768
Short name T240
Test name
Test status
Simulation time 536884590130 ps
CPU time 1129.39 seconds
Started Jun 02 02:47:05 PM PDT 24
Finished Jun 02 03:05:55 PM PDT 24
Peak memory 201776 kb
Host smart-a9a6b1a6-5af7-4a4e-b55c-fedfebab1eec
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060562768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.4060562768
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.205463258
Short name T431
Test name
Test status
Simulation time 200226528935 ps
CPU time 434.49 seconds
Started Jun 02 02:47:01 PM PDT 24
Finished Jun 02 02:54:16 PM PDT 24
Peak memory 201796 kb
Host smart-11006ccf-69a3-473c-b7b0-17afe2bee9f5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205463258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
adc_ctrl_filters_wakeup_fixed.205463258
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.1409485697
Short name T43
Test name
Test status
Simulation time 125959556025 ps
CPU time 364.39 seconds
Started Jun 02 02:47:01 PM PDT 24
Finished Jun 02 02:53:06 PM PDT 24
Peak memory 202116 kb
Host smart-15efc951-eec8-4ae9-9a03-b7117b766385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409485697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.1409485697
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.876424402
Short name T753
Test name
Test status
Simulation time 30108257123 ps
CPU time 10.46 seconds
Started Jun 02 02:47:05 PM PDT 24
Finished Jun 02 02:47:16 PM PDT 24
Peak memory 201584 kb
Host smart-6004e6d4-b4e8-4e96-b490-5708736ef0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876424402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.876424402
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.166369946
Short name T719
Test name
Test status
Simulation time 3106714163 ps
CPU time 2.36 seconds
Started Jun 02 02:47:00 PM PDT 24
Finished Jun 02 02:47:03 PM PDT 24
Peak memory 201544 kb
Host smart-d40e93e0-12ee-403b-a6de-dd115bd4988c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166369946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.166369946
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.403574025
Short name T510
Test name
Test status
Simulation time 5677328768 ps
CPU time 13.75 seconds
Started Jun 02 02:46:56 PM PDT 24
Finished Jun 02 02:47:10 PM PDT 24
Peak memory 201632 kb
Host smart-ab34801d-55d5-4022-a234-fda170f72eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403574025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.403574025
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.4117425516
Short name T774
Test name
Test status
Simulation time 27444583388 ps
CPU time 17.91 seconds
Started Jun 02 02:47:00 PM PDT 24
Finished Jun 02 02:47:18 PM PDT 24
Peak memory 201500 kb
Host smart-364f29c0-ddc0-499d-abcc-47d9bf7e83aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117425516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.4117425516
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.1424999184
Short name T84
Test name
Test status
Simulation time 180767636672 ps
CPU time 75.61 seconds
Started Jun 02 02:47:02 PM PDT 24
Finished Jun 02 02:48:18 PM PDT 24
Peak memory 210088 kb
Host smart-2deba7e3-bda7-48c2-b460-7f90e567247f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424999184 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.1424999184
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.1207047272
Short name T173
Test name
Test status
Simulation time 574347657 ps
CPU time 0.83 seconds
Started Jun 02 02:47:08 PM PDT 24
Finished Jun 02 02:47:09 PM PDT 24
Peak memory 201404 kb
Host smart-5b138205-9d23-4695-b542-c5930bdf53eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207047272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.1207047272
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.1721302441
Short name T684
Test name
Test status
Simulation time 420467396318 ps
CPU time 173.23 seconds
Started Jun 02 02:47:05 PM PDT 24
Finished Jun 02 02:49:59 PM PDT 24
Peak memory 201832 kb
Host smart-5e61d059-f92b-4517-9427-db03000ae8a4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721302441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.1721302441
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.3410456649
Short name T307
Test name
Test status
Simulation time 355406751656 ps
CPU time 429.7 seconds
Started Jun 02 02:47:08 PM PDT 24
Finished Jun 02 02:54:18 PM PDT 24
Peak memory 201924 kb
Host smart-10671550-a7cc-4c59-9c47-2f8751200325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410456649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.3410456649
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.1435370
Short name T290
Test name
Test status
Simulation time 496372597266 ps
CPU time 344.81 seconds
Started Jun 02 02:47:03 PM PDT 24
Finished Jun 02 02:52:49 PM PDT 24
Peak memory 201948 kb
Host smart-5ea37e30-76dc-419f-aec2-0d7e73a73e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.1435370
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.784408491
Short name T98
Test name
Test status
Simulation time 498421659568 ps
CPU time 230.33 seconds
Started Jun 02 02:47:03 PM PDT 24
Finished Jun 02 02:50:53 PM PDT 24
Peak memory 201712 kb
Host smart-d3e96461-030e-4cb2-af21-87b65ca2e87c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=784408491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrup
t_fixed.784408491
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.2751190230
Short name T441
Test name
Test status
Simulation time 165913229361 ps
CPU time 377.8 seconds
Started Jun 02 02:47:03 PM PDT 24
Finished Jun 02 02:53:22 PM PDT 24
Peak memory 201768 kb
Host smart-af26fe6c-5a1e-4422-a16d-47d216811b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751190230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.2751190230
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.3911333871
Short name T507
Test name
Test status
Simulation time 329404162054 ps
CPU time 358.35 seconds
Started Jun 02 02:47:04 PM PDT 24
Finished Jun 02 02:53:03 PM PDT 24
Peak memory 201840 kb
Host smart-5d5642d9-130c-4f49-8e0d-db011fa23f22
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911333871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.3911333871
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.2618965805
Short name T363
Test name
Test status
Simulation time 395890674211 ps
CPU time 563.18 seconds
Started Jun 02 02:47:02 PM PDT 24
Finished Jun 02 02:56:26 PM PDT 24
Peak memory 201772 kb
Host smart-fedd77cd-c092-4b6a-b050-402278c560ba
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618965805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.2618965805
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.541092015
Short name T340
Test name
Test status
Simulation time 95677949790 ps
CPU time 322.77 seconds
Started Jun 02 02:47:10 PM PDT 24
Finished Jun 02 02:52:33 PM PDT 24
Peak memory 202176 kb
Host smart-51160e0a-fefc-40e4-8adf-82a05fac3c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541092015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.541092015
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.2932269288
Short name T395
Test name
Test status
Simulation time 32016236074 ps
CPU time 73.4 seconds
Started Jun 02 02:47:06 PM PDT 24
Finished Jun 02 02:48:20 PM PDT 24
Peak memory 201448 kb
Host smart-c06fa127-c528-40e1-a58e-e53bd48d4b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932269288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.2932269288
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.2740681255
Short name T548
Test name
Test status
Simulation time 5260012732 ps
CPU time 2.47 seconds
Started Jun 02 02:47:07 PM PDT 24
Finished Jun 02 02:47:10 PM PDT 24
Peak memory 201556 kb
Host smart-ac03a480-450d-43f8-aed7-573b9441476c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740681255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.2740681255
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.146610909
Short name T359
Test name
Test status
Simulation time 5929264105 ps
CPU time 14.37 seconds
Started Jun 02 02:47:02 PM PDT 24
Finished Jun 02 02:47:16 PM PDT 24
Peak memory 201500 kb
Host smart-00c265ca-7315-45bf-9e69-4944c5238849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146610909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.146610909
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.989631285
Short name T242
Test name
Test status
Simulation time 64265221363 ps
CPU time 234.7 seconds
Started Jun 02 02:47:07 PM PDT 24
Finished Jun 02 02:51:02 PM PDT 24
Peak memory 217956 kb
Host smart-ad9d50d4-390e-4570-8ae2-a71c85c77560
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989631285 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.989631285
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.2743689336
Short name T388
Test name
Test status
Simulation time 419161037 ps
CPU time 1.09 seconds
Started Jun 02 02:47:13 PM PDT 24
Finished Jun 02 02:47:14 PM PDT 24
Peak memory 201412 kb
Host smart-ca4bcc01-11de-4377-a4a9-6cfa49e7ec91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743689336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.2743689336
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.3185994253
Short name T661
Test name
Test status
Simulation time 327363458996 ps
CPU time 82.16 seconds
Started Jun 02 02:47:14 PM PDT 24
Finished Jun 02 02:48:36 PM PDT 24
Peak memory 201792 kb
Host smart-87f58c66-47b1-4960-8185-ee85c9ca2041
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185994253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.3185994253
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.2865919431
Short name T331
Test name
Test status
Simulation time 532329696414 ps
CPU time 1069.11 seconds
Started Jun 02 02:47:15 PM PDT 24
Finished Jun 02 03:05:05 PM PDT 24
Peak memory 201832 kb
Host smart-d97d88ca-0ef4-45d6-9312-943932e2c071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865919431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.2865919431
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.3225852190
Short name T226
Test name
Test status
Simulation time 482909491818 ps
CPU time 567.38 seconds
Started Jun 02 02:47:08 PM PDT 24
Finished Jun 02 02:56:36 PM PDT 24
Peak memory 201844 kb
Host smart-aacaa721-158f-4d84-80f0-a17fe9e3078c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225852190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.3225852190
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.3897089436
Short name T481
Test name
Test status
Simulation time 160301941540 ps
CPU time 386.54 seconds
Started Jun 02 02:47:15 PM PDT 24
Finished Jun 02 02:53:42 PM PDT 24
Peak memory 201748 kb
Host smart-a6330bbe-8a59-4ee4-8784-e5939e04bc2c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897089436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.3897089436
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.3820501442
Short name T314
Test name
Test status
Simulation time 332321096042 ps
CPU time 192.6 seconds
Started Jun 02 02:47:08 PM PDT 24
Finished Jun 02 02:50:21 PM PDT 24
Peak memory 201748 kb
Host smart-b9a84e0c-174e-4e47-9c23-fd6fe843d978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820501442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.3820501442
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.39712436
Short name T782
Test name
Test status
Simulation time 485913331594 ps
CPU time 265.86 seconds
Started Jun 02 02:47:09 PM PDT 24
Finished Jun 02 02:51:35 PM PDT 24
Peak memory 201760 kb
Host smart-f22989a5-a174-4ae9-93c4-e40afe57cb90
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=39712436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fixed
.39712436
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.1152814423
Short name T739
Test name
Test status
Simulation time 581443458669 ps
CPU time 1289.17 seconds
Started Jun 02 02:47:14 PM PDT 24
Finished Jun 02 03:08:43 PM PDT 24
Peak memory 201728 kb
Host smart-c998d218-6863-484d-969a-d0b03c79cca1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152814423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.1152814423
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.4104396980
Short name T755
Test name
Test status
Simulation time 387929039558 ps
CPU time 228.26 seconds
Started Jun 02 02:47:12 PM PDT 24
Finished Jun 02 02:51:00 PM PDT 24
Peak memory 201864 kb
Host smart-dea3f5bd-c03b-4347-a498-b6ad7b2a4089
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104396980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.4104396980
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.1831038123
Short name T39
Test name
Test status
Simulation time 87947145569 ps
CPU time 307.59 seconds
Started Jun 02 02:47:14 PM PDT 24
Finished Jun 02 02:52:22 PM PDT 24
Peak memory 201992 kb
Host smart-1a95346b-9367-42e1-a699-9267eda39b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831038123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.1831038123
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.1811969232
Short name T691
Test name
Test status
Simulation time 44516062790 ps
CPU time 104.63 seconds
Started Jun 02 02:47:14 PM PDT 24
Finished Jun 02 02:48:59 PM PDT 24
Peak memory 201516 kb
Host smart-5f4f46e5-b657-496f-b4aa-b4876e2bc5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811969232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.1811969232
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.3825631613
Short name T472
Test name
Test status
Simulation time 4721506246 ps
CPU time 10.7 seconds
Started Jun 02 02:47:12 PM PDT 24
Finished Jun 02 02:47:23 PM PDT 24
Peak memory 201524 kb
Host smart-814e2e0f-986d-4716-bf69-eedbbb68a397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825631613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.3825631613
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.1306111513
Short name T525
Test name
Test status
Simulation time 5826450683 ps
CPU time 14.33 seconds
Started Jun 02 02:47:08 PM PDT 24
Finished Jun 02 02:47:23 PM PDT 24
Peak memory 201448 kb
Host smart-7b438486-b6d6-4ac8-9d9b-c7827208e594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306111513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.1306111513
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.3531402268
Short name T642
Test name
Test status
Simulation time 314274103464 ps
CPU time 581.3 seconds
Started Jun 02 02:47:13 PM PDT 24
Finished Jun 02 02:56:54 PM PDT 24
Peak memory 202088 kb
Host smart-6edfb3c2-d190-4323-b93c-01405dea9ac8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531402268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.3531402268
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.2026196403
Short name T201
Test name
Test status
Simulation time 76298687131 ps
CPU time 118.87 seconds
Started Jun 02 02:47:12 PM PDT 24
Finished Jun 02 02:49:12 PM PDT 24
Peak memory 210360 kb
Host smart-ee1ae9e8-9812-4d3e-8190-f8562218d1db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026196403 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.2026196403
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.2610187848
Short name T655
Test name
Test status
Simulation time 311417924 ps
CPU time 0.81 seconds
Started Jun 02 02:47:26 PM PDT 24
Finished Jun 02 02:47:28 PM PDT 24
Peak memory 201448 kb
Host smart-9378ce27-0428-4f36-bca7-769d0ed357b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610187848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.2610187848
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.1275153800
Short name T296
Test name
Test status
Simulation time 165961577763 ps
CPU time 104.77 seconds
Started Jun 02 02:47:20 PM PDT 24
Finished Jun 02 02:49:05 PM PDT 24
Peak memory 201776 kb
Host smart-26c28938-990e-4418-a5b9-26a3346c7119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275153800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.1275153800
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.763796420
Short name T125
Test name
Test status
Simulation time 325614475533 ps
CPU time 796.27 seconds
Started Jun 02 02:47:21 PM PDT 24
Finished Jun 02 03:00:37 PM PDT 24
Peak memory 201712 kb
Host smart-a420c6be-b246-4958-b859-74707d25d071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763796420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.763796420
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.1171881187
Short name T540
Test name
Test status
Simulation time 163824517420 ps
CPU time 383.54 seconds
Started Jun 02 02:47:23 PM PDT 24
Finished Jun 02 02:53:47 PM PDT 24
Peak memory 201792 kb
Host smart-debf6f7c-9e64-4bfb-a58a-3f5d2a30659e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171881187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.1171881187
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.2189937290
Short name T695
Test name
Test status
Simulation time 164681358438 ps
CPU time 359.6 seconds
Started Jun 02 02:47:15 PM PDT 24
Finished Jun 02 02:53:15 PM PDT 24
Peak memory 201788 kb
Host smart-6fe78313-9fd6-48da-9ecb-04a84a818b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189937290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.2189937290
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.4023907502
Short name T602
Test name
Test status
Simulation time 162070018027 ps
CPU time 178.67 seconds
Started Jun 02 02:47:12 PM PDT 24
Finished Jun 02 02:50:11 PM PDT 24
Peak memory 201892 kb
Host smart-2ac27f87-a7b1-47be-9768-596272ef9433
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023907502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.4023907502
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.3286083034
Short name T274
Test name
Test status
Simulation time 567590643502 ps
CPU time 392.7 seconds
Started Jun 02 02:47:21 PM PDT 24
Finished Jun 02 02:53:54 PM PDT 24
Peak memory 201772 kb
Host smart-c37bd604-ee7d-490f-aed3-7cf58f82ff80
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286083034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.3286083034
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.3346174349
Short name T410
Test name
Test status
Simulation time 400251914610 ps
CPU time 208.98 seconds
Started Jun 02 02:47:20 PM PDT 24
Finished Jun 02 02:50:49 PM PDT 24
Peak memory 201728 kb
Host smart-bc381588-ce97-4c86-8a0a-5f9524f228fc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346174349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.3346174349
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.1872739557
Short name T508
Test name
Test status
Simulation time 109598311372 ps
CPU time 589.94 seconds
Started Jun 02 02:47:23 PM PDT 24
Finished Jun 02 02:57:13 PM PDT 24
Peak memory 202100 kb
Host smart-a2f8cd2e-8162-4c1e-9952-c07397fdde0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872739557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.1872739557
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.443804153
Short name T345
Test name
Test status
Simulation time 33868516358 ps
CPU time 11.31 seconds
Started Jun 02 02:47:19 PM PDT 24
Finished Jun 02 02:47:30 PM PDT 24
Peak memory 201564 kb
Host smart-1247d073-6b09-4daf-936b-a9d7d3173926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443804153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.443804153
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.3565454421
Short name T611
Test name
Test status
Simulation time 3538134489 ps
CPU time 2.87 seconds
Started Jun 02 02:47:23 PM PDT 24
Finished Jun 02 02:47:27 PM PDT 24
Peak memory 201616 kb
Host smart-42e9f48f-549b-4e3e-b709-9c7cf35d5b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565454421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.3565454421
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.1644724883
Short name T671
Test name
Test status
Simulation time 5675326050 ps
CPU time 14.06 seconds
Started Jun 02 02:47:13 PM PDT 24
Finished Jun 02 02:47:28 PM PDT 24
Peak memory 201572 kb
Host smart-ccac827e-4b8c-482f-8a04-2865cb66700f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644724883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.1644724883
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.1199380452
Short name T635
Test name
Test status
Simulation time 249585693790 ps
CPU time 495.25 seconds
Started Jun 02 02:47:26 PM PDT 24
Finished Jun 02 02:55:42 PM PDT 24
Peak memory 202068 kb
Host smart-fdcfc100-48b0-4f70-bf91-ee99db0d975b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199380452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.1199380452
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.688197209
Short name T578
Test name
Test status
Simulation time 9716917591 ps
CPU time 6.11 seconds
Started Jun 02 02:47:19 PM PDT 24
Finished Jun 02 02:47:26 PM PDT 24
Peak memory 201664 kb
Host smart-6cfc9372-4c7c-467d-8f80-1efd2109a398
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688197209 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.688197209
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.1761035684
Short name T386
Test name
Test status
Simulation time 479149983 ps
CPU time 0.92 seconds
Started Jun 02 02:47:32 PM PDT 24
Finished Jun 02 02:47:33 PM PDT 24
Peak memory 201472 kb
Host smart-eab97234-5c08-4b47-a867-ab0dec8fea37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761035684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.1761035684
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.3746954156
Short name T315
Test name
Test status
Simulation time 162049429700 ps
CPU time 282.18 seconds
Started Jun 02 02:47:25 PM PDT 24
Finished Jun 02 02:52:07 PM PDT 24
Peak memory 201704 kb
Host smart-ecadf65d-f159-4fd1-a92b-8b512e9a9032
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746954156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.3746954156
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.83645380
Short name T792
Test name
Test status
Simulation time 183833101061 ps
CPU time 438.91 seconds
Started Jun 02 02:47:31 PM PDT 24
Finished Jun 02 02:54:50 PM PDT 24
Peak memory 201860 kb
Host smart-659c6e5b-df04-4c8f-a5b2-7ca227d93b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83645380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.83645380
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.1366449691
Short name T252
Test name
Test status
Simulation time 169615057431 ps
CPU time 407.59 seconds
Started Jun 02 02:47:27 PM PDT 24
Finished Jun 02 02:54:15 PM PDT 24
Peak memory 201768 kb
Host smart-49c939aa-9b60-4f2b-a0c5-b6365a5df478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366449691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.1366449691
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.740655697
Short name T364
Test name
Test status
Simulation time 326626953360 ps
CPU time 281.74 seconds
Started Jun 02 02:47:25 PM PDT 24
Finished Jun 02 02:52:08 PM PDT 24
Peak memory 201692 kb
Host smart-540e55ed-dcf3-4ae4-ac8b-4fc74a732e22
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=740655697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrup
t_fixed.740655697
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.499397973
Short name T736
Test name
Test status
Simulation time 159715247628 ps
CPU time 195.94 seconds
Started Jun 02 02:47:25 PM PDT 24
Finished Jun 02 02:50:42 PM PDT 24
Peak memory 201712 kb
Host smart-6dd4ed22-ef06-405d-900e-a6eb1323a055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499397973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.499397973
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.3645856742
Short name T608
Test name
Test status
Simulation time 165850971695 ps
CPU time 185.65 seconds
Started Jun 02 02:47:23 PM PDT 24
Finished Jun 02 02:50:29 PM PDT 24
Peak memory 201856 kb
Host smart-6d596415-2558-44ff-9b25-3cdd03113181
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645856742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.3645856742
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.3471044066
Short name T669
Test name
Test status
Simulation time 181163596240 ps
CPU time 107.47 seconds
Started Jun 02 02:47:26 PM PDT 24
Finished Jun 02 02:49:14 PM PDT 24
Peak memory 201844 kb
Host smart-d3fd9819-3e41-4f3d-9470-b6489488c48d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471044066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.3471044066
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.612042453
Short name T482
Test name
Test status
Simulation time 200390795077 ps
CPU time 62.52 seconds
Started Jun 02 02:47:26 PM PDT 24
Finished Jun 02 02:48:29 PM PDT 24
Peak memory 201844 kb
Host smart-a9d1a0e2-3519-464a-bab1-61ebb7bfe963
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612042453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
adc_ctrl_filters_wakeup_fixed.612042453
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.2283226990
Short name T157
Test name
Test status
Simulation time 71314384655 ps
CPU time 239.23 seconds
Started Jun 02 02:47:32 PM PDT 24
Finished Jun 02 02:51:32 PM PDT 24
Peak memory 202128 kb
Host smart-87edf2b8-4d82-4993-a361-908c21c28c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283226990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.2283226990
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.729208069
Short name T794
Test name
Test status
Simulation time 30026047461 ps
CPU time 71.16 seconds
Started Jun 02 02:47:31 PM PDT 24
Finished Jun 02 02:48:43 PM PDT 24
Peak memory 201576 kb
Host smart-56625020-686f-4d22-96a8-544a2ee0ddf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729208069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.729208069
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.733781456
Short name T668
Test name
Test status
Simulation time 3346367920 ps
CPU time 3.08 seconds
Started Jun 02 02:47:33 PM PDT 24
Finished Jun 02 02:47:36 PM PDT 24
Peak memory 201584 kb
Host smart-640b5a53-76bb-492f-9d3f-4980a0f012ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733781456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.733781456
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.793129716
Short name T366
Test name
Test status
Simulation time 5673511976 ps
CPU time 7.11 seconds
Started Jun 02 02:47:26 PM PDT 24
Finished Jun 02 02:47:33 PM PDT 24
Peak memory 201552 kb
Host smart-699dbdae-4638-45f9-b016-d87dc1224a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793129716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.793129716
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.1194216003
Short name T714
Test name
Test status
Simulation time 28501123229 ps
CPU time 69.12 seconds
Started Jun 02 02:47:31 PM PDT 24
Finished Jun 02 02:48:41 PM PDT 24
Peak memory 210116 kb
Host smart-e3983ab0-f725-4388-8acb-2838a322ddbc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194216003 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.1194216003
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.3514926855
Short name T587
Test name
Test status
Simulation time 534103118 ps
CPU time 0.95 seconds
Started Jun 02 02:47:43 PM PDT 24
Finished Jun 02 02:47:45 PM PDT 24
Peak memory 201500 kb
Host smart-82656c4b-5d14-440c-a4e9-d26dfc4d220a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514926855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.3514926855
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.674616632
Short name T255
Test name
Test status
Simulation time 357708339268 ps
CPU time 371.33 seconds
Started Jun 02 02:47:38 PM PDT 24
Finished Jun 02 02:53:49 PM PDT 24
Peak memory 202076 kb
Host smart-a165c9cf-bd26-4e70-a71e-e01e7cfb0557
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674616632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gati
ng.674616632
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.4115336660
Short name T253
Test name
Test status
Simulation time 535926357540 ps
CPU time 669.24 seconds
Started Jun 02 02:47:39 PM PDT 24
Finished Jun 02 02:58:49 PM PDT 24
Peak memory 201792 kb
Host smart-d6960645-112f-4149-a687-5460761fb1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115336660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.4115336660
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.1392385598
Short name T247
Test name
Test status
Simulation time 494997733803 ps
CPU time 1106.2 seconds
Started Jun 02 02:47:38 PM PDT 24
Finished Jun 02 03:06:05 PM PDT 24
Peak memory 201720 kb
Host smart-eca8b19e-23d6-4651-8d2f-f291e740fa9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392385598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.1392385598
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.1019207490
Short name T99
Test name
Test status
Simulation time 336052340948 ps
CPU time 804.94 seconds
Started Jun 02 02:47:37 PM PDT 24
Finished Jun 02 03:01:03 PM PDT 24
Peak memory 201764 kb
Host smart-98ac1c0c-25e2-485b-920b-133939ba9e74
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019207490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.1019207490
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.1115630736
Short name T575
Test name
Test status
Simulation time 165368381200 ps
CPU time 99.48 seconds
Started Jun 02 02:47:32 PM PDT 24
Finished Jun 02 02:49:12 PM PDT 24
Peak memory 201756 kb
Host smart-d4311288-ae31-4b66-a1d2-89157d94480a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115630736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.1115630736
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.476773003
Short name T772
Test name
Test status
Simulation time 336612007978 ps
CPU time 175.4 seconds
Started Jun 02 02:47:40 PM PDT 24
Finished Jun 02 02:50:36 PM PDT 24
Peak memory 201688 kb
Host smart-f6e36523-61a1-4150-8a6b-3df3125528b5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=476773003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fixe
d.476773003
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.716499900
Short name T8
Test name
Test status
Simulation time 188975342193 ps
CPU time 108.31 seconds
Started Jun 02 02:47:42 PM PDT 24
Finished Jun 02 02:49:31 PM PDT 24
Peak memory 201772 kb
Host smart-eca48034-6af1-434e-a86e-f2beb3e66552
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716499900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_
wakeup.716499900
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.910404941
Short name T91
Test name
Test status
Simulation time 401677773777 ps
CPU time 975.4 seconds
Started Jun 02 02:47:40 PM PDT 24
Finished Jun 02 03:03:55 PM PDT 24
Peak memory 201720 kb
Host smart-523bb3e1-6ed2-4095-964e-3a5966e1d0d8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910404941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
adc_ctrl_filters_wakeup_fixed.910404941
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.3641998372
Short name T197
Test name
Test status
Simulation time 99805898094 ps
CPU time 341.41 seconds
Started Jun 02 02:47:37 PM PDT 24
Finished Jun 02 02:53:19 PM PDT 24
Peak memory 201940 kb
Host smart-f4730d86-fd2b-4be4-b71c-7994ddbc2f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641998372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.3641998372
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.588150688
Short name T696
Test name
Test status
Simulation time 35756857090 ps
CPU time 80.56 seconds
Started Jun 02 02:47:39 PM PDT 24
Finished Jun 02 02:48:59 PM PDT 24
Peak memory 201596 kb
Host smart-283e473a-ce5f-47a3-85d1-0aed69b141ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588150688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.588150688
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.2082934511
Short name T606
Test name
Test status
Simulation time 2847800705 ps
CPU time 3.88 seconds
Started Jun 02 02:47:42 PM PDT 24
Finished Jun 02 02:47:46 PM PDT 24
Peak memory 201588 kb
Host smart-4ca08e49-8ca6-4085-8d52-150f1f69a6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082934511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.2082934511
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.2530571206
Short name T639
Test name
Test status
Simulation time 5570116587 ps
CPU time 13.81 seconds
Started Jun 02 02:47:30 PM PDT 24
Finished Jun 02 02:47:44 PM PDT 24
Peak memory 201600 kb
Host smart-9c84e28c-cbd6-4fa7-8f33-19a7b9e5038d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530571206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.2530571206
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.1202214002
Short name T276
Test name
Test status
Simulation time 217568805280 ps
CPU time 138.53 seconds
Started Jun 02 02:47:38 PM PDT 24
Finished Jun 02 02:49:57 PM PDT 24
Peak memory 201844 kb
Host smart-63596a6a-45a8-434d-b981-d8f73978580d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202214002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.1202214002
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.10773648
Short name T581
Test name
Test status
Simulation time 284428870145 ps
CPU time 461.76 seconds
Started Jun 02 02:47:41 PM PDT 24
Finished Jun 02 02:55:24 PM PDT 24
Peak memory 210448 kb
Host smart-07d74131-ae35-42f5-a0fd-afde1ce4a769
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10773648 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.10773648
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.844242044
Short name T63
Test name
Test status
Simulation time 313224455 ps
CPU time 0.96 seconds
Started Jun 02 02:47:55 PM PDT 24
Finished Jun 02 02:47:56 PM PDT 24
Peak memory 201440 kb
Host smart-aa9cc7fc-cb41-470e-bc42-6150fd061e7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844242044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.844242044
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.1912994793
Short name T769
Test name
Test status
Simulation time 210952017248 ps
CPU time 230.94 seconds
Started Jun 02 02:47:46 PM PDT 24
Finished Jun 02 02:51:38 PM PDT 24
Peak memory 201760 kb
Host smart-22435139-9c51-43fc-968a-7d5d2ca5a4d0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912994793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.1912994793
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.3744391968
Short name T174
Test name
Test status
Simulation time 170078649504 ps
CPU time 393.53 seconds
Started Jun 02 02:47:44 PM PDT 24
Finished Jun 02 02:54:18 PM PDT 24
Peak memory 201764 kb
Host smart-1e77a24b-283d-48f5-b7da-6b93599f230c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744391968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.3744391968
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.1158569294
Short name T617
Test name
Test status
Simulation time 163048564328 ps
CPU time 104.81 seconds
Started Jun 02 02:47:44 PM PDT 24
Finished Jun 02 02:49:30 PM PDT 24
Peak memory 201704 kb
Host smart-2a5b8685-2f94-4945-8c62-bdeade38864d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158569294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.1158569294
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.3513983737
Short name T435
Test name
Test status
Simulation time 331417164782 ps
CPU time 374.74 seconds
Started Jun 02 02:47:45 PM PDT 24
Finished Jun 02 02:54:00 PM PDT 24
Peak memory 201740 kb
Host smart-3d2f43ec-0e37-48ed-8765-60b20ed308cd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513983737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.3513983737
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.3882482162
Short name T306
Test name
Test status
Simulation time 322143841207 ps
CPU time 142.8 seconds
Started Jun 02 02:47:44 PM PDT 24
Finished Jun 02 02:50:07 PM PDT 24
Peak memory 201780 kb
Host smart-dfb21a8c-6f38-4b25-bde4-e89b23e115c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882482162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.3882482162
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.611114401
Short name T14
Test name
Test status
Simulation time 165138931828 ps
CPU time 97.73 seconds
Started Jun 02 02:47:42 PM PDT 24
Finished Jun 02 02:49:21 PM PDT 24
Peak memory 201748 kb
Host smart-d90add95-86a1-4b93-af71-25110ed289eb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=611114401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fixe
d.611114401
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.957279668
Short name T218
Test name
Test status
Simulation time 374088584044 ps
CPU time 925.79 seconds
Started Jun 02 02:47:44 PM PDT 24
Finished Jun 02 03:03:10 PM PDT 24
Peak memory 201732 kb
Host smart-def86052-af2e-448a-bf1e-1a3406a158c1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957279668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_
wakeup.957279668
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.2551294819
Short name T385
Test name
Test status
Simulation time 614076408257 ps
CPU time 1374.14 seconds
Started Jun 02 02:47:46 PM PDT 24
Finished Jun 02 03:10:40 PM PDT 24
Peak memory 201732 kb
Host smart-de781c08-c416-4986-bd9c-93951752c84e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551294819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.2551294819
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.1545758130
Short name T203
Test name
Test status
Simulation time 131854178219 ps
CPU time 589.64 seconds
Started Jun 02 02:47:50 PM PDT 24
Finished Jun 02 02:57:40 PM PDT 24
Peak memory 202172 kb
Host smart-a12d6072-4a0c-47f9-bc8b-8e5a0373dcd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545758130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.1545758130
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.2620559409
Short name T391
Test name
Test status
Simulation time 45672881414 ps
CPU time 59.4 seconds
Started Jun 02 02:47:55 PM PDT 24
Finished Jun 02 02:48:55 PM PDT 24
Peak memory 201540 kb
Host smart-45be472c-53ae-490c-9cf5-56860006411b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620559409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.2620559409
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.193500427
Short name T604
Test name
Test status
Simulation time 2963836146 ps
CPU time 2.23 seconds
Started Jun 02 02:47:56 PM PDT 24
Finished Jun 02 02:47:58 PM PDT 24
Peak memory 201560 kb
Host smart-933d8bf4-ac12-487f-b3da-f6129b8ed1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193500427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.193500427
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.1045569903
Short name T412
Test name
Test status
Simulation time 5972355071 ps
CPU time 4.56 seconds
Started Jun 02 02:47:45 PM PDT 24
Finished Jun 02 02:47:49 PM PDT 24
Peak memory 201592 kb
Host smart-e9ea9d16-3a78-4042-b8ed-879250526dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045569903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.1045569903
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.1902337321
Short name T452
Test name
Test status
Simulation time 384038603 ps
CPU time 0.85 seconds
Started Jun 02 02:48:02 PM PDT 24
Finished Jun 02 02:48:04 PM PDT 24
Peak memory 201572 kb
Host smart-a41fbb26-ea92-4c3e-b211-2b30fa914d4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902337321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.1902337321
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.2650905101
Short name T316
Test name
Test status
Simulation time 440017865782 ps
CPU time 137.18 seconds
Started Jun 02 02:47:57 PM PDT 24
Finished Jun 02 02:50:15 PM PDT 24
Peak memory 201684 kb
Host smart-58a1a3d1-5048-4b14-a3c0-433943fa5dc4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650905101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.2650905101
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.1862221797
Short name T234
Test name
Test status
Simulation time 370116431320 ps
CPU time 893.57 seconds
Started Jun 02 02:47:57 PM PDT 24
Finished Jun 02 03:02:51 PM PDT 24
Peak memory 201716 kb
Host smart-b3594af4-d39e-4401-964f-070cb567f5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862221797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.1862221797
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.4199099264
Short name T666
Test name
Test status
Simulation time 161223735150 ps
CPU time 89.95 seconds
Started Jun 02 02:47:56 PM PDT 24
Finished Jun 02 02:49:26 PM PDT 24
Peak memory 201836 kb
Host smart-3bdab275-d067-40ea-8a14-61918257a90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199099264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.4199099264
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.271742534
Short name T419
Test name
Test status
Simulation time 491210764615 ps
CPU time 314.04 seconds
Started Jun 02 02:47:56 PM PDT 24
Finished Jun 02 02:53:10 PM PDT 24
Peak memory 201756 kb
Host smart-07af656d-f775-4b1d-bd1c-de408fc60d4e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=271742534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrup
t_fixed.271742534
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.3882947497
Short name T485
Test name
Test status
Simulation time 163334429111 ps
CPU time 105.87 seconds
Started Jun 02 02:47:51 PM PDT 24
Finished Jun 02 02:49:37 PM PDT 24
Peak memory 201672 kb
Host smart-aa582ccb-6d4a-4927-922a-93faf571433c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882947497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.3882947497
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.2279281314
Short name T172
Test name
Test status
Simulation time 338244612265 ps
CPU time 226.1 seconds
Started Jun 02 02:47:56 PM PDT 24
Finished Jun 02 02:51:42 PM PDT 24
Peak memory 201720 kb
Host smart-ea238629-3ff0-4c98-bbbb-510021241a44
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279281314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.2279281314
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.2917915698
Short name T317
Test name
Test status
Simulation time 529698113547 ps
CPU time 1201.64 seconds
Started Jun 02 02:47:58 PM PDT 24
Finished Jun 02 03:08:00 PM PDT 24
Peak memory 201820 kb
Host smart-505d1eef-c3ca-4aca-937a-6d2542a2a939
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917915698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.2917915698
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.251399544
Short name T680
Test name
Test status
Simulation time 406567373155 ps
CPU time 960.22 seconds
Started Jun 02 02:47:55 PM PDT 24
Finished Jun 02 03:03:55 PM PDT 24
Peak memory 201712 kb
Host smart-554649ef-392c-4406-a54d-f6ac96a84dc9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251399544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
adc_ctrl_filters_wakeup_fixed.251399544
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.2218304817
Short name T483
Test name
Test status
Simulation time 104202986854 ps
CPU time 446.6 seconds
Started Jun 02 02:48:04 PM PDT 24
Finished Jun 02 02:55:31 PM PDT 24
Peak memory 202140 kb
Host smart-b31581c7-8a15-48b5-a350-5c5845772dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218304817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.2218304817
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.3820492444
Short name T466
Test name
Test status
Simulation time 42618765374 ps
CPU time 102.16 seconds
Started Jun 02 02:47:57 PM PDT 24
Finished Jun 02 02:49:40 PM PDT 24
Peak memory 201620 kb
Host smart-10fe12e0-bd31-400c-8b31-2064c427a672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820492444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.3820492444
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.509515386
Short name T365
Test name
Test status
Simulation time 5192615560 ps
CPU time 3.82 seconds
Started Jun 02 02:47:57 PM PDT 24
Finished Jun 02 02:48:02 PM PDT 24
Peak memory 201572 kb
Host smart-42aa4045-61bc-45a6-afb7-0eb6bd951489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509515386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.509515386
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.3988366017
Short name T461
Test name
Test status
Simulation time 5812264840 ps
CPU time 4.17 seconds
Started Jun 02 02:47:55 PM PDT 24
Finished Jun 02 02:48:00 PM PDT 24
Peak memory 201576 kb
Host smart-7938fb60-bb4d-4787-88ed-86bcff33eff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988366017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.3988366017
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.1872647524
Short name T89
Test name
Test status
Simulation time 9781518901 ps
CPU time 3.88 seconds
Started Jun 02 02:48:02 PM PDT 24
Finished Jun 02 02:48:06 PM PDT 24
Peak memory 201608 kb
Host smart-7e0881d9-c241-4f24-ad54-f616014d772c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872647524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.1872647524
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.552901478
Short name T638
Test name
Test status
Simulation time 305566164 ps
CPU time 1.21 seconds
Started Jun 02 02:48:08 PM PDT 24
Finished Jun 02 02:48:09 PM PDT 24
Peak memory 201396 kb
Host smart-5efb7594-f635-44a8-be84-02348fa58d35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552901478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.552901478
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.659585679
Short name T492
Test name
Test status
Simulation time 172936481766 ps
CPU time 245.12 seconds
Started Jun 02 02:48:09 PM PDT 24
Finished Jun 02 02:52:14 PM PDT 24
Peak memory 201736 kb
Host smart-332be1c4-576c-4c78-aa63-d4a6a9e09a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659585679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.659585679
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.1744818020
Short name T211
Test name
Test status
Simulation time 162973162448 ps
CPU time 206.81 seconds
Started Jun 02 02:48:03 PM PDT 24
Finished Jun 02 02:51:31 PM PDT 24
Peak memory 201844 kb
Host smart-c5d642ab-b0bc-4154-932d-029157bebc34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744818020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.1744818020
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.1984805503
Short name T656
Test name
Test status
Simulation time 324283997072 ps
CPU time 446.79 seconds
Started Jun 02 02:48:02 PM PDT 24
Finished Jun 02 02:55:29 PM PDT 24
Peak memory 201612 kb
Host smart-d3ebb769-3226-4903-902a-3d91f39a0d0b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984805503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.1984805503
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.3805073308
Short name T649
Test name
Test status
Simulation time 163325284517 ps
CPU time 199.72 seconds
Started Jun 02 02:48:02 PM PDT 24
Finished Jun 02 02:51:22 PM PDT 24
Peak memory 201780 kb
Host smart-5803f8ae-23b3-41dc-8a9c-0f5ae40264f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805073308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.3805073308
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.575093297
Short name T468
Test name
Test status
Simulation time 162177297605 ps
CPU time 86.09 seconds
Started Jun 02 02:48:04 PM PDT 24
Finished Jun 02 02:49:30 PM PDT 24
Peak memory 201716 kb
Host smart-31e4e0c3-f89e-4723-bde9-6194e16f394c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=575093297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fixe
d.575093297
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.3036174333
Short name T480
Test name
Test status
Simulation time 217530253990 ps
CPU time 132.28 seconds
Started Jun 02 02:48:03 PM PDT 24
Finished Jun 02 02:50:16 PM PDT 24
Peak memory 201852 kb
Host smart-9640d760-2173-4b24-8bfe-cd633fe6fddf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036174333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.3036174333
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.3899387097
Short name T554
Test name
Test status
Simulation time 581854926235 ps
CPU time 323.24 seconds
Started Jun 02 02:48:02 PM PDT 24
Finished Jun 02 02:53:26 PM PDT 24
Peak memory 201808 kb
Host smart-d6b776ea-32b7-4e19-a409-2c4f64f7f7a3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899387097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.3899387097
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.2749268989
Short name T433
Test name
Test status
Simulation time 102079032545 ps
CPU time 533.48 seconds
Started Jun 02 02:48:07 PM PDT 24
Finished Jun 02 02:57:01 PM PDT 24
Peak memory 202064 kb
Host smart-a223e20c-5ee5-47e0-8713-d7da36b7b9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749268989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.2749268989
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.2116760117
Short name T383
Test name
Test status
Simulation time 27458666833 ps
CPU time 62.22 seconds
Started Jun 02 02:48:08 PM PDT 24
Finished Jun 02 02:49:10 PM PDT 24
Peak memory 201548 kb
Host smart-3490ac23-b72d-4b16-aa11-b23aea58c0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116760117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.2116760117
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.2773130826
Short name T712
Test name
Test status
Simulation time 3217594465 ps
CPU time 2.73 seconds
Started Jun 02 02:48:07 PM PDT 24
Finished Jun 02 02:48:10 PM PDT 24
Peak memory 201600 kb
Host smart-70c576b3-96f7-4b71-ab9a-23d665979d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773130826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.2773130826
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.766921869
Short name T416
Test name
Test status
Simulation time 5995730214 ps
CPU time 15.07 seconds
Started Jun 02 02:48:04 PM PDT 24
Finished Jun 02 02:48:19 PM PDT 24
Peak memory 201632 kb
Host smart-027bc04c-0425-4864-a1f3-acffb7419abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766921869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.766921869
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.337225964
Short name T298
Test name
Test status
Simulation time 390807070684 ps
CPU time 178.32 seconds
Started Jun 02 02:48:07 PM PDT 24
Finished Jun 02 02:51:06 PM PDT 24
Peak memory 201752 kb
Host smart-1f9cfad7-e64e-4ee5-8bfb-43233d5177a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337225964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all.
337225964
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.3107876039
Short name T556
Test name
Test status
Simulation time 100629509184 ps
CPU time 58.75 seconds
Started Jun 02 02:48:07 PM PDT 24
Finished Jun 02 02:49:06 PM PDT 24
Peak memory 201884 kb
Host smart-8bb8ccdd-77e1-44c9-a167-0577ad6c052b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107876039 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.3107876039
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.1990221407
Short name T749
Test name
Test status
Simulation time 383129445 ps
CPU time 1.35 seconds
Started Jun 02 02:48:18 PM PDT 24
Finished Jun 02 02:48:20 PM PDT 24
Peak memory 201464 kb
Host smart-682de3e4-a0b6-4d68-8c9c-cfdad2c9eb85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990221407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.1990221407
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.4190022391
Short name T129
Test name
Test status
Simulation time 509820496674 ps
CPU time 305.43 seconds
Started Jun 02 02:48:20 PM PDT 24
Finished Jun 02 02:53:26 PM PDT 24
Peak memory 201500 kb
Host smart-6c7b20a7-d22c-4513-8102-7dcc945e1396
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190022391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.4190022391
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.3086461456
Short name T687
Test name
Test status
Simulation time 164545693768 ps
CPU time 114.04 seconds
Started Jun 02 02:48:19 PM PDT 24
Finished Jun 02 02:50:14 PM PDT 24
Peak memory 201692 kb
Host smart-7bd7bee8-42d4-49eb-9d0a-d53cad4feef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086461456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.3086461456
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.938579333
Short name T182
Test name
Test status
Simulation time 486984589668 ps
CPU time 211.76 seconds
Started Jun 02 02:48:12 PM PDT 24
Finished Jun 02 02:51:44 PM PDT 24
Peak memory 201784 kb
Host smart-13b9a179-977c-4cbc-8107-26ef8b26009c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938579333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.938579333
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.1870322960
Short name T436
Test name
Test status
Simulation time 164396745388 ps
CPU time 250.38 seconds
Started Jun 02 02:48:12 PM PDT 24
Finished Jun 02 02:52:23 PM PDT 24
Peak memory 201712 kb
Host smart-cadb4b05-7051-492e-a53b-14c5f9b82798
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870322960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.1870322960
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.2949955507
Short name T618
Test name
Test status
Simulation time 163346501731 ps
CPU time 358.26 seconds
Started Jun 02 02:48:14 PM PDT 24
Finished Jun 02 02:54:13 PM PDT 24
Peak memory 201816 kb
Host smart-6f81a659-c4c1-41a7-b961-529ce75a7f3d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949955507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.2949955507
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.1638521624
Short name T471
Test name
Test status
Simulation time 175621686995 ps
CPU time 206.25 seconds
Started Jun 02 02:48:13 PM PDT 24
Finished Jun 02 02:51:39 PM PDT 24
Peak memory 201828 kb
Host smart-35614ed0-a624-4d54-99bf-5987b73d7085
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638521624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.1638521624
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.1777928281
Short name T418
Test name
Test status
Simulation time 403759379880 ps
CPU time 881.39 seconds
Started Jun 02 02:48:23 PM PDT 24
Finished Jun 02 03:03:05 PM PDT 24
Peak memory 201724 kb
Host smart-33b359f7-d6e3-4cdd-8850-b30e96c65b93
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777928281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.1777928281
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.1686111347
Short name T208
Test name
Test status
Simulation time 110083691898 ps
CPU time 362.75 seconds
Started Jun 02 02:48:17 PM PDT 24
Finished Jun 02 02:54:21 PM PDT 24
Peak memory 202084 kb
Host smart-0a116ebf-b197-4307-a435-807783f893ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686111347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.1686111347
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.4059695654
Short name T101
Test name
Test status
Simulation time 33214692130 ps
CPU time 70.72 seconds
Started Jun 02 02:48:19 PM PDT 24
Finished Jun 02 02:49:30 PM PDT 24
Peak memory 201596 kb
Host smart-4c080464-58b5-416f-b856-07b3ff4de495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059695654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.4059695654
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.4243305883
Short name T423
Test name
Test status
Simulation time 4997723727 ps
CPU time 3.34 seconds
Started Jun 02 02:48:19 PM PDT 24
Finished Jun 02 02:48:23 PM PDT 24
Peak memory 201512 kb
Host smart-5e3e2356-6882-43d4-8e66-e886b85a45e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243305883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.4243305883
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.2494265552
Short name T626
Test name
Test status
Simulation time 5857495534 ps
CPU time 7.2 seconds
Started Jun 02 02:48:10 PM PDT 24
Finished Jun 02 02:48:17 PM PDT 24
Peak memory 201568 kb
Host smart-4952d741-0df8-4158-8032-9fa9bc769f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494265552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.2494265552
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.2819856542
Short name T514
Test name
Test status
Simulation time 217653081108 ps
CPU time 220.46 seconds
Started Jun 02 02:48:19 PM PDT 24
Finished Jun 02 02:52:00 PM PDT 24
Peak memory 201740 kb
Host smart-00011cfc-9a76-4496-a5d9-42f1ef05f25d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819856542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.2819856542
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.3294004123
Short name T20
Test name
Test status
Simulation time 83811852851 ps
CPU time 134.78 seconds
Started Jun 02 02:48:20 PM PDT 24
Finished Jun 02 02:50:36 PM PDT 24
Peak memory 217672 kb
Host smart-07cd7439-0c42-4100-beff-46f9d9741237
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294004123 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.3294004123
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.2072493737
Short name T518
Test name
Test status
Simulation time 436818800 ps
CPU time 1.16 seconds
Started Jun 02 02:45:36 PM PDT 24
Finished Jun 02 02:45:38 PM PDT 24
Peak memory 201440 kb
Host smart-956ce1b3-9e38-4a79-9c9e-cc136a7662f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072493737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.2072493737
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.3337596714
Short name T300
Test name
Test status
Simulation time 508996257942 ps
CPU time 321.48 seconds
Started Jun 02 02:45:42 PM PDT 24
Finished Jun 02 02:51:04 PM PDT 24
Peak memory 201876 kb
Host smart-0b072401-4d26-4832-be57-d21cc1201a7a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337596714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.3337596714
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.2313447741
Short name T168
Test name
Test status
Simulation time 352208372501 ps
CPU time 191.76 seconds
Started Jun 02 02:45:46 PM PDT 24
Finished Jun 02 02:48:59 PM PDT 24
Peak memory 201716 kb
Host smart-c5e0d244-d512-4dc2-b6b5-46d799e99c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313447741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.2313447741
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.3980725339
Short name T151
Test name
Test status
Simulation time 331393458024 ps
CPU time 388.76 seconds
Started Jun 02 02:45:26 PM PDT 24
Finished Jun 02 02:51:56 PM PDT 24
Peak memory 201852 kb
Host smart-6b507356-73bc-4211-96e9-6bea6d33bd10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980725339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.3980725339
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.2727369649
Short name T675
Test name
Test status
Simulation time 335117161643 ps
CPU time 415.81 seconds
Started Jun 02 02:45:18 PM PDT 24
Finished Jun 02 02:52:15 PM PDT 24
Peak memory 201740 kb
Host smart-fbe51bce-8a3f-4aa3-a73c-b6d938293cc8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727369649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.2727369649
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.2966445809
Short name T531
Test name
Test status
Simulation time 329250116593 ps
CPU time 123.08 seconds
Started Jun 02 02:45:58 PM PDT 24
Finished Jun 02 02:48:02 PM PDT 24
Peak memory 201820 kb
Host smart-5b012a40-04b2-43c3-b88d-897d6e0de149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966445809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.2966445809
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.2891148750
Short name T693
Test name
Test status
Simulation time 498382829126 ps
CPU time 550.01 seconds
Started Jun 02 02:46:01 PM PDT 24
Finished Jun 02 02:55:11 PM PDT 24
Peak memory 201776 kb
Host smart-8650ea89-e31e-4f4b-987c-3de026df9568
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891148750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.2891148750
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.2030755487
Short name T308
Test name
Test status
Simulation time 583806961587 ps
CPU time 342.54 seconds
Started Jun 02 02:45:29 PM PDT 24
Finished Jun 02 02:51:12 PM PDT 24
Peak memory 201872 kb
Host smart-1aafb8c0-8d5a-4cdd-9ac2-efef7ef0128f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030755487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.2030755487
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.1773323303
Short name T6
Test name
Test status
Simulation time 395462042573 ps
CPU time 238.85 seconds
Started Jun 02 02:45:43 PM PDT 24
Finished Jun 02 02:49:43 PM PDT 24
Peak memory 201728 kb
Host smart-c934f607-92ba-4650-93f2-1cbf0a2505fa
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773323303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.1773323303
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.4270682426
Short name T38
Test name
Test status
Simulation time 113554954974 ps
CPU time 612.16 seconds
Started Jun 02 02:45:19 PM PDT 24
Finished Jun 02 02:55:33 PM PDT 24
Peak memory 202024 kb
Host smart-0aff6b07-d781-479d-b573-fa22df52a37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270682426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.4270682426
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.2746760010
Short name T582
Test name
Test status
Simulation time 34110980388 ps
CPU time 37.77 seconds
Started Jun 02 02:45:47 PM PDT 24
Finished Jun 02 02:46:25 PM PDT 24
Peak memory 201472 kb
Host smart-c22e45d9-0d03-47ec-818a-00dddddfef32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746760010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.2746760010
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.1242383270
Short name T102
Test name
Test status
Simulation time 4607356959 ps
CPU time 3.53 seconds
Started Jun 02 02:45:17 PM PDT 24
Finished Jun 02 02:45:22 PM PDT 24
Peak memory 201848 kb
Host smart-d6976d43-befd-4f4e-aa5e-acd933ede430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242383270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.1242383270
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.2953081310
Short name T81
Test name
Test status
Simulation time 5681486207 ps
CPU time 2.78 seconds
Started Jun 02 02:45:20 PM PDT 24
Finished Jun 02 02:45:23 PM PDT 24
Peak memory 201448 kb
Host smart-42b39987-612b-441b-b2a5-f9b47dda3652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953081310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.2953081310
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.3160234704
Short name T679
Test name
Test status
Simulation time 335901513867 ps
CPU time 1097.39 seconds
Started Jun 02 02:45:22 PM PDT 24
Finished Jun 02 03:03:40 PM PDT 24
Peak memory 202092 kb
Host smart-55fb37d0-0bda-4fa9-814a-9aa6851d9f49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160234704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
3160234704
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.120295900
Short name T750
Test name
Test status
Simulation time 437898132 ps
CPU time 1.66 seconds
Started Jun 02 02:45:35 PM PDT 24
Finished Jun 02 02:45:37 PM PDT 24
Peak memory 201480 kb
Host smart-fb5f97d8-22ab-4ab1-8cd1-050d2a5a3e5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120295900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.120295900
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.3147252976
Short name T770
Test name
Test status
Simulation time 560354660536 ps
CPU time 267.74 seconds
Started Jun 02 02:45:45 PM PDT 24
Finished Jun 02 02:50:14 PM PDT 24
Peak memory 201844 kb
Host smart-b47305c5-f1db-42d6-9435-3143124713a5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147252976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.3147252976
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.1161743737
Short name T325
Test name
Test status
Simulation time 342549749860 ps
CPU time 413.66 seconds
Started Jun 02 02:45:19 PM PDT 24
Finished Jun 02 02:52:14 PM PDT 24
Peak memory 201740 kb
Host smart-0113beba-b84b-464b-a314-5facf7dac5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161743737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.1161743737
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.33961033
Short name T156
Test name
Test status
Simulation time 162196106903 ps
CPU time 356.23 seconds
Started Jun 02 02:45:48 PM PDT 24
Finished Jun 02 02:51:45 PM PDT 24
Peak memory 201616 kb
Host smart-19bc7fb1-3f96-44ef-ab32-7f9c96344c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33961033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.33961033
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.3184721701
Short name T625
Test name
Test status
Simulation time 162260498756 ps
CPU time 387.51 seconds
Started Jun 02 02:45:30 PM PDT 24
Finished Jun 02 02:51:58 PM PDT 24
Peak memory 201704 kb
Host smart-db627440-50d6-4ba7-9cbd-2645e35ca18a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184721701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.3184721701
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.2042602017
Short name T295
Test name
Test status
Simulation time 496865453639 ps
CPU time 1048.78 seconds
Started Jun 02 02:45:42 PM PDT 24
Finished Jun 02 03:03:12 PM PDT 24
Peak memory 201824 kb
Host smart-123af43a-7016-43d7-9cf3-a22a86c2c2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042602017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.2042602017
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.2160400993
Short name T434
Test name
Test status
Simulation time 332745609232 ps
CPU time 240.78 seconds
Started Jun 02 02:45:38 PM PDT 24
Finished Jun 02 02:49:39 PM PDT 24
Peak memory 201908 kb
Host smart-62d74639-4bd2-4540-8309-354cf6c493d4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160400993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.2160400993
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.1084943889
Short name T560
Test name
Test status
Simulation time 329131729588 ps
CPU time 745.81 seconds
Started Jun 02 02:45:40 PM PDT 24
Finished Jun 02 02:58:06 PM PDT 24
Peak memory 201992 kb
Host smart-517bcb8a-d59d-411f-9abb-b38667ec228e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084943889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.1084943889
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.709746894
Short name T645
Test name
Test status
Simulation time 201549416322 ps
CPU time 48.73 seconds
Started Jun 02 02:45:27 PM PDT 24
Finished Jun 02 02:46:16 PM PDT 24
Peak memory 201744 kb
Host smart-85847174-9c5a-4dea-b515-acba34c5ce5a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709746894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.a
dc_ctrl_filters_wakeup_fixed.709746894
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.167926250
Short name T209
Test name
Test status
Simulation time 90322100243 ps
CPU time 326.61 seconds
Started Jun 02 02:45:50 PM PDT 24
Finished Jun 02 02:51:17 PM PDT 24
Peak memory 202120 kb
Host smart-07aa66a0-14f0-4f36-8bca-fdffde4d183d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167926250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.167926250
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.1554562663
Short name T467
Test name
Test status
Simulation time 42800860724 ps
CPU time 27.55 seconds
Started Jun 02 02:45:55 PM PDT 24
Finished Jun 02 02:46:23 PM PDT 24
Peak memory 201608 kb
Host smart-ef85e664-cc78-4cd6-be23-f9809f78f65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554562663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.1554562663
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.2638000378
Short name T528
Test name
Test status
Simulation time 4048149655 ps
CPU time 5.27 seconds
Started Jun 02 02:45:38 PM PDT 24
Finished Jun 02 02:45:43 PM PDT 24
Peak memory 201604 kb
Host smart-0d03a9cd-4bb0-4723-a223-ae984ad72ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638000378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.2638000378
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.2359202429
Short name T784
Test name
Test status
Simulation time 5777997293 ps
CPU time 13.88 seconds
Started Jun 02 02:45:26 PM PDT 24
Finished Jun 02 02:45:41 PM PDT 24
Peak memory 201624 kb
Host smart-c65fe6f4-aa51-48bd-aae4-4a26e45273db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359202429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.2359202429
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.3481374345
Short name T313
Test name
Test status
Simulation time 580960141564 ps
CPU time 908.09 seconds
Started Jun 02 02:45:43 PM PDT 24
Finished Jun 02 03:00:52 PM PDT 24
Peak memory 210368 kb
Host smart-bbe7e1dd-80d4-40c1-98a9-272fb046fb37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481374345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
3481374345
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.985619365
Short name T19
Test name
Test status
Simulation time 77019759378 ps
CPU time 33.99 seconds
Started Jun 02 02:45:51 PM PDT 24
Finished Jun 02 02:46:25 PM PDT 24
Peak memory 210176 kb
Host smart-b90b5804-1324-4ef5-b601-1f5a3242e0b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985619365 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.985619365
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.1457731585
Short name T709
Test name
Test status
Simulation time 498468968 ps
CPU time 1.36 seconds
Started Jun 02 02:45:44 PM PDT 24
Finished Jun 02 02:45:46 PM PDT 24
Peak memory 201468 kb
Host smart-d6b8f06c-3096-4d6f-b0cb-dccb409c4112
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457731585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.1457731585
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.772931921
Short name T221
Test name
Test status
Simulation time 324201778521 ps
CPU time 323.91 seconds
Started Jun 02 02:45:38 PM PDT 24
Finished Jun 02 02:51:03 PM PDT 24
Peak memory 201764 kb
Host smart-dc8e147d-b69a-4813-b8b4-86859b03d4ff
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772931921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gatin
g.772931921
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.2276819150
Short name T305
Test name
Test status
Simulation time 348738515094 ps
CPU time 399.36 seconds
Started Jun 02 02:45:45 PM PDT 24
Finished Jun 02 02:52:25 PM PDT 24
Peak memory 201716 kb
Host smart-70ad2dde-1e24-4c73-8f70-82f6a7e1c63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276819150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.2276819150
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.168091656
Short name T230
Test name
Test status
Simulation time 166857637191 ps
CPU time 201.81 seconds
Started Jun 02 02:45:29 PM PDT 24
Finished Jun 02 02:48:52 PM PDT 24
Peak memory 201736 kb
Host smart-4089b525-20bc-4a0b-9278-0bf65319b932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168091656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.168091656
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.4241526177
Short name T90
Test name
Test status
Simulation time 335122834254 ps
CPU time 755.07 seconds
Started Jun 02 02:45:51 PM PDT 24
Finished Jun 02 02:58:27 PM PDT 24
Peak memory 201920 kb
Host smart-aec4de00-cb77-4af2-91c3-bcc2beff2bbe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241526177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.4241526177
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.2991124673
Short name T478
Test name
Test status
Simulation time 166460816288 ps
CPU time 265.13 seconds
Started Jun 02 02:45:30 PM PDT 24
Finished Jun 02 02:49:55 PM PDT 24
Peak memory 201760 kb
Host smart-2baadc13-c816-46dd-8045-f1edec781217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991124673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.2991124673
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.3628877357
Short name T344
Test name
Test status
Simulation time 327843387680 ps
CPU time 724.67 seconds
Started Jun 02 02:45:46 PM PDT 24
Finished Jun 02 02:57:51 PM PDT 24
Peak memory 201788 kb
Host smart-b627583a-1441-4e45-b7a7-90b5375dde65
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628877357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.3628877357
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.647816702
Short name T573
Test name
Test status
Simulation time 221422358737 ps
CPU time 264.19 seconds
Started Jun 02 02:45:36 PM PDT 24
Finished Jun 02 02:50:01 PM PDT 24
Peak memory 201776 kb
Host smart-04de8779-d088-4a0e-b715-5046170824cd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647816702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_w
akeup.647816702
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.1881671865
Short name T799
Test name
Test status
Simulation time 615491585684 ps
CPU time 1336.91 seconds
Started Jun 02 02:45:33 PM PDT 24
Finished Jun 02 03:07:50 PM PDT 24
Peak memory 201800 kb
Host smart-dab724e6-cf60-48a4-a584-7e14735f8ba1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881671865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.1881671865
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.624639052
Short name T41
Test name
Test status
Simulation time 91904273368 ps
CPU time 492.76 seconds
Started Jun 02 02:45:46 PM PDT 24
Finished Jun 02 02:54:00 PM PDT 24
Peak memory 202160 kb
Host smart-f2332757-6b95-447e-8bde-83466920a18c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624639052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.624639052
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.709555497
Short name T565
Test name
Test status
Simulation time 36574260398 ps
CPU time 87.87 seconds
Started Jun 02 02:45:30 PM PDT 24
Finished Jun 02 02:46:58 PM PDT 24
Peak memory 201592 kb
Host smart-3b59bc66-ab65-469a-95da-c9dc96b9810f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709555497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.709555497
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.593292214
Short name T584
Test name
Test status
Simulation time 4399236154 ps
CPU time 3.42 seconds
Started Jun 02 02:45:41 PM PDT 24
Finished Jun 02 02:45:44 PM PDT 24
Peak memory 201568 kb
Host smart-9bd63f8d-72de-4612-b3f5-c9a1b933e9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593292214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.593292214
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.2660083832
Short name T488
Test name
Test status
Simulation time 5629255080 ps
CPU time 4.27 seconds
Started Jun 02 02:45:39 PM PDT 24
Finished Jun 02 02:45:44 PM PDT 24
Peak memory 201568 kb
Host smart-2fdfafef-15d1-4c8e-a676-802927fdf9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660083832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.2660083832
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.1619628954
Short name T615
Test name
Test status
Simulation time 400110451021 ps
CPU time 234.63 seconds
Started Jun 02 02:45:38 PM PDT 24
Finished Jun 02 02:49:34 PM PDT 24
Peak memory 210472 kb
Host smart-eb5bde5a-63e0-4ffc-a229-80986f860727
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619628954 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.1619628954
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.3466067906
Short name T486
Test name
Test status
Simulation time 474410719 ps
CPU time 0.72 seconds
Started Jun 02 02:45:42 PM PDT 24
Finished Jun 02 02:45:43 PM PDT 24
Peak memory 201396 kb
Host smart-630f502f-1bbe-4c5b-aa76-c267a3057ca3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466067906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.3466067906
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.1998852376
Short name T185
Test name
Test status
Simulation time 518894945955 ps
CPU time 248.02 seconds
Started Jun 02 02:45:41 PM PDT 24
Finished Jun 02 02:49:50 PM PDT 24
Peak memory 201704 kb
Host smart-1b2631d5-be20-4e71-899c-5951867a6299
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998852376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.1998852376
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.1574569436
Short name T580
Test name
Test status
Simulation time 188302239430 ps
CPU time 431.83 seconds
Started Jun 02 02:45:35 PM PDT 24
Finished Jun 02 02:52:48 PM PDT 24
Peak memory 201676 kb
Host smart-fa9ec9bc-4eb9-4c94-ac54-47c9dde3d6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574569436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.1574569436
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.2609118281
Short name T304
Test name
Test status
Simulation time 486426734874 ps
CPU time 309.5 seconds
Started Jun 02 02:45:42 PM PDT 24
Finished Jun 02 02:50:52 PM PDT 24
Peak memory 201772 kb
Host smart-d2433fff-cd75-4b90-a733-094bc0c872be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609118281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.2609118281
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.27783883
Short name T579
Test name
Test status
Simulation time 332913113762 ps
CPU time 111.12 seconds
Started Jun 02 02:45:45 PM PDT 24
Finished Jun 02 02:47:42 PM PDT 24
Peak memory 201628 kb
Host smart-e28e9182-01f6-4b08-9674-d2faaccc5fc2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=27783883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt_
fixed.27783883
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.4262101016
Short name T663
Test name
Test status
Simulation time 168930610698 ps
CPU time 390.22 seconds
Started Jun 02 02:45:58 PM PDT 24
Finished Jun 02 02:52:28 PM PDT 24
Peak memory 201824 kb
Host smart-ea4cef20-3406-4d35-8df4-070f034f6f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262101016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.4262101016
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.1349441914
Short name T630
Test name
Test status
Simulation time 495443797411 ps
CPU time 641.84 seconds
Started Jun 02 02:45:48 PM PDT 24
Finished Jun 02 02:56:31 PM PDT 24
Peak memory 201792 kb
Host smart-f7c80bb1-7356-4a83-be53-c2c3649d9624
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349441914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.1349441914
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.514640306
Short name T231
Test name
Test status
Simulation time 370237786622 ps
CPU time 436.3 seconds
Started Jun 02 02:45:47 PM PDT 24
Finished Jun 02 02:53:04 PM PDT 24
Peak memory 201776 kb
Host smart-3d696b41-c696-4ba9-82eb-a70af20b095b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514640306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_w
akeup.514640306
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.3345842425
Short name T35
Test name
Test status
Simulation time 407095044204 ps
CPU time 521.62 seconds
Started Jun 02 02:45:40 PM PDT 24
Finished Jun 02 02:54:22 PM PDT 24
Peak memory 201792 kb
Host smart-5bc53c0c-ceed-415d-99b0-a85a9eb59375
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345842425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.3345842425
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.3865156559
Short name T502
Test name
Test status
Simulation time 79340485431 ps
CPU time 344.78 seconds
Started Jun 02 02:45:50 PM PDT 24
Finished Jun 02 02:51:35 PM PDT 24
Peak memory 202036 kb
Host smart-375691f3-e99f-43fe-96b8-a304c0e88f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865156559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.3865156559
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.1533304070
Short name T644
Test name
Test status
Simulation time 43264358896 ps
CPU time 51.12 seconds
Started Jun 02 02:45:45 PM PDT 24
Finished Jun 02 02:46:37 PM PDT 24
Peak memory 201612 kb
Host smart-375c24f5-420e-4e47-8755-86ef95c134c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533304070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.1533304070
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.2106106252
Short name T370
Test name
Test status
Simulation time 3460291112 ps
CPU time 2.59 seconds
Started Jun 02 02:45:42 PM PDT 24
Finished Jun 02 02:45:45 PM PDT 24
Peak memory 201576 kb
Host smart-f6608c46-82b4-44e3-82e9-ac7e4f97e24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106106252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.2106106252
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.4075280532
Short name T426
Test name
Test status
Simulation time 5955441477 ps
CPU time 4.75 seconds
Started Jun 02 02:45:27 PM PDT 24
Finished Jun 02 02:45:36 PM PDT 24
Peak memory 201596 kb
Host smart-d1a63535-c935-4f1a-9697-061e5bbd7733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075280532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.4075280532
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.3717886255
Short name T647
Test name
Test status
Simulation time 54299822529 ps
CPU time 66.11 seconds
Started Jun 02 02:45:50 PM PDT 24
Finished Jun 02 02:46:57 PM PDT 24
Peak memory 201732 kb
Host smart-77be73ab-9a9a-42ef-8d1b-5602d40c570b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717886255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
3717886255
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.3244341511
Short name T654
Test name
Test status
Simulation time 53309020201 ps
CPU time 121.89 seconds
Started Jun 02 02:45:48 PM PDT 24
Finished Jun 02 02:47:50 PM PDT 24
Peak memory 210180 kb
Host smart-304b9000-b0df-4db6-959e-4edd683de90f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244341511 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.3244341511
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.1440380819
Short name T620
Test name
Test status
Simulation time 439478551 ps
CPU time 1.65 seconds
Started Jun 02 02:45:45 PM PDT 24
Finished Jun 02 02:45:47 PM PDT 24
Peak memory 201376 kb
Host smart-cf950d99-4ff5-450e-9a0a-b1768283065b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440380819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.1440380819
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.2755503228
Short name T166
Test name
Test status
Simulation time 323006285133 ps
CPU time 54.65 seconds
Started Jun 02 02:45:37 PM PDT 24
Finished Jun 02 02:46:32 PM PDT 24
Peak memory 201616 kb
Host smart-b4f6bd96-42fb-47e6-9e7d-8b5743e12fa6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755503228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.2755503228
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.2286250588
Short name T797
Test name
Test status
Simulation time 498949154564 ps
CPU time 1161.52 seconds
Started Jun 02 02:45:59 PM PDT 24
Finished Jun 02 03:05:22 PM PDT 24
Peak memory 201740 kb
Host smart-062c15ca-7712-4e32-8811-3ed2bd69038b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286250588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.2286250588
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.2389230977
Short name T440
Test name
Test status
Simulation time 160743903011 ps
CPU time 146.46 seconds
Started Jun 02 02:45:44 PM PDT 24
Finished Jun 02 02:48:12 PM PDT 24
Peak memory 201836 kb
Host smart-9031fa40-1bd5-4a6a-a030-f84343bcaabe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389230977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.2389230977
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.3066181159
Short name T131
Test name
Test status
Simulation time 497654196486 ps
CPU time 192.62 seconds
Started Jun 02 02:45:45 PM PDT 24
Finished Jun 02 02:48:58 PM PDT 24
Peak memory 201752 kb
Host smart-a0a019a6-88a0-42bf-b444-456b616c412d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066181159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.3066181159
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.2926858206
Short name T563
Test name
Test status
Simulation time 315679838470 ps
CPU time 650.26 seconds
Started Jun 02 02:45:53 PM PDT 24
Finished Jun 02 02:56:44 PM PDT 24
Peak memory 201808 kb
Host smart-66434b36-1693-4840-950c-373af1592dcb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926858206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.2926858206
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.603953801
Short name T460
Test name
Test status
Simulation time 403546628480 ps
CPU time 53.42 seconds
Started Jun 02 02:45:47 PM PDT 24
Finished Jun 02 02:46:42 PM PDT 24
Peak memory 201788 kb
Host smart-2d6e7845-dc2a-41da-99b4-a2fcdaf1dfd4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603953801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.a
dc_ctrl_filters_wakeup_fixed.603953801
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.1598572312
Short name T490
Test name
Test status
Simulation time 23962199589 ps
CPU time 26.4 seconds
Started Jun 02 02:45:48 PM PDT 24
Finished Jun 02 02:46:15 PM PDT 24
Peak memory 201588 kb
Host smart-f4ba0ef6-22b4-45f2-8f2d-450d76b8ca84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598572312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.1598572312
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.4010630362
Short name T191
Test name
Test status
Simulation time 3657743204 ps
CPU time 3.21 seconds
Started Jun 02 02:45:43 PM PDT 24
Finished Jun 02 02:45:47 PM PDT 24
Peak memory 201536 kb
Host smart-1deab566-7c23-4f40-b64d-75631e4309d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010630362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.4010630362
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.2389422096
Short name T574
Test name
Test status
Simulation time 5744771498 ps
CPU time 14.12 seconds
Started Jun 02 02:45:44 PM PDT 24
Finished Jun 02 02:45:59 PM PDT 24
Peak memory 201544 kb
Host smart-6cb3fb1c-e43c-4128-879f-d3b7e2b4bdf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389422096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.2389422096
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.339479997
Short name T723
Test name
Test status
Simulation time 239565353141 ps
CPU time 695.18 seconds
Started Jun 02 02:45:45 PM PDT 24
Finished Jun 02 02:57:21 PM PDT 24
Peak memory 202112 kb
Host smart-7efc9c84-1239-4987-b7e7-8443381b4b2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339479997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.339479997
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.304245076
Short name T23
Test name
Test status
Simulation time 120394623912 ps
CPU time 291.33 seconds
Started Jun 02 02:45:55 PM PDT 24
Finished Jun 02 02:50:47 PM PDT 24
Peak memory 217932 kb
Host smart-664373ce-b1fc-4acb-ace4-d82588d9773a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304245076 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.304245076
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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