Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6873	1			T1	20		T4	49		T7	6
testmodes[AdcCtrlTestmodeNormal]	5410	1			T4	41		T6	1		T7	9
testmodes[AdcCtrlTestmodeLowpower]	5885	1			T2	2		T3	3		T4	43
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3710	1			T1	19		T4	16		T7	2
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1672	1			T4	16		T7	4		T10	4
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1384	1			T4	17		T44	17		T16	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1717	1			T4	15		T7	4		T10	3
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1978	1			T4	13		T7	4		T10	2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1370	1			T4	12		T41	1		T44	20
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1340	1			T4	18		T44	16		T56	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1426	1			T4	11		T44	22		T42	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2874	1			T2	1		T3	2		T4	14