Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26272

1

T1

20

T2

34

T3

38

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22631

1

T1

20

T3

29

T4

133

auto[ADC_CTRL_FILTER_COND_OUT]

3641

1

T2

34

T3

9

T8

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19959

1

T1

20

T3

29

T4

129

auto[1]

6313

1

T2

34

T3

9

T4

4

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22246

1

T1

20

T2

15

T3

38

auto[1]

4026

1

T2

19

T12

14

T14

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	489	1			T4	4		T44	2		T16	1
values[0]	42	1			T160	2		T190	1		T227	14
values[1]	578	1			T3	14		T56	52		T191	3
values[2]	2967	1			T5	22		T8	1		T11	1
values[3]	694	1			T2	5		T39	12		T40	19
values[4]	645	1			T2	29		T3	9		T6	1
values[5]	746	1			T42	3		T36	10		T214	22
values[6]	746	1			T41	20		T150	25		T27	18
values[7]	713	1			T12	8		T15	1		T39	16
values[8]	730	1			T11	1		T41	11		T42	22
values[9]	1158	1			T3	15		T39	16		T42	12
minimum	16764	1			T1	20		T4	129		T7	15

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	776	1			T3	14		T8	1		T11	1
values[1]	3126	1			T5	22		T13	10		T14	12
values[2]	510	1			T2	34		T39	12		T40	32
values[3]	658	1			T6	1		T12	20		T191	7
values[4]	749	1			T3	9		T42	3		T27	18
values[5]	796	1			T41	20		T150	25		T143	31
values[6]	712	1			T11	1		T15	1		T41	11
values[7]	625	1			T12	8		T39	16		T145	11
values[8]	890	1			T3	15		T39	16		T42	34
values[9]	184	1			T152	1		T49	1		T190	1
minimum	17246	1			T1	20		T4	133		T7	15

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22194

1

T1

20

T2

21

T3

3

auto[1]

4078

1

T2

13

T3

35

T5

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T3	14		T11	1		T191	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T8	1		T56	18		T183	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1576	1			T5	22		T13	10		T14	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T147	10		T228	3		T37	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T40	13		T229	1		T20	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T2	15		T39	9		T40	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T6	1		T12	11		T191	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T162	11		T214	12		T230	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T30	1		T51	6		T167	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T3	9		T42	3		T27	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T41	10		T150	12		T51	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T143	15		T144	1		T154	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T15	1		T41	9		T229	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T11	1		T43	13		T16	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T145	6		T20	1		T182	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T12	3		T39	3		T210	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T3	15		T39	12		T42	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T42	11		T43	10		T144	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T152	1		T49	1		T190	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T231	18		T232	9		T169	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17112	1			T1	20		T4	133		T7	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T233	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T194	2		T32	12		T35	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T56	34		T160	1		T234	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1085	1			T14	11		T41	8		T193	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T228	9		T37	6		T49	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T229	7		T20	2		T235	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T2	19		T39	3		T165	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T12	9		T166	5		T236	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T214	10		T211	3		T237	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T51	2		T167	14		T49	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T27	7		T36	3		T183	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T41	10		T150	13		T51	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T143	16		T144	1		T178	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T41	2		T229	13		T228	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T43	18		T16	3		T32	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T145	5		T20	1		T238	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T12	5		T39	13		T164	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T39	4		T42	4		T27	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T42	11		T43	10		T144	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T213	10		T239	4		T96	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T232	8		T240	1		T206	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T42	2		T17	2		T35	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	488	1			T4	4		T44	2		T16	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T160	1		T190	1		T227	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T3	14		T191	3		T194	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T56	18		T183	1		T234	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1478	1			T5	22		T11	1		T13	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T8	1		T147	10		T228	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T41	1		T42	1		T152	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T2	2		T39	9		T40	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T6	1		T12	11		T40	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T2	13		T3	9		T162	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T168	10		T161	1		T241	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T42	3		T36	7		T214	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T41	10		T150	12		T30	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T27	11		T143	15		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T15	1		T155	1		T228	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T12	3		T39	3		T43	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T41	9		T229	1		T145	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T11	1		T42	11		T210	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T3	15		T39	12		T42	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	395	1			T43	10		T144	11		T19	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16631	1			T1	20		T4	129		T7	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T242	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T160	1		T227	2		T243	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T194	2		T35	1		T244	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T56	34		T234	6		T245	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1014	1			T14	11		T193	21		T195	25
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T228	9		T49	11		T80	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T41	8		T152	13		T229	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T2	3		T39	3		T165	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T12	9		T166	5		T235	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T2	16		T211	3		T237	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T168	7		T161	6		T204	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T36	3		T214	10		T183	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T41	10		T150	13		T51	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T27	7		T143	16		T144	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T155	12		T228	2		T176	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T12	5		T39	13		T43	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T41	2		T229	13		T145	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T42	11		T164	19		T37	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T39	4		T42	4		T27	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T43	10		T144	14		T19	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T42	2		T17	2		T35	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T3	1		T11	1		T191	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T8	1		T56	36		T183	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1428	1			T5	2		T13	1		T14	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T147	1		T228	10		T37	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T40	1		T229	8		T20	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T2	21		T39	4		T40	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T6	1		T12	10		T191	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T162	1		T214	11		T230	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T30	1		T51	3		T167	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T3	1		T42	1		T27	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T41	11		T150	14		T51	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T143	17		T144	2		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T15	1		T41	3		T229	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T11	1		T43	19		T16	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T145	6		T20	2		T182	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T12	6		T39	14		T210	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T3	1		T39	5		T42	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T42	12		T43	11		T144	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T152	1		T49	1		T190	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T231	1		T232	9		T169	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17245	1			T1	20		T4	133		T7	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T233	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T3	13		T191	2		T32	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T56	16		T245	12		T246	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1233	1			T5	20		T13	9		T152	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T147	9		T228	2		T37	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T40	12		T20	2		T160	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T2	13		T39	8		T40	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T12	10		T191	6		T236	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T162	10		T214	11		T247	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T51	5		T49	12		T168	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T3	8		T42	2		T27	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T41	9		T150	11		T51	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T143	14		T154	12		T178	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T41	8		T228	5		T22	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T43	12		T16	5		T32	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T145	5		T231	16		T238	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T12	2		T39	2		T210	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T3	14		T39	11		T42	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T42	10		T43	9		T144	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T248	7		T249	5		T213	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T231	17		T232	8		T169	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	484	1			T4	4		T44	2		T16	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T160	2		T190	1		T227	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T3	1		T191	1		T194	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T56	36		T183	1		T234	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1351	1			T5	2		T11	1		T13	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T8	1		T147	1		T228	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T41	9		T42	1		T152	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T2	4		T39	4		T40	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T6	1		T12	10		T40	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T2	17		T3	1		T162	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T168	8		T161	7		T241	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T42	1		T36	6		T214	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T41	11		T150	14		T30	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T27	8		T143	17		T144	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T15	1		T155	13		T228	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T12	6		T39	14		T43	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T41	3		T229	14		T145	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T11	1		T42	12		T210	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T3	1		T39	5		T42	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T43	11		T144	15		T19	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16764	1			T1	20		T4	129		T7	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T249	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T227	11		T243	6		T250	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T3	13		T191	2		T33	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T56	16		T245	12		T246	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1141	1			T5	20		T13	9		T32	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T147	9		T228	2		T251	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T152	14		T20	2		T166	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T2	1		T39	8		T40	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T12	10		T40	12		T191	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T2	12		T3	8		T162	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T168	9		T252	9		T253	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T42	2		T36	4		T214	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T41	9		T150	11		T51	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T27	10		T143	14		T154	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T228	5		T176	2		T168	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T12	2		T39	2		T43	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T41	8		T145	5		T231	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T42	10		T210	18		T164	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T3	14		T39	11		T42	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T43	9		T144	10		T19	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22194

1

T1

20

T2

21

T3

3

auto[1]

auto[0]

4078

1

T2

13

T3

35

T5

20

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26272

1

T1

20

T2

34

T3

38

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22821

1

T1

20

T2

34

T3

24

auto[ADC_CTRL_FILTER_COND_OUT]

3451

1

T3

14

T15

1

T39

28

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20266

1

T1

20

T3

29

T4

133

auto[1]

6006

1

T2

34

T3

9

T5

22

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22246

1

T1

20

T2

15

T3

38

auto[1]

4026

1

T2

19

T12

14

T14

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	77	1			T17	12		T254	13		T255	19
values[1]	707	1			T12	8		T41	20		T162	11
values[2]	563	1			T42	22		T18	1		T164	37
values[3]	763	1			T12	20		T39	12		T43	20
values[4]	3003	1			T2	5		T5	22		T6	1
values[5]	708	1			T3	15		T40	13		T42	12
values[6]	489	1			T16	14		T27	33		T144	2
values[7]	688	1			T3	14		T11	1		T56	18
values[8]	749	1			T8	1		T39	16		T43	31
values[9]	1280	1			T2	29		T3	9		T11	1
minimum	17245	1			T1	20		T4	133		T7	15

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	860	1			T12	8		T41	20		T17	12
values[1]	672	1			T12	20		T42	22		T194	3
values[2]	696	1			T6	1		T39	12		T42	3
values[3]	3022	1			T2	5		T5	22		T13	10
values[4]	587	1			T3	15		T16	14		T27	33
values[5]	577	1			T3	14		T40	13		T56	18
values[6]	622	1			T11	1		T39	16		T27	18
values[7]	778	1			T8	1		T41	11		T43	31
values[8]	947	1			T11	1		T15	1		T41	9
values[9]	179	1			T2	29		T3	9		T39	16
minimum	17332	1			T1	20		T4	133		T7	15

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22194

1

T1

20

T2

21

T3

3

auto[1]

4078

1

T2

13

T3

35

T5

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T12	3		T155	1		T164	18
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T41	10		T17	7		T256	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T12	11		T42	11		T194	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T30	1		T162	11		T176	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T6	1		T42	3		T43	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T39	9		T49	13		T257	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1572	1			T2	2		T5	22		T13	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T40	19		T30	1		T33	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T3	15		T28	1		T35	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T16	11		T27	18		T143	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T56	3		T153	1		T51	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T3	14		T40	13		T35	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T11	1		T19	15		T228	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T39	12		T27	11		T36	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T8	1		T43	13		T37	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T41	9		T20	1		T178	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T11	1		T42	1		T150	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T15	1		T41	1		T56	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T2	13		T3	9		T39	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T191	7		T158	1		T168	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17126	1			T1	20		T4	133		T7	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T168	10		T258	7		T259	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T12	5		T164	19		T166	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T41	10		T17	5		T161	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T12	9		T42	11		T194	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T176	12		T160	17		T161	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T43	10		T155	12		T167	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T39	3		T49	11		T184	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1047	1			T2	3		T14	11		T42	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T145	5		T228	11		T260	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T35	1		T165	2		T37	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T16	3		T27	15		T143	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T56	15		T51	6		T235	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T35	7		T261	4		T211	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T19	10		T228	9		T178	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T39	4		T27	7		T36	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T43	18		T37	9		T244	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T41	2		T20	1		T178	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T150	13		T20	2		T166	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T41	8		T56	19		T152	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T2	16		T39	13		T144	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T168	9		T262	13		T96	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T42	2		T17	2		T35	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T168	7		T258	16		T259	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T263	9		T264	1		T265	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T17	7		T254	13		T255	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T12	3		T155	1		T37	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T41	10		T162	11		T256	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T42	11		T18	1		T164	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T231	17		T161	1		T50	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T12	11		T43	10		T194	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T39	9		T30	1		T176	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1612	1			T2	2		T5	22		T6	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T40	19		T30	1		T145	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T3	15		T42	8		T28	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T40	13		T33	11		T143	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T51	9		T163	1		T165	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T16	11		T27	18		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T11	1		T56	3		T153	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T3	14		T27	11		T35	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T8	1		T43	13		T37	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T39	12		T229	2		T20	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	330	1			T2	13		T3	9		T11	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	383	1			T15	1		T41	10		T56	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17112	1			T1	20		T4	133		T7	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T264	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T17	5		T255	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T12	5		T37	6		T169	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T41	10		T168	7		T161	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T42	11		T164	19		T166	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T161	11		T266	9		T260	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T12	9		T43	10		T194	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T39	3		T176	12		T160	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1028	1			T2	3		T14	11		T193	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T145	5		T228	2		T49	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T42	4		T35	1		T37	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T143	16		T228	9		T37	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T51	6		T165	2		T49	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T16	3		T27	15		T144	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T56	15		T19	10		T228	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T27	7		T35	7		T36	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T43	18		T37	9		T211	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T39	4		T229	20		T20	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T2	16		T39	13		T150	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T41	10		T56	19		T152	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T42	2		T17	2		T35	1