Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26272

1

T1

20

T2

34

T3

38

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23009

1

T1

20

T2

29

T3

29

auto[ADC_CTRL_FILTER_COND_OUT]

3263

1

T2

5

T3

9

T6

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20339

1

T1

20

T2

34

T3

38

auto[1]

5933

1

T5

22

T6

1

T11

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22246

1

T1

20

T2

15

T3

38

auto[1]

4026

1

T2

19

T12

14

T14

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	116	1			T20	6		T266	19		T316	1
values[0]	36	1			T49	24		T211	11		T317	1
values[1]	668	1			T6	1		T39	12		T42	12
values[2]	937	1			T12	20		T15	1		T41	20
values[3]	720	1			T3	24		T42	22		T150	25
values[4]	617	1			T2	29		T11	1		T39	16
values[5]	2914	1			T5	22		T13	10		T14	12
values[6]	713	1			T8	1		T12	8		T191	3
values[7]	797	1			T2	5		T11	1		T40	13
values[8]	631	1			T144	25		T145	11		T19	25
values[9]	878	1			T3	14		T39	16		T40	19
minimum	17245	1			T1	20		T4	133		T7	15

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	736	1			T42	13		T191	7		T152	28
values[1]	871	1			T12	20		T15	1		T41	20
values[2]	547	1			T3	24		T11	1		T42	22
values[3]	2945	1			T2	29		T5	22		T13	10
values[4]	799	1			T8	1		T194	3		T30	1
values[5]	628	1			T12	8		T43	31		T191	3
values[6]	706	1			T2	5		T11	1		T40	13
values[7]	590	1			T3	14		T40	19		T144	25
values[8]	727	1			T39	16		T41	9		T42	3
values[9]	193	1			T56	18		T20	6		T168	17
minimum	17530	1			T1	20		T4	133		T6	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22194

1

T1

20

T2

21

T3

3

auto[1]

4078

1

T2

13

T3

35

T5

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T42	8		T191	7		T30	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T42	1		T152	15		T162	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T12	11		T15	1		T41	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T28	1		T32	11		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T3	15		T11	1		T176	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T3	9		T42	11		T56	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1557	1			T2	13		T5	22		T13	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T228	6		T37	1		T49	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T33	11		T143	15		T35	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T8	1		T194	1		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T12	3		T153	1		T166	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T43	13		T191	3		T27	29
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T11	1		T16	11		T154	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T2	2		T40	13		T43	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T3	14		T40	19		T144	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T19	15		T157	2		T247	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T39	3		T41	1		T42	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T17	7		T18	1		T147	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T56	3		T168	10		T319	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T20	4		T308	1		T109	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17184	1			T1	20		T4	133		T7	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T6	1		T39	9		T38	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T42	4		T229	13		T155	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T152	13		T211	6		T206	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T12	9		T41	10		T150	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T32	7		T147	11		T235	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T176	18		T235	12		T161	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T42	11		T56	19		T214	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1097	1			T2	16		T14	11		T39	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T228	2		T37	1		T268	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T143	16		T35	7		T36	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T194	2		T37	6		T236	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T12	5		T166	5		T49	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T43	18		T27	22		T35	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T16	3		T20	1		T178	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T2	3		T43	10		T145	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T144	14		T168	9		T50	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T19	10		T232	8		T260	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T39	13		T41	8		T144	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T17	5		T228	9		T178	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T56	15		T168	7		T204	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T20	2		T308	1		T109	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T42	2		T17	2		T35	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T39	3		T38	4		T160	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T266	10		T316	1		T319	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T20	4		T326	1		T109	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T49	13		T211	8		T317	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T42	8		T191	7		T30	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T6	1		T39	9		T162	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T12	11		T15	1		T41	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T42	1		T152	15		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T3	15		T150	12		T51	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T3	9		T42	11		T56	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T2	13		T11	1		T39	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T228	6		T37	1		T190	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1556	1			T5	22		T13	10		T14	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T194	1		T30	1		T37	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T12	3		T33	11		T143	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T8	1		T191	3		T27	29
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T11	1		T16	11		T153	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T2	2		T40	13		T43	23
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T144	11		T20	1		T304	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T145	6		T19	15		T157	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T3	14		T39	3		T40	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T17	7		T18	1		T147	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17112	1			T1	20		T4	133		T7	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T266	9		T294	9		T275	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T20	2		T109	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T49	11		T211	3		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T42	4		T155	12		T160	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T39	3		T38	4		T235	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T12	9		T41	10		T32	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T152	13		T32	7		T147	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T150	13		T51	2		T176	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T42	11		T56	19		T214	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T2	16		T39	4		T41	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T228	2		T37	1		T268	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1065	1			T14	11		T193	21		T195	25
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T194	2		T37	6		T251	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T12	5		T143	16		T166	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T27	22		T35	1		T166	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T16	3		T178	8		T290	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T2	3		T43	28		T51	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T144	14		T20	1		T168	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T145	5		T19	10		T232	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T39	13		T41	8		T56	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T17	5		T228	9		T178	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T42	2		T17	2		T35	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T42	5		T191	1		T30	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T42	1		T152	14		T162	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T12	10		T15	1		T41	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T28	1		T32	8		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T3	1		T11	1		T176	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T3	1		T42	12		T56	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1434	1			T2	17		T5	2		T13	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T228	3		T37	2		T49	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T33	1		T143	17		T35	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T8	1		T194	3		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T12	6		T153	1		T166	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T43	19		T191	1		T27	24
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T11	1		T16	9		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T2	4		T40	1		T43	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T3	1		T40	1		T144	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T19	17		T157	1		T247	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T39	14		T41	9		T42	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T17	9		T18	1		T147	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T56	16		T168	8		T319	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T20	4		T308	2		T109	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17346	1			T1	20		T4	133		T7	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T6	1		T39	4		T38	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T42	7		T191	6		T154	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T152	14		T162	10		T211	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T12	10		T41	9		T150	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T32	10		T147	21		T244	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T3	14		T176	14		T169	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T3	8		T42	10		T56	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1220	1			T2	12		T5	20		T13	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T228	5		T269	13		T268	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T33	10		T143	14		T35	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T210	18		T37	6		T236	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T12	2		T183	10		T261	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T43	12		T191	2		T27	27
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T16	5		T154	7		T178	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T2	1		T40	12		T43	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T3	13		T40	18		T144	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T19	8		T157	1		T247	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T39	2		T42	2		T165	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T17	3		T147	9		T228	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T56	2		T168	9		T319	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T20	2		T109	8		T321	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T49	12		T284	8		T231	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T39	8		T38	4		T227	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T266	10		T316	1		T319	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T20	4		T326	1		T109	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T49	12		T211	4		T317	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T42	5		T191	1		T30	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T6	1		T39	4		T162	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T12	10		T15	1		T41	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T42	1		T152	14		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T3	1		T150	14		T51	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T3	1		T42	12		T56	20
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T2	17		T11	1		T39	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T228	3		T37	2		T190	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1408	1			T5	2		T13	1		T14	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T194	3		T30	1		T37	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T12	6		T33	1		T143	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T8	1		T191	1		T27	24
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T11	1		T16	9		T153	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T2	4		T40	1		T43	30
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T144	15		T20	2		T304	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T145	6		T19	17		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T3	1		T39	14		T40	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T17	9		T18	1		T147	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17245	1			T1	20		T4	133		T7	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T266	9		T319	10		T275	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T20	2		T109	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T49	12		T211	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T42	7		T191	6		T154	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T39	8		T162	10		T38	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T12	10		T41	9		T32	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T152	14		T32	10		T147	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T3	14		T150	11		T51	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T3	8		T42	10		T56	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T2	12		T39	11		T41	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T228	5		T269	13		T268	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1213	1			T5	20		T13	9		T322	30
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T37	6		T251	15		T24	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T12	2		T33	10		T143	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T191	2		T27	27		T35	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T16	5		T154	7		T178	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T2	1		T40	12		T43	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T144	10		T168	6		T244	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T145	5		T19	8		T157	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T3	13		T39	2		T40	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T17	3		T147	9		T228	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22194

1

T1

20

T2

21

T3

3

auto[1]

auto[0]

4078

1

T2

13

T3

35

T5

20