Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26272

1

T1

20

T2

34

T3

38

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22761

1

T1

20

T2

5

T3

9

auto[ADC_CTRL_FILTER_COND_OUT]

3511

1

T2

29

T3

29

T6

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20531

1

T1

20

T2

5

T3

9

auto[1]

5741

1

T2

29

T3

29

T5

22

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22246

1

T1

20

T2

15

T3

38

auto[1]

4026

1

T2

19

T12

14

T14

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	52	1			T327	18		T328	16		T329	17
values[0]	61	1			T235	4		T287	2		T305	1
values[1]	528	1			T12	8		T56	34		T30	1
values[2]	842	1			T12	20		T43	31		T150	25
values[3]	597	1			T40	13		T41	11		T16	14
values[4]	593	1			T39	28		T42	4		T32	18
values[5]	749	1			T3	29		T11	1		T42	34
values[6]	601	1			T39	16		T152	28		T32	25
values[7]	841	1			T40	19		T41	29		T152	1
values[8]	3019	1			T5	22		T11	1		T13	10
values[9]	1144	1			T2	34		T3	9		T6	1
minimum	17245	1			T1	20		T4	133		T7	15

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	858	1			T12	28		T56	34		T30	1
values[1]	738	1			T40	13		T43	31		T150	25
values[2]	561	1			T39	28		T41	11		T42	3
values[3]	772	1			T3	15		T42	1		T17	12
values[4]	477	1			T3	14		T11	1		T42	34
values[5]	785	1			T39	16		T40	19		T152	29
values[6]	3058	1			T5	22		T13	10		T14	12
values[7]	603	1			T8	1		T11	1		T191	3
values[8]	945	1			T2	34		T3	9		T15	1
values[9]	225	1			T6	1		T20	1		T176	25
minimum	17250	1			T1	20		T4	133		T7	15

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22194

1

T1

20

T2

21

T3

3

auto[1]

4078

1

T2

13

T3

35

T5

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T12	3		T157	2		T163	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T12	11		T56	15		T30	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T40	13		T43	13		T150	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T19	15		T20	4		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T42	3		T16	11		T214	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T39	21		T41	9		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T32	11		T144	1		T147	22
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T3	15		T42	1		T17	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T32	13		T145	6		T155	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T3	14		T11	1		T42	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T39	3		T144	11		T166	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T40	19		T152	16		T18	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1571	1			T5	22		T13	10		T14	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T155	1		T228	6		T49	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T8	1		T27	18		T162	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T11	1		T191	3		T194	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T2	2		T3	9		T15	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T2	13		T43	10		T51	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T20	1		T283	1		T237	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T6	1		T176	13		T304	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17112	1			T1	20		T4	133		T7	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T200	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T12	5		T235	3		T251	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T12	9		T56	19		T143	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T43	18		T150	13		T20	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T19	10		T20	2		T261	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T16	3		T214	10		T228	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T39	7		T41	2		T229	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T32	7		T144	1		T147	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T17	5		T165	2		T167	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T32	12		T145	5		T160	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T42	15		T234	6		T246	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T39	13		T144	14		T166	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T152	13		T178	8		T244	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1076	1			T14	11		T41	18		T193	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T155	12		T228	2		T49	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T27	15		T228	9		T164	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T194	2		T35	1		T51	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T2	3		T56	15		T178	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T2	16		T43	10		T51	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T237	4		T277	2		T302	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T176	12		T308	1		T24	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T42	2		T17	2		T35	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T327	10		T328	8		T330	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T329	17		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T235	1		T287	1		T305	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T307	1		T312	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T12	3		T157	2		T251	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T56	15		T30	1		T35	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T43	13		T150	12		T191	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T12	11		T143	15		T229	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T40	13		T16	11		T153	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T41	9		T28	1		T229	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T42	3		T32	11		T144	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T39	21		T42	1		T147	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T155	1		T147	22		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T3	29		T11	1		T42	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T39	3		T32	13		T166	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T152	15		T50	1		T241	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T41	11		T27	29		T144	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T40	19		T152	1		T18	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1557	1			T5	22		T13	10		T14	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T11	1		T43	10		T191	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T2	2		T3	9		T8	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	369	1			T2	13		T6	1		T51	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17112	1			T1	20		T4	133		T7	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T327	8		T328	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T235	3		T287	1		T331	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T307	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T12	5		T251	17		T270	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T56	19		T35	7		T49	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T43	18		T150	13		T20	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T12	9		T143	16		T229	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T16	3		T214	10		T228	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T41	2		T229	7		T235	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T32	7		T144	1		T145	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T39	7		T165	2		T37	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T147	11		T245	12		T206	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T42	15		T17	5		T178	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T39	13		T32	12		T166	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T152	13		T244	4		T171	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T41	18		T27	22		T144	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T155	12		T228	2		T236	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1050	1			T14	11		T193	21		T195	25
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T43	10		T194	2		T35	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T2	3		T56	15		T178	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T2	16		T51	8		T166	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T42	2		T17	2		T35	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T12	6		T157	1		T163	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T12	10		T56	20		T30	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T40	1		T43	19		T150	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T19	17		T20	4		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T42	1		T16	9		T214	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T39	9		T41	3		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T32	8		T144	2		T147	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T3	1		T42	1		T17	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T32	13		T145	6		T155	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T3	1		T11	1		T42	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T39	14		T144	15		T166	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T40	1		T152	15		T18	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1417	1			T5	2		T13	1		T14	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T155	13		T228	3		T49	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T8	1		T27	16		T162	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T11	1		T191	1		T194	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T2	4		T3	1		T15	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T2	17		T43	11		T51	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T20	1		T283	1		T237	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T6	1		T176	13		T304	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17245	1			T1	20		T4	133		T7	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T200	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T12	2		T157	1		T251	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T12	10		T56	14		T143	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T40	12		T43	12		T150	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T19	8		T20	2		T261	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T42	2		T16	5		T214	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T39	19		T41	8		T37	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T32	10		T147	21		T236	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T3	14		T17	3		T154	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T32	12		T145	5		T160	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T3	13		T42	17		T246	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T39	2		T144	10		T166	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T40	18		T152	14		T178	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1230	1			T5	20		T13	9		T41	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T228	5		T236	16		T231	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T27	17		T162	10		T228	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T191	2		T35	1		T51	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T2	1		T3	8		T56	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T2	12		T43	9		T51	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T302	2		T310	5		T311	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T176	12		T314	1		T24	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T200	4		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T327	9		T328	9		T330	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T329	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T235	4		T287	2		T305	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T307	11		T312	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T12	6		T157	1		T251	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T56	20		T30	1		T35	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T43	19		T150	14		T191	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T12	10		T143	17		T229	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T40	1		T16	9		T153	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T41	3		T28	1		T229	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T42	1		T32	8		T144	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T39	9		T42	1		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T155	1		T147	12		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T3	2		T11	1		T42	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T39	14		T32	13		T166	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T152	14		T50	1		T241	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T41	20		T27	24		T144	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T40	1		T152	1		T18	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1396	1			T5	2		T13	1		T14	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T11	1		T43	11		T191	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T2	4		T3	1		T8	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	398	1			T2	17		T6	1		T51	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17245	1			T1	20		T4	133		T7	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T327	9		T328	7		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T329	16		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T332	19		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T312	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T12	2		T157	1		T251	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T56	14		T35	5		T154	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T43	12		T150	11		T191	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T12	10		T143	14		T19	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T40	12		T16	5		T214	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T41	8		T211	3		T169	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T42	2		T32	10		T145	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T39	19		T147	9		T165	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T147	21		T245	12		T206	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T3	27		T42	17		T17	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T39	2		T32	12		T166	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T152	14		T244	10		T171	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T41	9		T27	27		T144	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T40	18		T228	5		T256	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1211	1			T5	20		T13	9		T322	30
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T43	9		T191	2		T35	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T2	1		T3	8		T56	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T2	12		T51	13		T176	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22194

1

T1

20

T2

21

T3

3

auto[1]

auto[0]

4078

1

T2

13

T3

35

T5

20