Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26272

1

T1

20

T2

34

T3

38

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23007

1

T1

20

T2

34

T3

23

auto[ADC_CTRL_FILTER_COND_OUT]

3265

1

T3

15

T6

1

T8

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20314

1

T1

20

T3

9

T4

133

auto[1]

5958

1

T2

34

T3

29

T5

22

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22246

1

T1

20

T2

15

T3

38

auto[1]

4026

1

T2

19

T12

14

T14

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	418	1			T154	13		T20	1		T214	22
values[0]	46	1			T56	18		T232	17		T333	11
values[1]	852	1			T2	29		T40	13		T41	20
values[2]	664	1			T11	1		T12	8		T39	16
values[3]	640	1			T2	5		T11	1		T12	20
values[4]	796	1			T3	14		T39	16		T41	11
values[5]	2862	1			T3	9		T5	22		T8	1
values[6]	508	1			T15	1		T42	12		T191	7
values[7]	801	1			T6	1		T43	31		T56	34
values[8]	471	1			T42	3		T194	3		T30	1
values[9]	969	1			T3	15		T39	12		T40	19
minimum	17245	1			T1	20		T4	133		T7	15

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	969	1			T2	29		T11	1		T41	20
values[1]	646	1			T2	5		T11	1		T12	8
values[2]	760	1			T3	14		T12	20		T43	20
values[3]	2954	1			T5	22		T13	10		T14	12
values[4]	478	1			T3	9		T8	1		T41	9
values[5]	630	1			T15	1		T42	12		T152	1
values[6]	718	1			T6	1		T43	31		T56	34
values[7]	529	1			T3	15		T42	3		T194	3
values[8]	1014	1			T39	12		T40	19		T143	31
values[9]	188	1			T20	1		T146	1		T164	37
minimum	17386	1			T1	20		T4	133		T7	15

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22194

1

T1

20

T2

21

T3

3

auto[1]

4078

1

T2

13

T3

35

T5

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T2	13		T41	10		T152	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T11	1		T32	24		T144	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T2	2		T39	12		T42	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T11	1		T12	3		T42	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T3	14		T12	11		T16	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T43	10		T163	1		T166	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1493	1			T5	22		T13	10		T14	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T150	12		T36	7		T20	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T3	9		T191	3		T17	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T8	1		T41	1		T191	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T15	1		T42	8		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T182	1		T49	14		T160	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T56	15		T27	18		T28	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T6	1		T43	13		T35	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T42	3		T194	1		T51	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T3	15		T30	1		T19	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	333	1			T39	9		T40	19		T143	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T153	1		T51	9		T155	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T146	1		T257	1		T238	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T20	1		T164	18		T334	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17126	1			T1	20		T4	133		T7	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T40	13		T147	22		T335	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T2	16		T41	10		T152	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T32	19		T144	14		T155	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T2	3		T39	4		T42	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T12	5		T168	7		T232	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T12	9		T16	3		T37	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T43	10		T166	5		T165	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1010	1			T14	11		T39	13		T41	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T150	13		T36	3		T20	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T17	5		T235	12		T336	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T41	8		T80	2		T287	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T42	4		T27	7		T145	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T49	11		T160	1		T245	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T56	19		T27	15		T35	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T43	18		T35	7		T144	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T194	2		T51	2		T228	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T19	10		T178	8		T167	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T39	3		T143	16		T214	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T51	6		T80	9		T244	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T238	11		T118	9		T323	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T164	19		T295	5		T201	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T42	2		T56	15		T17	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T147	11		T337	11		T243	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T154	13		T214	12		T257	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T20	1		T164	18		T190	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T56	3		T232	13		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T333	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T2	13		T41	10		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T40	13		T32	24		T144	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T39	12		T42	11		T152	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T11	1		T12	3		T182	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T2	2		T12	11		T210	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T11	1		T42	1		T163	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T3	14		T39	3		T41	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T43	10		T150	12		T20	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1465	1			T3	9		T5	22		T13	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T8	1		T41	1		T36	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T15	1		T42	8		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T191	7		T182	1		T49	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T56	15		T27	18		T28	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T6	1		T43	13		T35	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T42	3		T194	1		T51	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T30	1		T144	1		T178	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T39	9		T40	19		T143	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T3	15		T153	1		T19	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17112	1			T1	20		T4	133		T7	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T214	10		T238	11		T206	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T164	19		T268	9		T23	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T56	15		T232	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T2	16		T41	10		T37	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T32	19		T144	14		T155	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T39	4		T42	11		T152	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T12	5		T168	7		T232	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T2	3		T12	9		T176	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T165	2		T271	5		T338	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T39	13		T41	2		T16	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T43	10		T150	13		T20	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1006	1			T14	11		T193	21		T195	25
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T41	8		T36	3		T236	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T42	4		T27	7		T80	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T49	11		T245	14		T294	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T56	19		T27	15		T35	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T43	18		T35	7		T229	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T194	2		T51	2		T228	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T144	1		T178	8		T244	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T39	3		T143	16		T228	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T19	10		T51	6		T167	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T42	2		T17	2		T35	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T2	17		T41	11		T152	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T11	1		T32	21		T144	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T2	4		T39	5		T42	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T11	1		T12	6		T42	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T3	1		T12	10		T16	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T43	11		T163	1		T166	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1339	1			T5	2		T13	1		T14	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T150	14		T36	6		T20	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T3	1		T191	1		T17	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T8	1		T41	9		T191	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T15	1		T42	5		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T182	1		T49	13		T160	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T56	20		T27	16		T28	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T6	1		T43	19		T35	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T42	1		T194	3		T51	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T3	1		T30	1		T19	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T39	4		T40	1		T143	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T153	1		T51	7		T155	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T146	1		T257	1		T238	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T20	1		T164	20		T334	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17279	1			T1	20		T4	133		T7	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T40	1		T147	12		T335	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T2	12		T41	9		T152	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T32	22		T144	10		T228	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T2	1		T39	11		T42	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T12	2		T247	10		T168	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T3	13		T12	10		T16	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T43	9		T165	9		T261	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1164	1			T5	20		T13	9		T39	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T150	11		T36	4		T236	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T3	8		T191	2		T17	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T191	6		T297	11		T212	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T42	7		T27	10		T145	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T49	12		T245	12		T281	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T56	14		T27	17		T162	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T43	12		T35	5		T231	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T42	2		T51	5		T228	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T3	14		T19	8		T178	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T39	8		T40	18		T143	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T51	8		T269	13		T268	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T238	12		T118	3		T285	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T164	17		T185	1		T295	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T56	2		T339	3		T340	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T40	12		T147	21		T243	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T154	1		T214	11		T257	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T20	1		T164	20		T190	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T56	16		T232	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T333	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T2	17		T41	11		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T40	1		T32	21		T144	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T39	5		T42	12		T152	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T11	1		T12	6		T182	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T2	4		T12	10		T210	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T11	1		T42	1		T163	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T3	1		T39	14		T41	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T43	11		T150	14		T20	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1332	1			T3	1		T5	2		T13	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T8	1		T41	9		T36	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T15	1		T42	5		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T191	1		T182	1		T49	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T56	20		T27	16		T28	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T6	1		T43	19		T35	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T42	1		T194	3		T51	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T30	1		T144	2		T178	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T39	4		T40	1		T143	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T3	1		T153	1		T19	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17245	1			T1	20		T4	133		T7	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T154	12		T214	11		T238	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T164	17		T268	11		T23	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T56	2		T232	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T333	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T2	12		T41	9		T37	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T40	12		T32	22		T144	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T39	11		T42	10		T152	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T12	2		T247	10		T168	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T2	1		T12	10		T210	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T165	9		T271	6		T341	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T3	13		T39	2		T41	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T43	9		T150	11		T168	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1139	1			T3	8		T5	20		T13	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T36	4		T236	7		T168	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T42	7		T27	10		T336	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T191	6		T49	12		T245	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T56	14		T27	17		T162	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T43	12		T35	5		T231	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T42	2		T51	5		T228	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T178	8		T244	29		T232	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T39	8		T40	18		T143	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T3	14		T19	8		T51	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22194

1

T1

20

T2

21

T3

3

auto[1]

auto[0]

4078

1

T2

13

T3

35

T5

20