Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26272

1

T1

20

T2

34

T3

38

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22875

1

T1

20

T2

34

T3

24

auto[ADC_CTRL_FILTER_COND_OUT]

3397

1

T3

14

T15

1

T39

28

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20239

1

T1

20

T3

29

T4

133

auto[1]

6033

1

T2

34

T3

9

T5

22

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22246

1

T1

20

T2

15

T3

38

auto[1]

4026

1

T2

19

T12

14

T14

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	273	1			T3	9		T11	1		T152	28
values[0]	21	1			T17	12		T263	9		-	-
values[1]	767	1			T12	8		T41	20		T162	11
values[2]	576	1			T12	20		T42	22		T18	1
values[3]	768	1			T39	12		T43	20		T194	3
values[4]	2952	1			T2	5		T5	22		T6	1
values[5]	723	1			T3	15		T40	13		T42	12
values[6]	470	1			T16	14		T27	33		T144	2
values[7]	675	1			T3	14		T11	1		T56	18
values[8]	801	1			T8	1		T39	16		T43	31
values[9]	1001	1			T2	29		T15	1		T39	16
minimum	17245	1			T1	20		T4	133		T7	15

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	591	1			T12	8		T41	20		T155	1
values[1]	664	1			T12	20		T42	22		T194	3
values[2]	739	1			T6	1		T39	12		T42	3
values[3]	2939	1			T2	5		T5	22		T13	10
values[4]	728	1			T3	15		T40	13		T16	14
values[5]	533	1			T3	14		T11	1		T56	18
values[6]	606	1			T39	16		T27	18		T36	10
values[7]	789	1			T8	1		T41	11		T43	31
values[8]	996	1			T11	1		T15	1		T39	16
values[9]	126	1			T2	29		T3	9		T191	7
minimum	17561	1			T1	20		T4	133		T7	15

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22194

1

T1

20

T2

21

T3

3

auto[1]

4078

1

T2

13

T3

35

T5

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T12	3		T155	1		T166	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T41	10		T256	8		T297	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T12	11		T42	11		T194	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T30	1		T162	11		T176	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T6	1		T42	3		T43	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T39	9		T49	13		T257	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1573	1			T2	2		T5	22		T13	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T40	19		T30	1		T33	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T3	15		T28	1		T35	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T40	13		T16	11		T27	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T11	1		T56	3		T153	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T3	14		T35	11		T144	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T19	15		T228	3		T178	21
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T39	12		T27	11		T36	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T8	1		T43	13		T37	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T41	9		T229	1		T20	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T11	1		T39	3		T42	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T15	1		T41	1		T56	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T2	13		T3	9		T144	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T191	7		T158	1		T262	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17176	1			T1	20		T4	133		T7	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T17	7		T168	10		T231	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T12	5		T166	5		T37	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T41	10		T255	9		T307	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T12	9		T42	11		T194	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T176	12		T160	17		T161	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T43	10		T155	12		T167	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T39	3		T49	11		T184	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1050	1			T2	3		T14	11		T42	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T145	5		T228	11		T260	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T35	1		T165	2		T37	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T16	3		T27	15		T143	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T56	15		T51	6		T235	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T35	7		T144	1		T261	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T19	10		T228	9		T178	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T39	4		T27	7		T36	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T43	18		T37	9		T232	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T41	2		T229	7		T20	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T39	13		T150	13		T20	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T41	8		T56	19		T152	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T2	16		T144	14		T168	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T262	13		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T42	2		T17	2		T35	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T17	5		T168	7		T161	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T3	9		T11	1		T144	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T152	15		T158	1		T230	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T263	9		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T17	7		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T12	3		T155	1		T37	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T41	10		T162	11		T256	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T12	11		T42	11		T18	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T231	17		T161	1		T50	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T43	10		T194	1		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T39	9		T30	1		T176	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1571	1			T2	2		T5	22		T6	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T40	19		T30	1		T145	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T3	15		T42	8		T28	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T40	13		T33	11		T143	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T51	9		T163	1		T165	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T16	11		T27	18		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T11	1		T56	3		T153	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T3	14		T27	11		T35	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T8	1		T43	13		T37	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T39	12		T229	2		T20	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T2	13		T39	3		T42	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T15	1		T41	10		T56	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17112	1			T1	20		T4	133		T7	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T144	14		T168	9		T279	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T152	13		T183	10		T211	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T17	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T12	5		T37	6		T284	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T41	10		T168	7		T161	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T12	9		T42	11		T164	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T161	11		T266	9		T260	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T43	10		T194	2		T155	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T39	3		T176	12		T160	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1003	1			T2	3		T14	11		T193	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T145	5		T228	2		T49	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T42	4		T35	1		T37	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T143	16		T228	9		T37	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T51	6		T165	2		T49	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T16	3		T27	15		T144	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T56	15		T19	10		T228	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T27	7		T35	7		T36	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T43	18		T37	9		T211	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T39	4		T229	20		T20	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T2	16		T39	13		T150	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T41	10		T56	19		T147	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T42	2		T17	2		T35	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T12	6		T155	1		T166	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T41	11		T256	1		T297	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T12	10		T42	12		T194	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T30	1		T162	1		T176	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T6	1		T42	1		T43	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T39	4		T49	12		T257	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1391	1			T2	4		T5	2		T13	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T40	1		T30	1		T33	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T3	1		T28	1		T35	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T40	1		T16	9		T27	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T11	1		T56	16		T153	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T3	1		T35	13		T144	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T19	17		T228	10		T178	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T39	5		T27	8		T36	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T8	1		T43	19		T37	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T41	3		T229	8		T20	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T11	1		T39	14		T42	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T15	1		T41	9		T56	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T2	17		T3	1		T144	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T191	1		T158	1		T262	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17330	1			T1	20		T4	133		T7	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T17	9		T168	8		T231	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T12	2		T37	6		T284	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T41	9		T256	7		T297	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T12	10		T42	10		T164	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T162	10		T176	12		T160	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T42	2		T43	9		T147	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T39	8		T49	12		T303	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1232	1			T2	1		T5	20		T13	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T40	18		T33	10		T145	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T3	14		T35	1		T154	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T40	12		T16	5		T27	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T56	2		T51	8		T267	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T3	13		T35	5		T154	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T19	8		T228	2		T178	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T39	11		T27	10		T36	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T43	12		T37	11		T247	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T41	8		T178	8		T268	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T39	2		T150	11		T20	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T56	14		T191	2		T152	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T2	12		T3	8		T144	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T191	6		T262	10		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T269	13		T169	9		T275	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T17	3		T168	9		T231	17

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T3	1		T11	1		T144	15
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T152	14		T158	1		T230	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T263	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T17	9		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T12	6		T155	1		T37	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T41	11		T162	1		T256	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T12	10		T42	12		T18	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T231	1		T161	12		T50	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T43	11		T194	3		T155	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T39	4		T30	1		T176	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1336	1			T2	4		T5	2		T6	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T40	1		T30	1		T145	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T3	1		T42	5		T28	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T40	1		T33	1		T143	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T51	7		T163	1		T165	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T16	9		T27	16		T144	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T11	1		T56	16		T153	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T3	1		T27	8		T35	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T8	1		T43	19		T37	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T39	5		T229	22		T20	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T2	17		T39	14		T42	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T15	1		T41	12		T56	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17245	1			T1	20		T4	133		T7	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T3	8		T144	10		T168	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T152	14		T183	10		T211	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T263	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T17	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T12	2		T37	6		T284	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T41	9		T162	10		T256	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T12	10		T42	10		T164	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T231	16		T266	9		T260	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T43	9		T147	9		T247	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T39	8		T176	12		T160	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1238	1			T2	1		T5	20		T13	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T40	18		T145	5		T228	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T3	14		T42	7		T35	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T40	12		T33	10		T143	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T51	8		T165	9		T267	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T16	5		T27	17		T214	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T56	2		T19	8		T228	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T3	13		T27	10		T35	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T43	12		T37	11		T211	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T39	11		T178	8		T232	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T2	12		T39	2		T150	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T41	8		T56	14		T191	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22194

1

T1

20

T2

21

T3

3

auto[1]

auto[0]

4078

1

T2

13

T3

35

T5

20