Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26272

1

T1

20

T2

34

T3

38

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23111

1

T1

20

T3

29

T4

133

auto[ADC_CTRL_FILTER_COND_OUT]

3161

1

T2

34

T3

9

T8

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20169

1

T1

20

T3

29

T4

129

auto[1]

6103

1

T2

34

T3

9

T4

4

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22246

1

T1

20

T2

15

T3

38

auto[1]

4026

1

T2

19

T12

14

T14

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	741	1			T4	4		T44	2		T42	12
values[0]	51	1			T160	2		T190	1		T232	17
values[1]	559	1			T3	14		T56	52		T191	3
values[2]	2992	1			T5	22		T8	1		T11	1
values[3]	687	1			T2	5		T40	19		T41	9
values[4]	669	1			T2	29		T6	1		T12	20
values[5]	677	1			T3	9		T42	3		T36	10
values[6]	753	1			T41	20		T150	25		T27	18
values[7]	728	1			T15	1		T43	31		T16	14
values[8]	693	1			T11	1		T12	8		T39	16
values[9]	958	1			T3	15		T39	16		T43	20
minimum	16764	1			T1	20		T4	129		T7	15

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	536	1			T11	1		T32	25		T33	11
values[1]	3080	1			T5	22		T8	1		T13	10
values[2]	542	1			T2	34		T39	12		T40	32
values[3]	669	1			T6	1		T12	20		T191	7
values[4]	684	1			T3	9		T42	3		T27	18
values[5]	807	1			T41	20		T150	25		T143	31
values[6]	726	1			T11	1		T15	1		T41	11
values[7]	702	1			T12	8		T39	16		T42	22
values[8]	867	1			T3	15		T39	16		T42	12
values[9]	134	1			T190	1		T231	18		T232	17
minimum	17525	1			T1	20		T3	14		T4	133

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22194

1

T1

20

T2

21

T3

3

auto[1]

4078

1

T2

13

T3

35

T5

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T11	1		T32	13		T33	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T183	1		T245	13		T314	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1622	1			T5	22		T13	10		T14	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T8	1		T41	1		T35	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T229	1		T235	1		T160	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T2	15		T39	9		T40	32
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T6	1		T12	11		T166	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T191	7		T30	1		T162	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T30	1		T51	6		T167	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T3	9		T42	3		T27	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T41	10		T154	13		T51	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T150	12		T143	15		T144	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T11	1		T15	1		T41	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T43	13		T16	11		T32	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T20	1		T210	19		T231	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T12	3		T39	3		T42	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T3	15		T39	12		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T42	8		T43	10		T17	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T190	1		T297	5		T206	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T231	18		T232	9		T170	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17209	1			T1	20		T3	14		T4	133
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T56	15		T191	3		T194	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T32	12		T35	1		T244	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T245	12		T237	8		T255	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1096	1			T14	11		T193	21		T195	25
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T41	8		T35	7		T228	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T229	7		T235	3		T160	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T2	19		T39	3		T20	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T12	9		T166	5		T236	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T261	10		T211	3		T237	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T51	2		T167	14		T168	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T27	7		T36	3		T214	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T41	10		T51	6		T176	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T150	13		T143	16		T144	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T41	2		T229	13		T228	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T43	18		T16	3		T32	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T20	1		T270	2		T287	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T12	5		T39	13		T42	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T39	4		T27	15		T19	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T42	4		T43	10		T17	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T206	1		T213	10		T96	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T232	8		T170	17		T342	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T42	2		T56	15		T17	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T56	19		T194	2		T160	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	580	1			T4	4		T44	2		T16	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T42	8		T290	3		T254	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T232	13		T243	9		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T160	1		T190	1		T227	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T3	14		T56	3		T33	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T56	15		T191	3		T194	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1601	1			T5	22		T11	1		T13	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T8	1		T35	11		T228	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T42	1		T152	15		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T2	2		T40	19		T41	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T6	1		T12	11		T166	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T2	13		T39	9		T40	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T230	1		T168	10		T318	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T3	9		T42	3		T36	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T41	10		T30	1		T154	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T150	12		T27	11		T143	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T15	1		T228	16		T176	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T43	13		T16	11		T32	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T11	1		T41	9		T229	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T12	3		T39	3		T42	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T3	15		T39	12		T152	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T43	10		T17	7		T144	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16631	1			T1	20		T4	129		T7	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T27	15		T37	9		T206	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T42	4		T290	8		T223	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T232	4		T243	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T160	1		T227	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T56	15		T244	16		T287	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T56	19		T194	2		T234	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1109	1			T14	11		T193	21		T195	25
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T35	7		T228	9		T235	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T152	13		T229	7		T166	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T2	3		T41	8		T20	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T12	9		T166	5		T235	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T2	16		T39	3		T261	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T168	7		T204	11		T186	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T36	3		T214	10		T183	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T41	10		T51	8		T167	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T150	13		T27	7		T143	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T228	11		T176	6		T178	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T43	18		T16	3		T32	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T41	2		T229	13		T20	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T12	5		T39	13		T42	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T39	4		T19	10		T147	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T43	10		T17	5		T144	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T42	2		T17	2		T35	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T11	1		T32	13		T33	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T183	1		T245	13		T314	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1436	1			T5	2		T13	1		T14	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T8	1		T41	9		T35	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T229	8		T235	4		T160	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T2	21		T39	4		T40	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T6	1		T12	10		T166	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T191	1		T30	1		T162	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T30	1		T51	3		T167	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T3	1		T42	1		T27	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T41	11		T154	1		T51	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T150	14		T143	17		T144	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T11	1		T15	1		T41	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T43	19		T16	9		T32	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T20	2		T210	1		T231	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T12	6		T39	14		T42	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T3	1		T39	5		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T42	5		T43	11		T17	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T190	1		T297	1		T206	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T231	1		T232	9		T170	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17327	1			T1	20		T3	1		T4	133
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T56	20		T191	1		T194	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T32	12		T33	10		T35	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T245	12		T314	1		T255	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1282	1			T5	20		T13	9		T152	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T35	5		T228	2		T37	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T160	13		T261	3		T282	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T2	13		T39	8		T40	30
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T12	10		T247	10		T236	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T191	6		T162	10		T261	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T51	5		T168	9		T211	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T3	8		T42	2		T27	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T41	9		T154	12		T51	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T150	11		T143	14		T236	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T41	8		T228	14		T168	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T43	12		T16	5		T32	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T210	18		T231	16		T287	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T12	2		T39	2		T42	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T3	14		T39	11		T27	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T42	7		T43	9		T17	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T297	4		T248	7		T249	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T231	17		T232	8		T343	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T3	13		T56	2		T232	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T56	14		T191	2		T227	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	561	1			T4	4		T44	2		T16	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T42	5		T290	9		T254	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T232	5		T243	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T160	2		T190	1		T227	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T3	1		T56	16		T33	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T56	20		T191	1		T194	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1451	1			T5	2		T11	1		T13	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T8	1		T35	13		T228	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T42	1		T152	14		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T2	4		T40	1		T41	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T6	1		T12	10		T166	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T2	17		T39	4		T40	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T230	1		T168	8		T318	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T3	1		T42	1		T36	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T41	11		T30	1		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T150	14		T27	8		T143	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T15	1		T228	13		T176	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T43	19		T16	9		T32	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T11	1		T41	3		T229	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T12	6		T39	14		T42	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T3	1		T39	5		T152	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T43	11		T17	9		T144	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16764	1			T1	20		T4	129		T7	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T27	17		T37	11		T297	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T42	7		T290	2		T254	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T232	12		T243	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T227	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T3	13		T56	2		T33	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T56	14		T191	2		T245	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1259	1			T5	20		T13	9		T32	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T35	5		T228	2		T291	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T152	14		T166	10		T160	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T2	1		T40	18		T20	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T12	10		T247	10		T236	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T2	12		T39	8		T40	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T168	9		T291	14		T254	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T3	8		T42	2		T36	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T41	9		T154	12		T51	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T150	11		T27	10		T143	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T228	14		T176	2		T178	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T43	12		T16	5		T32	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T41	8		T210	18		T231	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T12	2		T39	2		T42	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T3	14		T39	11		T154	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T43	9		T17	3		T144	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22194

1

T1

20

T2

21

T3

3

auto[1]

auto[0]

4078

1

T2

13

T3

35

T5

20