Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26272

1

T1

20

T2

34

T3

38

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22750

1

T1

20

T2

29

T3

15

auto[ADC_CTRL_FILTER_COND_OUT]

3522

1

T2

5

T3

23

T8

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20276

1

T1

20

T4

133

T6

1

auto[1]

5996

1

T2

34

T3

38

T5

22

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22246

1

T1

20

T2

15

T3

38

auto[1]

4026

1

T2

19

T12

14

T14

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	226	1			T191	7		T16	14		T229	8
values[0]	30	1			T24	20		T285	10		-	-
values[1]	796	1			T2	29		T11	1		T43	20
values[2]	661	1			T39	16		T27	33		T32	18
values[3]	678	1			T2	5		T12	20		T56	34
values[4]	788	1			T41	9		T152	1		T28	1
values[5]	608	1			T6	1		T39	12		T42	23
values[6]	660	1			T39	16		T40	19		T41	11
values[7]	529	1			T15	1		T42	3		T20	1
values[8]	686	1			T3	14		T11	1		T40	13
values[9]	3365	1			T3	24		T5	22		T8	1
minimum	17245	1			T1	20		T4	133		T7	15

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	708	1			T43	20		T27	18		T144	2
values[1]	671	1			T39	16		T27	33		T32	18
values[2]	677	1			T2	5		T12	20		T56	34
values[3]	722	1			T39	12		T41	9		T56	18
values[4]	660	1			T6	1		T41	11		T42	23
values[5]	572	1			T15	1		T39	16		T40	19
values[6]	2942	1			T5	22		T13	10		T14	12
values[7]	614	1			T3	29		T11	1		T40	13
values[8]	1007	1			T3	9		T8	1		T12	8
values[9]	141	1			T191	7		T35	18		T178	17
minimum	17558	1			T1	20		T2	29		T4	133

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22194

1

T1

20

T2

21

T3

3

auto[1]

4078

1

T2

13

T3

35

T5

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T144	1		T154	8		T210	19
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T43	10		T27	11		T257	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T32	11		T37	1		T38	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T39	3		T27	18		T20	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T194	1		T152	1		T144	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T2	2		T12	11		T56	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T39	9		T41	1		T20	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T56	3		T28	1		T147	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T6	1		T41	9		T42	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T42	11		T30	1		T32	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T15	1		T39	12		T42	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T40	19		T164	18		T49	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1592	1			T5	22		T13	10		T14	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T214	12		T165	10		T256	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T3	15		T40	13		T191	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T3	14		T11	1		T152	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T12	3		T153	1		T229	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T3	9		T8	1		T41	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T191	7		T178	9		T244	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T35	11		T344	1		T105	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17181	1			T1	20		T2	13		T4	133
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T11	1		T36	7		T154	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T144	1		T235	12		T261	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T43	10		T27	7		T211	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T32	7		T37	1		T38	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T39	13		T27	15		T20	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T194	2		T144	14		T37	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T2	3		T12	9		T56	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T39	3		T41	8		T20	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T56	15		T228	9		T211	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T41	2		T166	10		T176	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T42	11		T32	12		T80	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T39	4		T229	13		T228	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T164	19		T49	11		T270	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1049	1			T14	11		T42	4		T150	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T214	10		T165	2		T160	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T51	2		T166	5		T167	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T152	13		T277	2		T292	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T12	5		T229	7		T51	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T41	10		T43	18		T16	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T178	8		T244	2		T246	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T35	7		T108	9		T320	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T2	16		T42	2		T17	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T36	3		T19	10		T268	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T191	7		T229	1		T178	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T16	11		T206	1		T323	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T285	5		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T24	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T2	13		T17	7		T144	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T11	1		T43	10		T27	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T32	11		T154	8		T37	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T39	3		T27	18		T20	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T194	1		T144	11		T37	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T2	2		T12	11		T56	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T41	1		T152	1		T20	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T28	1		T158	1		T228	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T6	1		T39	9		T42	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T42	11		T56	3		T32	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T39	12		T41	9		T229	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T40	19		T30	1		T164	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T15	1		T42	3		T20	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T214	12		T165	10		T49	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T40	13		T42	8		T150	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T3	14		T11	1		T152	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1699	1			T3	15		T5	22		T12	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T3	9		T8	1		T41	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17112	1			T1	20		T4	133		T7	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T229	7		T178	8		T246	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T16	3		T206	1		T323	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T285	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T24	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T2	16		T17	5		T144	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T43	10		T27	7		T36	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T32	7		T37	1		T38	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T39	13		T27	15		T20	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T194	2		T144	14		T37	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T2	3		T12	9		T56	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T41	8		T20	2		T183	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T228	9		T178	17		T211	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T39	3		T166	10		T176	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T42	11		T56	15		T32	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T39	4		T41	2		T229	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T164	19		T251	17		T299	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T244	4		T270	3		T252	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T214	10		T165	2		T49	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T42	4		T150	13		T51	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T152	13		T279	12		T115	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1109	1			T12	5		T14	11		T193	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T41	10		T43	18		T143	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T42	2		T17	2		T35	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T144	2		T154	1		T210	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T43	11		T27	8		T257	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T32	8		T37	2		T38	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T39	14		T27	16		T20	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T194	3		T152	1		T144	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T2	4		T12	10		T56	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T39	4		T41	9		T20	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T56	16		T28	1		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T6	1		T41	3		T42	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T42	12		T30	1		T32	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T15	1		T39	5		T42	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T40	1		T164	20		T49	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1379	1			T5	2		T13	1		T14	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T214	11		T165	3		T256	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T3	1		T40	1		T191	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T3	1		T11	1		T152	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T12	6		T153	1		T229	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T3	1		T8	1		T41	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T191	1		T178	9		T244	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T35	13		T344	1		T105	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17332	1			T1	20		T2	17		T4	133
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T11	1		T36	6		T154	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T154	7		T210	18		T261	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T43	9		T27	10		T211	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T32	10		T38	4		T236	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T39	2		T27	17		T228	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T144	10		T37	6		T231	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T2	1		T12	10		T56	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T39	8		T20	2		T37	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T56	2		T147	9		T228	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T41	8		T166	10		T176	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T42	10		T32	12		T251	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T39	11		T42	2		T228	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T40	18		T164	17		T247	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1262	1			T5	20		T13	9		T42	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T214	11		T165	9		T256	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T3	14		T40	12		T191	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T3	13		T152	14		T297	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T12	2		T51	8		T168	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T3	8		T41	9		T43	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T191	6		T178	8		T246	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T35	5		T105	4		T108	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T2	12		T17	3		T176	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T36	4		T154	12		T19	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T191	1		T229	8		T178	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T16	9		T206	2		T323	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T285	6		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T24	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T2	17		T17	9		T144	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T11	1		T43	11		T27	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T32	8		T154	1		T37	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T39	14		T27	16		T20	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T194	3		T144	15		T37	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T2	4		T12	10		T56	20
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T41	9		T152	1		T20	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T28	1		T158	1		T228	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T6	1		T39	4		T42	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T42	12		T56	16		T32	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T39	5		T41	3		T229	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T40	1		T30	1		T164	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T15	1		T42	1		T20	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T214	11		T165	3		T49	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T40	1		T42	5		T150	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T3	1		T11	1		T152	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1460	1			T3	1		T5	2		T12	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	347	1			T3	1		T8	1		T41	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17245	1			T1	20		T4	133		T7	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T191	6		T178	8		T246	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T16	5		T345	17		T105	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T285	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T24	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T2	12		T17	3		T210	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T43	9		T27	10		T36	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T32	10		T154	7		T38	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T39	2		T27	17		T228	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T144	10		T37	6		T236	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T2	1		T12	10		T56	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T20	2		T183	10		T266	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T228	9		T178	20		T231	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T39	8		T166	10		T176	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T42	10		T56	2		T32	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T39	11		T41	8		T228	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T40	18		T164	17		T247	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T42	2		T244	10		T269	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T214	11		T165	9		T160	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T40	12		T42	7		T150	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T3	13		T152	14		T256	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1348	1			T3	14		T5	20		T12	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T3	8		T41	9		T43	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22194

1

T1

20

T2

21

T3

3

auto[1]

auto[0]

4078

1

T2

13

T3

35

T5

20