Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26272

1

T1

20

T2

34

T3

38

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22702

1

T1

20

T2

34

T3

23

auto[ADC_CTRL_FILTER_COND_OUT]

3570

1

T3

15

T8

1

T11

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20232

1

T1

20

T2

34

T3

24

auto[1]

6040

1

T3

14

T5

22

T12

28

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22246

1

T1

20

T2

15

T3

38

auto[1]

4026

1

T2

19

T12

14

T14

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	310	1			T41	20		T210	19		T166	21
values[0]	65	1			T164	37		T201	28		-	-
values[1]	489	1			T39	28		T40	13		T191	7
values[2]	2798	1			T5	22		T12	8		T13	10
values[3]	578	1			T41	9		T42	1		T143	31
values[4]	645	1			T42	22		T30	1		T35	18
values[5]	728	1			T2	5		T8	1		T12	20
values[6]	819	1			T3	15		T43	20		T56	34
values[7]	863	1			T3	14		T42	12		T150	25
values[8]	694	1			T3	9		T16	14		T228	12
values[9]	1038	1			T2	29		T6	1		T11	2
minimum	17245	1			T1	20		T4	133		T7	15

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	460	1			T39	28		T191	7		T30	1
values[1]	2750	1			T5	22		T12	8		T13	10
values[2]	696	1			T41	9		T42	1		T30	1
values[3]	662	1			T42	22		T194	3		T35	18
values[4]	781	1			T8	1		T12	20		T41	11
values[5]	804	1			T2	5		T3	29		T56	34
values[6]	746	1			T3	9		T42	12		T150	25
values[7]	775	1			T15	1		T40	19		T228	12
values[8]	997	1			T2	29		T6	1		T11	2
values[9]	149	1			T210	19		T230	1		T160	31
minimum	17452	1			T1	20		T4	133		T7	15

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22194

1

T1

20

T2

21

T3

3

auto[1]

4078

1

T2

13

T3

35

T5

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T191	7		T20	4		T214	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T39	12		T30	1		T33	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1465	1			T5	22		T12	3		T13	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T229	1		T51	9		T37	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T143	15		T51	6		T37	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T41	1		T42	1		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T194	1		T35	11		T236	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T42	11		T144	1		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T12	11		T42	3		T43	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T8	1		T41	9		T56	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T2	2		T3	14		T36	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T3	15		T56	15		T27	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T3	9		T42	8		T16	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T150	12		T191	3		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T15	1		T228	3		T165	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T40	19		T167	1		T168	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T2	13		T6	1		T39	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T11	2		T153	1		T20	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T230	1		T160	14		T114	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T210	19		T318	1		T241	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17148	1			T1	20		T4	133		T7	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T40	13		T17	7		T38	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T20	2		T214	10		T164	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T39	16		T50	3		T22	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	999	1			T12	5		T14	11		T193	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T229	13		T51	6		T37	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T143	16		T51	2		T37	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T41	8		T19	10		T155	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T194	2		T35	7		T236	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T42	11		T144	1		T161	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T12	9		T43	10		T152	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T41	2		T56	15		T228	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T2	3		T36	3		T37	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T56	19		T27	7		T147	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T42	4		T16	3		T27	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T150	13		T176	6		T161	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T228	9		T165	2		T235	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T167	14		T168	7		T302	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T2	16		T39	4		T41	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T166	10		T235	3		T251	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T160	17		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T245	12		T325	16		T311	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T42	2		T17	2		T35	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T17	5		T38	4		T346	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T41	10		T160	14		T261	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T210	19		T166	11		T182	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T164	18		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T201	19		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T191	7		T20	4		T214	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T39	12		T40	13		T30	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1457	1			T5	22		T12	3		T13	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T33	11		T229	1		T51	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T143	15		T51	6		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T41	1		T42	1		T18	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T35	11		T37	7		T236	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T42	11		T30	1		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T2	2		T12	11		T42	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T8	1		T41	9		T56	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T43	10		T147	10		T178	21
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T3	15		T56	15		T27	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T3	14		T42	8		T27	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T150	12		T191	3		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T3	9		T16	11		T228	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T167	1		T168	10		T298	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T2	13		T6	1		T15	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T11	2		T40	19		T153	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17112	1			T1	20		T4	133		T7	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T41	10		T160	17		T261	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T166	10		T232	8		T245	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T164	19		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T201	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T20	2		T214	10		T161	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T39	16		T17	5		T38	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1008	1			T12	5		T14	11		T193	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T229	13		T51	6		T37	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T143	16		T51	2		T206	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T41	8		T19	10		T155	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T35	7		T37	6		T236	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T42	11		T144	1		T161	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T2	3		T12	9		T194	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T41	2		T56	15		T228	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T43	10		T178	17		T168	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T56	19		T27	7		T147	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T42	4		T27	15		T36	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T150	13		T176	6		T161	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T16	3		T228	9		T165	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T167	14		T168	7		T23	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T2	16		T39	4		T43	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T235	3		T251	17		T245	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T42	2		T17	2		T35	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T191	1		T20	4		T214	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T39	18		T30	1		T33	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1330	1			T5	2		T12	6		T13	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T229	14		T51	7		T37	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T143	17		T51	3		T37	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T41	9		T42	1		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T194	3		T35	13		T236	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T42	12		T144	2		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T12	10		T42	1		T43	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T8	1		T41	3		T56	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T2	4		T3	1		T36	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T3	1		T56	20		T27	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T3	1		T42	5		T16	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T150	14		T191	1		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T15	1		T228	10		T165	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T40	1		T167	15		T168	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	320	1			T2	17		T6	1		T39	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T11	2		T153	1		T20	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T230	1		T160	18		T114	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T210	1		T318	1		T241	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17280	1			T1	20		T4	133		T7	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T40	1		T17	9		T38	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T191	6		T20	2		T214	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T39	10		T33	10		T22	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1134	1			T5	20		T12	2		T13	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T51	8		T247	15		T169	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T143	14		T51	5		T37	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T19	8		T176	12		T244	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T35	5		T236	16		T113	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T42	10		T261	11		T267	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T12	10		T42	2		T43	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T41	8		T56	2		T162	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T2	1		T3	13		T36	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T3	14		T56	14		T27	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T3	8		T42	7		T16	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T150	11		T191	2		T154	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T228	2		T165	9		T290	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T40	18		T168	9		T298	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T2	12		T39	11		T41	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T166	10		T251	15		T232	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T160	13		T263	12		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T210	18		T245	12		T325	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T280	6		T299	3		T115	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T40	12		T17	3		T38	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T41	11		T160	18		T261	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T210	1		T166	11		T182	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T164	20		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T201	10		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T191	1		T20	4		T214	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T39	18		T40	1		T30	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1333	1			T5	2		T12	6		T13	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T33	1		T229	14		T51	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T143	17		T51	3		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T41	9		T42	1		T18	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T35	13		T37	7		T236	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T42	12		T30	1		T144	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T2	4		T12	10		T42	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T8	1		T41	3		T56	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T43	11		T147	1		T178	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T3	1		T56	20		T27	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T3	1		T42	5		T27	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T150	14		T191	1		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T3	1		T16	9		T228	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T167	15		T168	8		T298	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	329	1			T2	17		T6	1		T15	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T11	2		T40	1		T153	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17245	1			T1	20		T4	133		T7	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T41	9		T160	13		T261	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T210	18		T166	10		T232	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T164	17		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T201	18		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T191	6		T20	2		T214	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T39	10		T40	12		T17	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1132	1			T5	20		T12	2		T13	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T33	10		T51	8		T247	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T143	14		T51	5		T297	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T19	8		T176	12		T244	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T35	5		T37	6		T236	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T42	10		T261	11		T267	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T2	1		T12	10		T42	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T41	8		T56	2		T162	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T43	9		T147	9		T178	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T3	14		T56	14		T27	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T3	13		T42	7		T27	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T150	11		T191	2		T154	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T3	8		T16	5		T228	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T168	9		T298	4		T23	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T2	12		T39	11		T43	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T40	18		T251	15		T245	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22194

1

T1

20

T2

21

T3

3

auto[1]

auto[0]

4078

1

T2

13

T3

35

T5

20