Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	333	1			T12	6		T155	1		T164	20
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T41	11		T17	9		T256	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T12	10		T42	12		T194	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T30	1		T162	1		T176	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T6	1		T42	1		T43	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T39	4		T49	12		T257	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1387	1			T2	4		T5	2		T13	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T40	1		T30	1		T33	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T3	1		T28	1		T35	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T16	9		T27	16		T143	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T56	16		T153	1		T51	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T3	1		T40	1		T35	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T11	1		T19	17		T228	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T39	5		T27	8		T36	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T8	1		T43	19		T37	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T41	3		T20	2		T178	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T11	1		T42	1		T150	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	350	1			T15	1		T41	9		T56	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T2	17		T3	1		T39	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T191	1		T158	1		T168	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17258	1			T1	20		T4	133		T7	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T168	8		T258	17		T259	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T12	2		T164	17		T37	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T41	9		T17	3		T256	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T12	10		T42	10		T176	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T162	10		T176	12		T160	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T42	2		T43	9		T147	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T39	8		T49	12		T169	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1232	1			T2	1		T5	20		T13	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T40	18		T33	10		T145	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T3	14		T35	1		T154	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T16	5		T27	17		T143	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T56	2		T51	8		T267	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T3	13		T40	12		T35	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T19	8		T228	2		T178	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T39	11		T27	10		T36	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T43	12		T37	11		T247	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T41	8		T178	8		T268	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T150	11		T20	2		T166	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T56	14		T191	2		T152	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T2	12		T3	8		T39	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T191	6		T168	6		T262	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T185	12		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T168	9		T258	6		T259	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T263	1		T264	12		T265	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T17	9		T254	1		T255	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T12	6		T155	1		T37	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T41	11		T162	1		T256	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T42	12		T18	1		T164	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T231	1		T161	12		T50	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T12	10		T43	11		T194	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T39	4		T30	1		T176	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1363	1			T2	4		T5	2		T6	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T40	1		T30	1		T145	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T3	1		T42	5		T28	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T40	1		T33	1		T143	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T51	7		T163	1		T165	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T16	9		T27	16		T144	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T11	1		T56	16		T153	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T3	1		T27	8		T35	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T8	1		T43	19		T37	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T39	5		T229	22		T20	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T2	17		T3	1		T11	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	419	1			T15	1		T41	12		T56	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17245	1			T1	20		T4	133		T7	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T263	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T17	3		T254	12		T255	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T12	2		T37	6		T269	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T41	9		T162	10		T256	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T42	10		T164	17		T176	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T231	16		T266	9		T260	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T12	10		T43	9		T147	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T39	8		T176	12		T160	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1277	1			T2	1		T5	20		T13	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T40	18		T145	5		T228	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T3	14		T42	7		T35	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T40	12		T33	10		T143	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T51	8		T165	9		T267	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T16	5		T27	17		T214	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T56	2		T19	8		T228	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T3	13		T27	10		T35	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T43	12		T37	11		T211	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T39	11		T178	8		T232	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T2	12		T3	8		T39	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T41	8		T56	14		T191	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22194

1

T1

20

T2

21

T3

3

auto[1]

auto[0]

4078

1

T2

13

T3

35

T5

20