Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26272

1

T1

20

T2

34

T3

38

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20738

1

T1

20

T2

34

T3

29

auto[ADC_CTRL_FILTER_COND_OUT]

5534

1

T3

9

T5

22

T6

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20077

1

T1

20

T2

29

T3

23

auto[1]

6195

1

T2

5

T3

15

T5

22

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22246

1

T1

20

T2

15

T3

38

auto[1]

4026

1

T2

19

T12

14

T14

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	13	1			T154	13		-	-		-	-
values[0]	32	1			T30	1		T270	12		T271	12
values[1]	514	1			T12	20		T15	1		T154	8
values[2]	721	1			T2	29		T39	12		T41	11
values[3]	808	1			T56	34		T16	14		T30	1
values[4]	601	1			T19	25		T51	8		T155	1
values[5]	786	1			T3	9		T6	1		T8	1
values[6]	605	1			T36	10		T51	15		T165	12
values[7]	872	1			T3	29		T11	1		T39	16
values[8]	689	1			T11	1		T12	8		T40	19
values[9]	3386	1			T2	5		T5	22		T13	10
minimum	17245	1			T1	20		T4	133		T7	15

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	709	1			T15	1		T41	11		T30	1
values[1]	2925	1			T2	29		T5	22		T12	20
values[2]	842	1			T28	1		T17	12		T32	25
values[3]	645	1			T191	3		T155	1		T210	19
values[4]	794	1			T3	9		T6	1		T8	1
values[5]	665	1			T3	14		T41	20		T35	18
values[6]	730	1			T3	15		T11	2		T39	16
values[7]	806	1			T12	8		T42	12		T150	25
values[8]	757	1			T2	5		T39	16		T40	19
values[9]	125	1			T152	1		T166	21		T168	16
minimum	17274	1			T1	20		T4	133		T7	15

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22194

1

T1

20

T2

21

T3

3

auto[1]

4078

1

T2

13

T3

35

T5

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T41	9		T18	1		T157	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T15	1		T30	1		T154	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T2	13		T12	11		T39	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1526	1			T5	22		T13	10		T14	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	346	1			T17	7		T32	13		T162	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T28	1		T51	6		T176	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T191	3		T228	10		T166	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T155	1		T210	19		T228	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T8	1		T43	13		T56	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T3	9		T6	1		T143	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T3	14		T37	4		T182	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T41	10		T35	11		T145	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T3	15		T11	1		T32	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T11	1		T39	12		T40	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T12	3		T150	12		T153	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T42	8		T27	18		T20	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T2	2		T40	19		T43	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T39	3		T41	1		T42	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T166	11		T168	7		T261	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T152	1		T161	1		T272	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17113	1			T1	20		T4	133		T7	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T273	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T41	2		T161	11		T211	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T37	6		T261	4		T240	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T2	16		T12	9		T39	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1032	1			T14	11		T56	19		T193	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T17	5		T32	12		T144	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T51	2		T176	12		T37	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T228	9		T166	5		T168	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T228	9		T160	17		T274	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T43	18		T56	15		T36	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T143	16		T51	6		T178	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T37	2		T80	6		T275	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T41	10		T35	7		T145	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T32	7		T168	1		T160	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T39	4		T27	7		T20	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T12	5		T150	13		T214	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T42	4		T27	15		T20	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T2	3		T43	10		T194	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T39	13		T41	8		T42	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T166	10		T168	9		T261	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T161	6		T276	2		T252	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T42	2		T17	2		T35	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T273	13		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T154	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T270	1		T271	7		T277	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T30	1		T24	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T12	11		T157	2		T230	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T15	1		T154	8		T37	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T2	13		T39	9		T41	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T42	1		T191	7		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T30	1		T32	13		T162	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T56	15		T16	11		T176	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T19	15		T147	10		T166	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T51	6		T155	1		T210	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T8	1		T43	13		T56	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T3	9		T6	1		T143	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T36	7		T235	1		T231	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T51	9		T165	10		T230	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T3	29		T11	1		T32	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T39	12		T40	13		T41	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T12	3		T40	19		T150	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T11	1		T42	8		T27	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	362	1			T2	2		T43	10		T194	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1643	1			T5	22		T13	10		T14	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17112	1			T1	20		T4	133		T7	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T270	11		T271	5		T277	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T12	9		T161	11		T245	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T37	6		T261	4		T240	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T2	16		T39	3		T41	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T155	12		T278	12		T279	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T32	12		T144	1		T229	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T56	19		T16	3		T176	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T19	10		T166	5		T49	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T51	2		T228	9		T37	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T43	18		T56	15		T228	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T143	16		T178	8		T160	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T36	3		T235	3		T80	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T51	6		T165	2		T80	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T32	7		T37	2		T168	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T39	4		T41	10		T27	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T12	5		T150	13		T214	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T42	4		T27	15		T232	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T2	3		T43	10		T194	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1112	1			T14	11		T39	13		T41	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T42	2		T17	2		T35	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T41	3		T18	1		T157	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T15	1		T30	1		T154	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T2	17		T12	10		T39	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1368	1			T5	2		T13	1		T14	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T17	9		T32	13		T162	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T28	1		T51	3		T176	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T191	1		T228	10		T166	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T155	1		T210	1		T228	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T8	1		T43	19		T56	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T3	1		T6	1		T143	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T3	1		T37	5		T182	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T41	11		T35	13		T145	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T3	1		T11	1		T32	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T11	1		T39	5		T40	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T12	6		T150	14		T153	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T42	5		T27	16		T20	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T2	4		T40	1		T43	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T39	14		T41	9		T42	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T166	11		T168	10		T261	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T152	1		T161	7		T272	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17257	1			T1	20		T4	133		T7	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T273	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T41	8		T157	1		T211	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T154	7		T37	6		T261	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T2	12		T12	10		T39	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1190	1			T5	20		T13	9		T56	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T17	3		T32	12		T162	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T51	5		T176	12		T247	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T191	2		T228	9		T168	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T210	18		T228	2		T160	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T43	12		T56	2		T36	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T3	8		T143	14		T51	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T3	13		T37	1		T231	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T41	9		T35	5		T145	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T3	14		T32	10		T168	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T39	11		T40	12		T27	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T12	2		T150	11		T214	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T42	7		T27	17		T280	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T2	1		T40	18		T43	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T39	2		T42	12		T144	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T166	10		T168	6		T261	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T276	1		T252	9		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T273	3		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T154	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T270	12		T271	6		T277	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T30	1		T24	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T12	10		T157	1		T230	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T15	1		T154	1		T37	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T2	17		T39	4		T41	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T42	1		T191	1		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T30	1		T32	13		T162	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T56	20		T16	9		T176	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T19	17		T147	1		T166	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T51	3		T155	1		T210	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T8	1		T43	19		T56	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T3	1		T6	1		T143	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T36	6		T235	4		T231	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T51	7		T165	3		T230	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T3	2		T11	1		T32	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T39	5		T40	1		T41	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T12	6		T40	1		T150	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T11	1		T42	5		T27	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	347	1			T2	4		T43	11		T194	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1459	1			T5	2		T13	1		T14	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17245	1			T1	20		T4	133		T7	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T154	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T271	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T12	10		T157	1		T245	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T154	7		T37	6		T261	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T2	12		T39	8		T41	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T191	6		T281	4		T278	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T32	12		T162	10		T164	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T56	14		T16	5		T176	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T19	8		T147	9		T168	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T51	5		T210	18		T228	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T43	12		T56	2		T191	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T3	8		T143	14		T178	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T36	4		T231	16		T282	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T51	8		T165	9		T169	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T3	27		T32	10		T37	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T39	11		T40	12		T41	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T12	2		T40	18		T150	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T42	7		T27	17		T247	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T2	1		T43	9		T152	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1296	1			T5	20		T13	9		T39	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22194

1

T1

20

T2

21

T3

3

auto[1]

auto[0]

4078

1

T2

13

T3

35

T5

20