Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26272

1

T1

20

T2

34

T3

38

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22700

1

T1

20

T2

29

T3

15

auto[ADC_CTRL_FILTER_COND_OUT]

3572

1

T2

5

T3

23

T8

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20346

1

T1

20

T3

9

T4

133

auto[1]

5926

1

T2

34

T3

29

T5

22

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22246

1

T1

20

T2

15

T3

38

auto[1]

4026

1

T2

19

T12

14

T14

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	15	1			T209	15		-	-		-	-
values[0]	76	1			T154	13		T283	1		T24	20
values[1]	693	1			T2	29		T11	1		T43	20
values[2]	711	1			T39	16		T194	3		T27	33
values[3]	732	1			T2	5		T12	20		T56	34
values[4]	743	1			T39	12		T41	9		T152	1
values[5]	585	1			T6	1		T42	23		T56	18
values[6]	653	1			T39	16		T40	19		T41	11
values[7]	576	1			T15	1		T42	3		T20	1
values[8]	682	1			T3	14		T11	1		T40	13
values[9]	3561	1			T3	24		T5	22		T8	1
minimum	17245	1			T1	20		T4	133		T7	15

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1001	1			T2	29		T43	20		T27	18
values[1]	720	1			T39	16		T27	33		T32	18
values[2]	633	1			T2	5		T12	20		T56	34
values[3]	743	1			T39	12		T41	9		T42	1
values[4]	642	1			T6	1		T41	11		T42	22
values[5]	576	1			T15	1		T39	16		T40	19
values[6]	2982	1			T5	22		T13	10		T14	12
values[7]	536	1			T3	38		T11	1		T191	3
values[8]	977	1			T8	1		T12	8		T41	20
values[9]	216	1			T191	7		T35	18		T157	2
minimum	17246	1			T1	20		T4	133		T7	15

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22194

1

T1

20

T2

21

T3

3

auto[1]

4078

1

T2

13

T3

35

T5

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T2	13		T17	7		T144	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T43	10		T27	11		T36	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T32	11		T37	1		T38	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T39	3		T27	18		T20	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T194	1		T152	1		T144	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T2	2		T12	11		T56	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T39	9		T41	1		T42	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T56	3		T28	1		T147	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T6	1		T41	9		T176	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T42	11		T30	1		T32	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T15	1		T39	12		T42	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T40	19		T164	18		T49	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1604	1			T5	22		T13	10		T14	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T214	12		T165	10		T183	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T3	15		T191	3		T162	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T3	23		T11	1		T30	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T12	3		T153	1		T229	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T8	1		T41	10		T43	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T191	7		T178	9		T244	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T35	11		T157	2		T236	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17112	1			T1	20		T4	133		T7	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T11	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T2	16		T17	5		T144	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T43	10		T27	7		T36	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T32	7		T37	1		T38	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T39	13		T27	15		T20	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T194	2		T144	14		T37	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T2	3		T12	9		T56	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T39	3		T41	8		T20	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T56	15		T228	9		T80	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T41	2		T176	12		T37	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T42	11		T32	12		T166	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T39	4		T229	13		T228	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T164	19		T49	11		T270	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1071	1			T14	11		T42	4		T150	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T214	10		T165	2		T160	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T166	5		T235	9		T284	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T51	2		T277	2		T115	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T12	5		T229	7		T51	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T41	10		T43	18		T152	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T178	8		T244	2		T232	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T35	7		T236	13		T108	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T42	2		T17	2		T35	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T209	5		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T283	1		T113	11		T285	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T154	13		T24	11		T286	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T2	13		T17	7		T144	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T11	1		T43	10		T27	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T194	1		T154	8		T37	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T39	3		T27	18		T20	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T32	11		T144	11		T37	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T2	2		T12	11		T56	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T39	9		T41	1		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T28	1		T158	1		T228	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T6	1		T42	1		T37	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T42	11		T56	3		T30	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T39	12		T41	9		T229	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T40	19		T164	18		T165	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T15	1		T42	3		T20	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T214	12		T49	1		T183	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T40	13		T42	8		T150	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T3	14		T11	1		T152	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1773	1			T3	15		T5	22		T12	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T3	9		T8	1		T41	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17112	1			T1	20		T4	133		T7	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T209	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T285	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T24	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T2	16		T17	5		T144	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T43	10		T27	7		T36	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T194	2		T37	1		T38	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T39	13		T27	15		T20	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T32	7		T144	14		T37	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T2	3		T12	9		T56	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T39	3		T41	8		T20	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T228	9		T238	11		T287	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T37	11		T161	6		T80	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T42	11		T56	15		T32	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T39	4		T41	2		T229	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T164	19		T165	2		T251	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T244	4		T270	3		T171	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T214	10		T49	11		T160	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T42	4		T150	13		T51	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T152	13		T35	1		T51	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1172	1			T12	5		T14	11		T193	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T41	10		T43	18		T16	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T42	2		T17	2		T35	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T2	17		T17	9		T144	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T43	11		T27	8		T36	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T32	8		T37	2		T38	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T39	14		T27	16		T20	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T194	3		T152	1		T144	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T2	4		T12	10		T56	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T39	4		T41	9		T42	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T56	16		T28	1		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T6	1		T41	3		T176	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T42	12		T30	1		T32	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T15	1		T39	5		T42	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T40	1		T164	20		T49	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1404	1			T5	2		T13	1		T14	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T214	11		T165	3		T183	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T3	1		T191	1		T162	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T3	2		T11	1		T30	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T12	6		T153	1		T229	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T8	1		T41	11		T43	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T191	1		T178	9		T244	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T35	13		T157	1		T236	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17245	1			T1	20		T4	133		T7	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T11	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T2	12		T17	3		T154	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T43	9		T27	10		T36	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T32	10		T38	4		T236	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T39	2		T27	17		T228	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T144	10		T37	6		T231	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T2	1		T12	10		T56	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T39	8		T20	2		T37	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T56	2		T147	9		T228	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T41	8		T176	12		T37	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T42	10		T32	12		T166	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T39	11		T42	2		T228	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T40	18		T164	17		T247	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1271	1			T5	20		T13	9		T40	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T214	11		T165	9		T160	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T3	14		T191	2		T162	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T3	21		T33	10		T51	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T12	2		T51	8		T168	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T41	9		T43	12		T152	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T191	6		T178	8		T232	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T35	5		T157	1		T236	16

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T209	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T283	1		T113	1		T285	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T154	1		T24	12		T286	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T2	17		T17	9		T144	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T11	1		T43	11		T27	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T194	3		T154	1		T37	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T39	14		T27	16		T20	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T32	8		T144	15		T37	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T2	4		T12	10		T56	20
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T39	4		T41	9		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T28	1		T158	1		T228	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T6	1		T42	1		T37	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T42	12		T56	16		T30	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T39	5		T41	3		T229	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T40	1		T164	20		T165	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T15	1		T42	1		T20	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T214	11		T49	12		T183	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T40	1		T42	5		T150	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T3	1		T11	1		T152	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1538	1			T3	1		T5	2		T12	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	372	1			T3	1		T8	1		T41	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17245	1			T1	20		T4	133		T7	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T209	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T113	10		T285	4		T288	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T154	12		T24	8		T289	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T2	12		T17	3		T210	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T43	9		T27	10		T36	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T154	7		T38	4		T245	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T39	2		T27	17		T49	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T32	10		T144	10		T37	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T2	1		T12	10		T56	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T39	8		T20	2		T183	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T228	9		T231	17		T238	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T37	12		T267	14		T290	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T42	10		T56	2		T32	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T39	11		T41	8		T228	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T40	18		T164	17		T165	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T42	2		T244	10		T269	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T214	11		T160	13		T291	23
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T40	12		T42	7		T150	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T3	13		T152	14		T35	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1407	1			T3	14		T5	20		T12	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T3	8		T41	9		T43	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22194

1

T1

20

T2

21

T3

3

auto[1]

auto[0]

4078

1

T2

13

T3

35

T5

20