Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26272

1

T1

20

T2

34

T3

38

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22993

1

T1

20

T2

34

T3

23

auto[ADC_CTRL_FILTER_COND_OUT]

3279

1

T3

15

T6

1

T8

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20328

1

T1

20

T3

9

T4

133

auto[1]

5944

1

T2

34

T3

29

T5

22

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22246

1

T1

20

T2

15

T3

38

auto[1]

4026

1

T2

19

T12

14

T14

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	22	1			T292	22		-	-		-	-
values[0]	67	1			T41	20		T56	18		T232	17
values[1]	802	1			T40	13		T152	28		T32	43
values[2]	693	1			T2	34		T11	2		T39	16
values[3]	625	1			T12	28		T42	1		T163	1
values[4]	804	1			T3	14		T8	1		T41	11
values[5]	2858	1			T3	9		T5	22		T13	10
values[6]	486	1			T15	1		T42	12		T191	7
values[7]	765	1			T6	1		T43	31		T56	34
values[8]	565	1			T42	3		T194	3		T27	33
values[9]	1340	1			T3	15		T39	12		T40	19
minimum	17245	1			T1	20		T4	133		T7	15

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1106	1			T2	29		T41	20		T56	18
values[1]	569	1			T2	5		T11	2		T39	16
values[2]	797	1			T3	14		T12	28		T43	20
values[3]	2915	1			T5	22		T13	10		T14	12
values[4]	552	1			T3	9		T8	1		T39	16
values[5]	608	1			T15	1		T152	1		T27	18
values[6]	764	1			T6	1		T42	12		T43	31
values[7]	527	1			T3	15		T42	3		T194	3
values[8]	951	1			T39	12		T40	19		T143	31
values[9]	214	1			T20	1		T146	1		T164	37
minimum	17269	1			T1	20		T4	133		T7	15

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22194

1

T1

20

T2

21

T3

3

auto[1]

4078

1

T2

13

T3

35

T5

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T2	13		T41	10		T56	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T32	24		T144	11		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T2	2		T39	12		T42	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T11	2		T42	1		T182	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T3	14		T12	11		T16	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T12	3		T43	10		T150	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1496	1			T5	22		T13	10		T14	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T36	7		T20	1		T182	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T3	9		T39	3		T191	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T8	1		T41	1		T191	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T15	1		T152	1		T27	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T182	1		T49	14		T87	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T42	8		T56	15		T27	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T6	1		T43	13		T35	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T42	3		T194	1		T35	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T3	15		T30	1		T19	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T39	9		T40	19		T143	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T153	1		T51	9		T155	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T146	1		T230	1		T257	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T20	1		T164	18		T190	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17113	1			T1	20		T4	133		T7	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T40	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T2	16		T41	10		T56	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T32	19		T144	14		T155	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T2	3		T39	4		T42	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T168	7		T169	16		T293	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T12	9		T16	3		T37	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T12	5		T43	10		T150	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	996	1			T14	11		T41	2		T193	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T36	3		T20	1		T235	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T39	13		T17	5		T235	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T41	8		T80	2		T287	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T27	7		T145	5		T166	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T49	11		T245	14		T294	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T42	4		T56	19		T27	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T43	18		T35	7		T144	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T194	2		T35	1		T51	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T19	10		T167	14		T244	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T39	3		T143	16		T214	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T51	6		T244	2		T268	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T238	11		T234	6		T118	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T164	19		T80	9		T295	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T42	2		T17	2		T35	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T292	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T41	10		T56	3		T232	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T296	9		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T152	15		T158	1		T37	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T40	13		T32	24		T144	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T2	15		T39	12		T42	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T11	2		T182	1		T247	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T12	11		T210	19		T176	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T12	3		T42	1		T163	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T3	14		T41	9		T16	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T8	1		T43	10		T150	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1471	1			T3	9		T5	22		T13	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T41	1		T36	7		T236	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T15	1		T42	8		T27	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T191	7		T49	13		T160	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T56	15		T28	1		T162	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T6	1		T43	13		T35	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T42	3		T194	1		T27	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T30	1		T144	1		T178	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	386	1			T39	9		T40	19		T143	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	389	1			T3	15		T153	1		T19	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17112	1			T1	20		T4	133		T7	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T292	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T41	10		T56	15		T232	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T152	13		T37	6		T183	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T32	19		T144	14		T155	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T2	19		T39	4		T42	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T168	7		T261	10		T232	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T12	9		T176	18		T37	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T12	5		T165	2		T287	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T41	2		T16	3		T37	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T43	10		T150	13		T20	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1023	1			T14	11		T39	13		T193	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T41	8		T36	3		T236	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T42	4		T27	7		T80	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T49	11		T160	1		T245	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T56	19		T35	1		T145	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T43	18		T35	7		T229	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T194	2		T27	15		T51	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T144	1		T178	8		T167	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T39	3		T143	16		T214	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T19	10		T51	6		T164	19
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T42	2		T17	2		T35	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	325	1			T2	17		T41	11		T56	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T32	21		T144	15		T155	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T2	4		T39	5		T42	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T11	2		T42	1		T182	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T3	1		T12	10		T16	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T12	6		T43	11		T150	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1325	1			T5	2		T13	1		T14	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T36	6		T20	2		T182	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T3	1		T39	14		T191	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T8	1		T41	9		T191	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T15	1		T152	1		T27	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T182	1		T49	13		T87	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T42	5		T56	20		T27	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T6	1		T43	19		T35	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T42	1		T194	3		T35	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T3	1		T30	1		T19	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T39	4		T40	1		T143	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T153	1		T51	7		T155	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T146	1		T230	1		T257	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T20	1		T164	20		T190	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17256	1			T1	20		T4	133		T7	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T40	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T2	12		T41	9		T56	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T32	22		T144	10		T147	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T2	1		T39	11		T42	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T247	10		T168	9		T267	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T3	13		T12	10		T16	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T12	2		T43	9		T150	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1167	1			T5	20		T13	9		T41	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T36	4		T236	7		T168	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T3	8		T39	2		T191	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T191	6		T297	11		T212	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T27	10		T145	5		T166	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T49	12		T245	12		T281	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T42	7		T56	14		T27	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T43	12		T35	5		T178	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T42	2		T35	1		T51	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T3	14		T19	8		T244	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T39	8		T40	18		T143	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T51	8		T298	4		T268	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T238	12		T118	3		T285	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T164	17		T269	13		T185	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T40	12		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T292	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T41	11		T56	16		T232	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T296	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T152	14		T158	1		T37	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T40	1		T32	21		T144	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T2	21		T39	5		T42	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T11	2		T182	1		T247	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T12	10		T210	1		T176	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T12	6		T42	1		T163	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T3	1		T41	3		T16	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T8	1		T43	11		T150	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1353	1			T3	1		T5	2		T13	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T41	9		T36	6		T236	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T15	1		T42	5		T27	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T191	1		T49	12		T160	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T56	20		T28	1		T162	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T6	1		T43	19		T35	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T42	1		T194	3		T27	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T30	1		T144	2		T178	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	346	1			T39	4		T40	1		T143	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	376	1			T3	1		T153	1		T19	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17245	1			T1	20		T4	133		T7	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T292	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T41	9		T56	2		T232	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T296	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T152	14		T37	6		T247	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T40	12		T32	22		T144	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T2	13		T39	11		T42	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T247	10		T168	9		T261	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T12	10		T210	18		T176	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T12	2		T165	9		T287	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T3	13		T41	8		T16	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T43	9		T150	11		T168	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1141	1			T3	8		T5	20		T13	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T36	4		T236	7		T168	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T42	7		T27	10		T299	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T191	6		T49	12		T245	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T56	14		T162	10		T35	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T43	12		T35	5		T231	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T42	2		T27	17		T51	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T178	8		T244	29		T232	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	313	1			T39	8		T40	18		T143	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T3	14		T19	8		T51	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22194

1

T1

20

T2

21

T3

3

auto[1]

auto[0]

4078

1

T2

13

T3

35

T5

20