Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26272

1

T1

20

T2

34

T3

38

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20691

1

T1

20

T2

34

T3

29

auto[ADC_CTRL_FILTER_COND_OUT]

5581

1

T3

9

T5

22

T6

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20110

1

T1

20

T2

29

T3

23

auto[1]

6162

1

T2

5

T3

15

T5

22

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22246

1

T1

20

T2

15

T3

38

auto[1]

4026

1

T2

19

T12

14

T14

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	252	1			T43	20		T144	25		T154	13
values[0]	1	1			T250	1		-	-		-	-
values[1]	547	1			T12	20		T15	1		T30	1
values[2]	759	1			T2	29		T39	12		T41	11
values[3]	753	1			T191	7		T16	14		T30	1
values[4]	661	1			T19	25		T51	8		T155	1
values[5]	724	1			T3	9		T6	1		T8	1
values[6]	646	1			T35	18		T36	10		T51	15
values[7]	892	1			T3	29		T11	1		T39	16
values[8]	568	1			T11	1		T12	8		T42	12
values[9]	3224	1			T2	5		T5	22		T13	10
minimum	17245	1			T1	20		T4	133		T7	15

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	525	1			T12	20		T30	1		T157	2
values[1]	2970	1			T2	29		T5	22		T13	10
values[2]	821	1			T191	7		T17	12		T162	11
values[3]	620	1			T191	3		T51	8		T155	1
values[4]	837	1			T3	9		T6	1		T8	1
values[5]	586	1			T41	20		T35	18		T36	10
values[6]	813	1			T3	29		T11	2		T39	16
values[7]	758	1			T12	8		T42	12		T150	25
values[8]	825	1			T2	5		T39	16		T40	19
values[9]	72	1			T152	1		T168	16		T300	4
minimum	17445	1			T1	20		T4	133		T7	15

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22194

1

T1

20

T2

21

T3

3

auto[1]

4078

1

T2

13

T3

35

T5

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T12	11		T157	2		T228	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T30	1		T37	7		T284	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T2	13		T39	9		T41	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1545	1			T5	22		T13	10		T14	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T17	7		T162	11		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T191	7		T210	19		T176	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T191	3		T228	10		T166	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T51	6		T155	1		T228	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T8	1		T43	13		T56	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T3	9		T6	1		T143	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T36	7		T37	4		T182	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T41	10		T35	11		T145	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T3	29		T11	2		T32	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T39	12		T40	13		T27	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T12	3		T150	12		T153	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T42	8		T27	18		T232	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T2	2		T40	19		T43	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T39	3		T41	1		T42	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T168	7		T300	1		T208	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T152	1		T272	1		T276	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17179	1			T1	20		T4	133		T7	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T15	1		T154	8		T301	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T12	9		T228	2		T211	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T37	6		T261	4		T240	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T2	16		T39	3		T41	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1034	1			T14	11		T56	19		T193	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T17	5		T144	1		T229	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T176	12		T37	1		T237	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T228	9		T166	5		T235	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T51	2		T228	9		T160	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T43	18		T56	15		T49	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T143	16		T51	6		T178	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T36	3		T37	2		T80	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T41	10		T35	7		T145	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T32	7		T214	10		T168	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T39	4		T27	7		T20	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T12	5		T150	13		T167	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T42	4		T27	15		T232	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T2	3		T43	10		T194	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T39	13		T41	8		T42	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T168	9		T300	3		T208	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T276	2		T252	9		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T42	2		T17	2		T35	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T301	2		T96	12		T259	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T43	10		T166	11		T37	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T144	11		T154	13		T161	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T250	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T12	11		T157	2		T230	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T15	1		T30	1		T154	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T2	13		T39	9		T41	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T42	1		T56	15		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T30	1		T17	7		T33	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T191	7		T16	11		T176	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T19	15		T147	10		T228	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T51	6		T155	1		T210	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T8	1		T43	13		T56	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T3	9		T6	1		T143	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T36	7		T235	1		T231	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T35	11		T51	9		T165	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T3	29		T11	1		T32	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T39	12		T40	13		T41	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T11	1		T12	3		T150	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T42	8		T247	11		T232	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T2	2		T40	19		T194	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1643	1			T5	22		T13	10		T14	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17112	1			T1	20		T4	133		T7	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T43	10		T166	10		T37	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T144	14		T161	6		T260	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T12	9		T161	11		T270	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T37	6		T261	4		T240	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T2	16		T39	3		T41	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T56	19		T155	12		T278	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T17	5		T144	1		T229	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T16	3		T176	12		T237	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T19	10		T228	9		T166	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T51	2		T228	9		T37	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T43	18		T56	15		T49	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T143	16		T178	8		T160	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T36	3		T235	3		T80	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T35	7		T51	6		T165	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T32	7		T37	2		T168	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T39	4		T41	10		T27	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T12	5		T150	13		T214	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T42	4		T232	11		T299	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T2	3		T194	2		T152	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1112	1			T14	11		T39	13		T41	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T42	2		T17	2		T35	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T12	10		T157	1		T228	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T30	1		T37	7		T284	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T2	17		T39	4		T41	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1372	1			T5	2		T13	1		T14	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T17	9		T162	1		T144	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T191	1		T210	1		T176	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T191	1		T228	10		T166	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T51	3		T155	1		T228	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T8	1		T43	19		T56	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T3	1		T6	1		T143	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T36	6		T37	5		T182	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T41	11		T35	13		T145	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T3	2		T11	2		T32	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T39	5		T40	1		T27	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T12	6		T150	14		T153	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T42	5		T27	16		T232	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T2	4		T40	1		T43	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T39	14		T41	9		T42	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T168	10		T300	4		T208	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T152	1		T272	1		T276	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17327	1			T1	20		T4	133		T7	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T15	1		T154	1		T301	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T12	10		T157	1		T228	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T37	6		T261	3		T240	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T2	12		T39	8		T41	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1207	1			T5	20		T13	9		T56	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T17	3		T162	10		T19	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T191	6		T210	18		T176	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T191	2		T228	9		T168	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T51	5		T228	2		T160	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T43	12		T56	2		T183	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T3	8		T143	14		T51	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T36	4		T37	1		T275	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T41	9		T35	5		T145	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T3	27		T32	10		T214	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T39	11		T40	12		T27	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T12	2		T150	11		T38	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T42	7		T27	17		T232	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T2	1		T40	18		T43	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T39	2		T42	12		T144	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T168	6		T208	5		T209	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T276	1		T252	9		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T245	12		T302	2		T303	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T154	7		T301	2		T96	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T43	11		T166	11		T37	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T144	15		T154	1		T161	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T250	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T12	10		T157	1		T230	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T15	1		T30	1		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T2	17		T39	4		T41	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T42	1		T56	20		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T30	1		T17	9		T33	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T191	1		T16	9		T176	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T19	17		T147	1		T228	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T51	3		T155	1		T210	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T8	1		T43	19		T56	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T3	1		T6	1		T143	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T36	6		T235	4		T231	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T35	13		T51	7		T165	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T3	2		T11	1		T32	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T39	5		T40	1		T41	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T11	1		T12	6		T150	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T42	5		T247	1		T232	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T2	4		T40	1		T194	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1454	1			T5	2		T13	1		T14	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17245	1			T1	20		T4	133		T7	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T43	9		T166	10		T37	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T144	10		T154	12		T260	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T12	10		T157	1		T245	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T154	7		T37	6		T261	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T2	12		T39	8		T41	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T56	14		T281	4		T278	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T17	3		T33	10		T162	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T191	6		T16	5		T176	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T19	8		T147	9		T228	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T51	5		T210	18		T228	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T43	12		T56	2		T191	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T3	8		T143	14		T178	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T36	4		T231	16		T184	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T35	5		T51	8		T165	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T3	27		T32	10		T37	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T39	11		T40	12		T41	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T12	2		T150	11		T214	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T42	7		T247	10		T232	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T2	1		T40	18		T152	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1301	1			T5	20		T13	9		T39	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22194

1

T1

20

T2

21

T3

3

auto[1]

auto[0]

4078

1

T2

13

T3

35

T5

20