Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26272

1

T1

20

T2

34

T3

38

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22831

1

T1

20

T2

5

T3

24

auto[ADC_CTRL_FILTER_COND_OUT]

3441

1

T2

29

T3

14

T6

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20530

1

T1

20

T2

5

T3

24

auto[1]

5742

1

T2

29

T3

14

T5

22

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22246

1

T1

20

T2

15

T3

38

auto[1]

4026

1

T2

19

T12

14

T14

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	283	1			T178	38		T182	1		T304	1
values[0]	10	1			T305	1		T263	9		-	-
values[1]	574	1			T12	8		T56	34		T30	1
values[2]	861	1			T12	20		T43	31		T150	25
values[3]	571	1			T40	13		T16	14		T28	1
values[4]	613	1			T39	28		T41	11		T42	4
values[5]	690	1			T3	29		T11	1		T42	34
values[6]	653	1			T39	16		T40	19		T152	28
values[7]	779	1			T41	29		T152	1		T27	18
values[8]	3059	1			T5	22		T11	1		T13	10
values[9]	934	1			T2	34		T3	9		T6	1
minimum	17245	1			T1	20		T4	133		T7	15

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	670	1			T56	34		T143	31		T35	18
values[1]	725	1			T12	20		T40	13		T43	31
values[2]	652	1			T39	28		T41	11		T42	4
values[3]	685	1			T3	15		T17	12		T32	18
values[4]	520	1			T3	14		T11	1		T42	34
values[5]	878	1			T39	16		T40	19		T152	29
values[6]	2969	1			T5	22		T13	10		T14	12
values[7]	629	1			T11	1		T43	20		T191	3
values[8]	997	1			T2	34		T3	9		T6	1
values[9]	141	1			T176	25		T304	1		T306	1
minimum	17406	1			T1	20		T4	133		T7	15

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22194

1

T1

20

T2

21

T3

3

auto[1]

4078

1

T2

13

T3

35

T5

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T56	15		T163	1		T230	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T143	15		T35	11		T154	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T40	13		T43	13		T150	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T12	11		T19	15		T20	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T42	3		T16	11		T214	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T39	21		T41	9		T42	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T3	15		T32	11		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T17	7		T154	8		T147	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T32	13		T145	6		T155	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T3	14		T11	1		T42	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T39	3		T152	1		T144	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T40	19		T152	15		T155	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1552	1			T5	22		T13	10		T14	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T18	1		T228	6		T49	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T27	18		T162	11		T228	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T11	1		T43	10		T191	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T2	2		T3	9		T8	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T2	13		T6	1		T51	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T237	1		T277	1		T302	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T176	13		T304	1		T306	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17173	1			T1	20		T4	133		T7	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T30	1		T80	1		T206	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T56	19		T270	2		T287	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T143	16		T35	7		T229	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T43	18		T150	13		T20	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T12	9		T19	10		T20	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T16	3		T214	10		T228	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T39	7		T41	2		T229	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T32	7		T144	1		T147	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T17	5		T165	2		T37	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T32	12		T145	5		T160	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T42	15		T246	1		T282	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T39	13		T144	14		T166	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T152	13		T155	12		T178	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1073	1			T14	11		T41	18		T193	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T228	2		T49	11		T161	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T27	15		T228	9		T164	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T43	10		T194	2		T35	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T2	3		T56	15		T178	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T2	16		T51	2		T166	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T237	4		T277	2		T302	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T176	12		T24	9		T279	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T12	5		T42	2		T17	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T80	2		T206	1		T307	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T178	21		T237	1		T277	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T182	1		T304	1		T306	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T305	1		T263	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T12	3		T56	15		T157	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T30	1		T35	11		T154	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T43	13		T150	12		T191	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T12	11		T143	15		T229	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T40	13		T16	11		T153	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T28	1		T229	1		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T42	3		T32	11		T144	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T39	21		T41	9		T42	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T3	15		T145	6		T155	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T3	14		T11	1		T42	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T39	3		T32	13		T166	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T40	19		T152	15		T178	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T41	11		T152	1		T27	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T18	1		T155	1		T228	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1547	1			T5	22		T13	10		T14	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T11	1		T43	10		T191	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T2	2		T3	9		T8	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	332	1			T2	13		T6	1		T51	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17112	1			T1	20		T4	133		T7	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T178	17		T237	4		T277	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T308	1		T204	11		T118	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T12	5		T56	19		T235	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T35	7		T49	11		T161	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T43	18		T150	13		T20	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T12	9		T143	16		T229	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T16	3		T214	10		T228	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T229	7		T235	6		T211	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T32	7		T144	1		T37	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T39	7		T41	2		T165	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T145	5		T147	11		T234	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T42	15		T17	5		T168	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T39	13		T32	12		T166	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T152	13		T178	8		T244	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T41	18		T27	7		T144	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T155	12		T228	2		T236	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1061	1			T14	11		T193	21		T195	25
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T43	10		T194	2		T35	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T2	3		T56	15		T50	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T2	16		T51	8		T166	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T42	2		T17	2		T35	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T56	20		T163	1		T230	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T143	17		T35	13		T154	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T40	1		T43	19		T150	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T12	10		T19	17		T20	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T42	1		T16	9		T214	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T39	9		T41	3		T42	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T3	1		T32	8		T144	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T17	9		T154	1		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T32	13		T145	6		T155	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T3	1		T11	1		T42	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T39	14		T152	1		T144	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T40	1		T152	14		T155	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1413	1			T5	2		T13	1		T14	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T18	1		T228	3		T49	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T27	16		T162	1		T228	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T11	1		T43	11		T191	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T2	4		T3	1		T8	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T2	17		T6	1		T51	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T237	5		T277	3		T302	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T176	13		T304	1		T306	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17309	1			T1	20		T4	133		T7	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T30	1		T80	3		T206	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T56	14		T309	6		T293	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T143	14		T35	5		T154	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T40	12		T43	12		T150	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T12	10		T19	8		T20	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T42	2		T16	5		T214	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T39	19		T41	8		T211	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T3	14		T32	10		T147	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T17	3		T154	7		T147	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T32	12		T145	5		T160	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T3	13		T42	17		T246	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T39	2		T144	10		T166	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T40	18		T152	14		T178	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1212	1			T5	20		T13	9		T41	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T228	5		T231	16		T211	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T27	17		T162	10		T228	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T43	9		T191	2		T35	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T2	1		T3	8		T56	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T2	12		T51	5		T38	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T302	2		T310	5		T311	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T176	12		T24	8		T185	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T12	2		T157	1		T251	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T252	9		T312	10		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T178	18		T237	5		T277	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T182	1		T304	1		T306	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T305	1		T263	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T12	6		T56	20		T157	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T30	1		T35	13		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T43	19		T150	14		T191	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T12	10		T143	17		T229	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T40	1		T16	9		T153	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T28	1		T229	8		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T42	1		T32	8		T144	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T39	9		T41	3		T42	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T3	1		T145	6		T155	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T3	1		T11	1		T42	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T39	14		T32	13		T166	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T40	1		T152	14		T178	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T41	20		T152	1		T27	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T18	1		T155	13		T228	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1398	1			T5	2		T13	1		T14	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T11	1		T43	11		T191	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T2	4		T3	1		T8	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T2	17		T6	1		T51	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17245	1			T1	20		T4	133		T7	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T178	20		T313	7		T172	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T314	1		T185	12		T315	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T263	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T12	2		T56	14		T157	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T35	5		T154	12		T49	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T43	12		T150	11		T191	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T12	10		T143	14		T19	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T40	12		T16	5		T214	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T211	3		T169	12		T245	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T42	2		T32	10		T236	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T39	19		T41	8		T154	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T3	14		T145	5		T147	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T3	13		T42	17		T17	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T39	2		T32	12		T166	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T40	18		T152	14		T178	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T41	9		T27	10		T144	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T228	5		T256	7		T236	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1210	1			T5	20		T13	9		T27	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T43	9		T191	2		T35	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T2	1		T3	8		T56	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T2	12		T51	13		T176	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22194

1

T1

20

T2

21

T3

3

auto[1]

auto[0]

4078

1

T2

13

T3

35

T5

20