Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26272

1

T1

20

T2

34

T3

38

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22985

1

T1

20

T2

29

T3

29

auto[ADC_CTRL_FILTER_COND_OUT]

3287

1

T2

5

T3

9

T6

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20314

1

T1

20

T2

5

T3

38

auto[1]

5958

1

T2

29

T5

22

T6

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22246

1

T1

20

T2

15

T3

38

auto[1]

4026

1

T2

19

T12

14

T14

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	37	1			T168	17		T316	1		T109	19
values[0]	26	1			T6	1		T211	11		T317	1
values[1]	688	1			T39	12		T42	12		T191	7
values[2]	960	1			T12	20		T15	1		T41	20
values[3]	663	1			T2	29		T3	9		T42	22
values[4]	593	1			T3	15		T11	1		T39	16
values[5]	2900	1			T5	22		T8	1		T13	10
values[6]	749	1			T12	8		T191	3		T27	51
values[7]	791	1			T2	5		T11	1		T40	13
values[8]	666	1			T144	25		T145	11		T19	25
values[9]	954	1			T3	14		T39	16		T40	19
minimum	17245	1			T1	20		T4	133		T7	15

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1048	1			T39	12		T42	13		T191	7
values[1]	828	1			T12	20		T15	1		T150	25
values[2]	551	1			T3	9		T11	1		T41	20
values[3]	2913	1			T2	29		T3	15		T5	22
values[4]	828	1			T194	3		T30	1		T33	11
values[5]	637	1			T8	1		T12	8		T43	31
values[6]	704	1			T2	5		T11	1		T40	13
values[7]	618	1			T3	14		T40	19		T144	25
values[8]	675	1			T39	16		T41	9		T42	3
values[9]	224	1			T20	6		T168	17		T318	1
minimum	17246	1			T1	20		T4	133		T6	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22194

1

T1

20

T2

21

T3

3

auto[1]

4078

1

T2

13

T3

35

T5

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	348	1			T39	9		T42	8		T191	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T42	1		T152	15		T38	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T15	1		T150	12		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T12	11		T28	1		T32	24
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T11	1		T41	10		T176	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T3	9		T42	11		T56	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1528	1			T2	13		T3	15		T5	22
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T39	12		T228	6		T37	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T33	11		T143	15		T35	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T194	1		T30	1		T210	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T12	3		T153	1		T182	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T8	1		T43	13		T191	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T11	1		T16	11		T20	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T2	2		T40	13		T43	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T3	14		T40	19		T144	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T19	15		T157	2		T228	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T39	3		T41	1		T42	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T17	7		T18	1		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T168	10		T300	1		T319	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T20	4		T318	1		T308	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17112	1			T1	20		T4	133		T7	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T6	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T39	3		T42	4		T229	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T152	13		T38	4		T235	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T150	13		T51	2		T37	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T12	9		T32	19		T147	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T41	10		T176	6		T235	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T42	11		T56	19		T214	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1060	1			T2	16		T14	11		T41	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T39	4		T228	2		T37	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T143	16		T35	7		T36	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T194	2		T37	6		T236	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T12	5		T49	11		T183	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T43	18		T27	22		T35	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T16	3		T20	1		T178	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T2	3		T43	10		T145	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T144	14		T168	9		T80	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T19	10		T228	9		T232	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T39	13		T41	8		T56	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T17	5		T178	17		T270	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T168	7		T300	3		T204	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T20	2		T308	1		T109	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T42	2		T17	2		T35	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T168	10		T316	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T109	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T211	8		T317	1		T320	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T6	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T39	9		T42	8		T191	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T38	6		T235	1		T160	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T15	1		T41	10		T152	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T12	11		T42	1		T152	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T2	13		T150	12		T51	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T3	9		T42	11		T56	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T3	15		T11	1		T41	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T39	12		T228	6		T176	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1498	1			T5	22		T13	10		T14	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T8	1		T194	1		T30	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T12	3		T33	11		T143	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T191	3		T27	29		T35	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T11	1		T16	11		T153	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T2	2		T40	13		T43	23
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T144	11		T20	1		T304	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T145	6		T19	15		T157	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	321	1			T3	14		T39	3		T40	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T17	7		T18	1		T20	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17112	1			T1	20		T4	133		T7	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T168	7		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T109	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T211	3		T320	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T39	3		T42	4		T155	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T38	4		T235	6		T160	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T41	10		T229	13		T37	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T12	9		T152	13		T32	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T2	16		T150	13		T51	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T42	11		T56	19		T214	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T41	2		T167	14		T235	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T39	4		T228	2		T176	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1043	1			T14	11		T193	21		T195	25
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T194	2		T37	6		T235	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T12	5		T143	16		T35	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T27	22		T35	1		T166	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T16	3		T178	8		T290	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T2	3		T43	28		T51	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T144	14		T20	1		T168	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T145	5		T19	10		T228	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T39	13		T41	8		T56	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T17	5		T20	2		T178	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T42	2		T17	2		T35	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	360	1			T39	4		T42	5		T191	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T42	1		T152	14		T38	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T15	1		T150	14		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T12	10		T28	1		T32	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T11	1		T41	11		T176	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T3	1		T42	12		T56	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1386	1			T2	17		T3	1		T5	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T39	5		T228	3		T37	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T33	1		T143	17		T35	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T194	3		T30	1		T210	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T12	6		T153	1		T182	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T8	1		T43	19		T191	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T11	1		T16	9		T20	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T2	4		T40	1		T43	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T3	1		T40	1		T144	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T19	17		T157	1		T228	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T39	14		T41	9		T42	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T17	9		T18	1		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T168	8		T300	4		T319	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T20	4		T318	1		T308	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17245	1			T1	20		T4	133		T7	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T6	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T39	8		T42	7		T191	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T152	14		T38	4		T160	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T150	11		T51	5		T37	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T12	10		T32	22		T147	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T41	9		T176	2		T169	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T3	8		T42	10		T56	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1202	1			T2	12		T3	14		T5	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T39	11		T228	5		T267	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T33	10		T143	14		T35	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T210	18		T37	6		T236	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T12	2		T183	10		T261	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T43	12		T191	2		T27	27
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T16	5		T178	8		T290	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T2	1		T40	12		T43	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T3	13		T40	18		T144	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T19	8		T157	1		T228	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T39	2		T42	2		T56	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T17	3		T147	9		T178	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T168	9		T319	10		T275	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T20	2		T109	8		T321	16

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T168	8		T316	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T109	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T211	4		T317	1		T320	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T6	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T39	4		T42	5		T191	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T38	6		T235	7		T160	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T15	1		T41	11		T152	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T12	10		T42	1		T152	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T2	17		T150	14		T51	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T3	1		T42	12		T56	20
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T3	1		T11	1		T41	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T39	5		T228	3		T176	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1376	1			T5	2		T13	1		T14	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T8	1		T194	3		T30	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T12	6		T33	1		T143	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T191	1		T27	24		T35	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T11	1		T16	9		T153	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T2	4		T40	1		T43	30
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T144	15		T20	2		T304	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T145	6		T19	17		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	330	1			T3	1		T39	14		T40	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T17	9		T18	1		T20	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17245	1			T1	20		T4	133		T7	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T168	9		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T109	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T211	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T39	8		T42	7		T191	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T38	4		T160	13		T206	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T41	9		T37	11		T22	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T12	10		T152	14		T32	22
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T2	12		T150	11		T51	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T3	8		T42	10		T56	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T3	14		T41	8		T211	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T39	11		T228	5		T176	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1165	1			T5	20		T13	9		T322	30
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T37	6		T267	14		T269	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T12	2		T33	10		T143	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T191	2		T27	27		T35	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T16	5		T178	8		T290	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T2	1		T40	12		T43	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T144	10		T168	6		T244	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T145	5		T19	8		T157	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T3	13		T39	2		T40	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T17	3		T20	2		T178	20

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22194

1

T1

20

T2

21

T3

3

auto[1]

auto[0]

4078

1

T2

13

T3

35

T5

20