Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26272

1

T1

20

T2

34

T3

38

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22713

1

T1

20

T2

34

T3

23

auto[ADC_CTRL_FILTER_COND_OUT]

3559

1

T3

15

T8

1

T11

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20313

1

T1

20

T2

34

T3

24

auto[1]

5959

1

T3

14

T5

22

T12

28

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22246

1

T1

20

T2

15

T3

38

auto[1]

4026

1

T2

19

T12

14

T14

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	60	1			T303	36		T323	1		T324	1
values[0]	65	1			T164	37		T201	28		-	-
values[1]	495	1			T39	28		T40	13		T191	7
values[2]	2821	1			T5	22		T12	8		T13	10
values[3]	512	1			T41	9		T42	1		T143	31
values[4]	629	1			T42	22		T30	1		T35	18
values[5]	836	1			T2	5		T8	1		T12	20
values[6]	818	1			T3	15		T43	20		T56	34
values[7]	806	1			T3	14		T42	12		T191	3
values[8]	667	1			T3	9		T150	25		T16	14
values[9]	1318	1			T2	29		T6	1		T11	2
minimum	17245	1			T1	20		T4	133		T7	15

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	645	1			T39	28		T40	13		T191	7
values[1]	2795	1			T5	22		T12	8		T13	10
values[2]	631	1			T41	9		T30	1		T143	31
values[3]	673	1			T42	22		T194	3		T35	18
values[4]	798	1			T2	5		T8	1		T12	20
values[5]	775	1			T3	29		T42	12		T152	1
values[6]	826	1			T150	25		T56	34		T191	3
values[7]	689	1			T3	9		T11	2		T15	1
values[8]	989	1			T2	29		T6	1		T39	16
values[9]	206	1			T43	31		T37	6		T160	31
minimum	17245	1			T1	20		T4	133		T7	15

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22194

1

T1

20

T2

21

T3

3

auto[1]

4078

1

T2

13

T3

35

T5

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T191	7		T20	4		T214	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T39	12		T40	13		T30	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1459	1			T5	22		T12	3		T13	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T42	1		T33	11		T229	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T143	15		T51	6		T37	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T41	1		T30	1		T18	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T194	1		T35	11		T236	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T42	11		T144	1		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T2	2		T12	11		T42	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T8	1		T41	9		T56	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T3	14		T42	8		T157	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T3	15		T152	1		T27	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T16	11		T27	18		T36	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T150	12		T56	15		T191	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T3	9		T15	1		T228	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T11	2		T40	19		T167	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T2	13		T6	1		T39	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T153	1		T20	1		T210	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T43	13		T37	4		T160	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T318	1		T241	1		T251	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17112	1			T1	20		T4	133		T7	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T20	2		T214	10		T164	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T39	16		T17	5		T38	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	998	1			T12	5		T14	11		T193	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T229	13		T51	6		T176	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T143	16		T51	2		T37	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T41	8		T19	10		T155	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T194	2		T35	7		T236	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T42	11		T144	1		T161	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T2	3		T12	9		T43	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T41	2		T56	15		T228	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T42	4		T37	9		T168	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T27	7		T147	11		T228	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T16	3		T27	15		T36	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T150	13		T56	19		T176	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T228	9		T165	2		T284	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T167	14		T168	7		T302	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T2	16		T39	4		T41	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T166	10		T235	3		T232	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T43	18		T37	2		T160	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T251	17		T325	16		T311	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T42	2		T17	2		T35	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T303	18		T323	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T324	1		T108	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T164	18		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T201	19		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T191	7		T20	4		T214	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T39	12		T40	13		T30	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1470	1			T5	22		T12	3		T13	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T33	11		T229	1		T51	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T143	15		T51	6		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T41	1		T42	1		T18	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T35	11		T37	7		T236	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T42	11		T30	1		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T2	2		T12	11		T42	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T8	1		T41	9		T56	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T43	10		T147	10		T178	21
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T3	15		T56	15		T27	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T3	14		T42	8		T27	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T191	3		T152	1		T28	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T3	9		T16	11		T228	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T150	12		T153	1		T167	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	376	1			T2	13		T6	1		T15	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	358	1			T11	2		T40	19		T20	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17112	1			T1	20		T4	133		T7	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T303	18		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T108	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T164	19		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T201	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T20	2		T214	10		T308	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T39	16		T17	5		T37	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1023	1			T12	5		T14	11		T193	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T229	13		T51	6		T160	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T143	16		T51	2		T234	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T41	8		T155	12		T176	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T35	7		T37	6		T236	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T42	11		T144	1		T19	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T2	3		T12	9		T194	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T41	2		T56	15		T228	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T43	10		T178	17		T168	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T56	19		T27	7		T147	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T42	4		T27	15		T36	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T176	6		T161	6		T211	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T16	3		T228	9		T165	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T150	13		T167	14		T168	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	333	1			T2	16		T39	4		T41	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T166	10		T235	3		T251	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T42	2		T17	2		T35	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T191	1		T20	4		T214	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T39	18		T40	1		T30	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1326	1			T5	2		T12	6		T13	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T42	1		T33	1		T229	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T143	17		T51	3		T37	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T41	9		T30	1		T18	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T194	3		T35	13		T236	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T42	12		T144	2		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T2	4		T12	10		T42	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T8	1		T41	3		T56	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T3	1		T42	5		T157	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T3	1		T152	1		T27	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T16	9		T27	16		T36	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T150	14		T56	20		T191	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T3	1		T15	1		T228	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T11	2		T40	1		T167	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	323	1			T2	17		T6	1		T39	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T153	1		T20	1		T210	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T43	19		T37	5		T160	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T318	1		T241	1		T251	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17245	1			T1	20		T4	133		T7	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T191	6		T20	2		T214	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T39	10		T40	12		T17	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1131	1			T5	20		T12	2		T13	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T33	10		T51	8		T176	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T143	14		T51	5		T37	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T19	8		T244	19		T291	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T35	5		T236	16		T212	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T42	10		T261	11		T267	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T2	1		T12	10		T42	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T41	8		T56	2		T162	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T3	13		T42	7		T157	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T3	14		T27	10		T147	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T16	5		T27	17		T36	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T150	11		T56	14		T191	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T3	8		T228	2		T165	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T40	18		T168	9		T298	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T2	12		T39	11		T41	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T210	18		T166	10		T232	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T43	12		T37	1		T160	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T251	15		T325	9		T311	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T303	19		T323	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T324	1		T108	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T164	20		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T201	10		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T191	1		T20	4		T214	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T39	18		T40	1		T30	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1349	1			T5	2		T12	6		T13	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T33	1		T229	14		T51	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T143	17		T51	3		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T41	9		T42	1		T18	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T35	13		T37	7		T236	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T42	12		T30	1		T144	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T2	4		T12	10		T42	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T8	1		T41	3		T56	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T43	11		T147	1		T178	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T3	1		T56	20		T27	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T3	1		T42	5		T27	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T191	1		T152	1		T28	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T3	1		T16	9		T228	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T150	14		T153	1		T167	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	416	1			T2	17		T6	1		T15	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T11	2		T40	1		T20	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17245	1			T1	20		T4	133		T7	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T303	17		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T108	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T164	17		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T201	18		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T191	6		T20	2		T214	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T39	10		T40	12		T17	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1144	1			T5	20		T12	2		T13	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T33	10		T51	8		T247	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T143	14		T51	5		T297	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T176	12		T291	9		T287	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T35	5		T37	6		T236	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T42	10		T19	8		T261	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T2	1		T12	10		T42	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T41	8		T56	2		T162	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T43	9		T147	9		T178	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T3	14		T56	14		T27	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T3	13		T42	7		T27	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T191	2		T154	12		T176	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T3	8		T16	5		T228	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T150	11		T168	9		T298	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T2	12		T39	11		T41	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T40	18		T210	18		T166	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22194

1

T1

20

T2

21

T3

3

auto[1]

auto[0]

4078

1

T2

13

T3

35

T5

20