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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.72 99.07 96.67 100.00 100.00 98.83 98.33 91.17


Total test records in report: 918
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T793 /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.1241804339 Jun 04 01:55:32 PM PDT 24 Jun 04 01:59:22 PM PDT 24 392718595948 ps
T794 /workspace/coverage/default/16.adc_ctrl_clock_gating.4073274841 Jun 04 01:53:10 PM PDT 24 Jun 04 01:59:27 PM PDT 24 335664736626 ps
T795 /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.3856533629 Jun 04 01:56:41 PM PDT 24 Jun 04 02:19:29 PM PDT 24 608808280761 ps
T796 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1098111377 Jun 04 01:02:22 PM PDT 24 Jun 04 01:02:25 PM PDT 24 516044447 ps
T55 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.590271789 Jun 04 01:01:36 PM PDT 24 Jun 04 01:01:50 PM PDT 24 4995891592 ps
T797 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.3841811812 Jun 04 01:01:36 PM PDT 24 Jun 04 01:01:38 PM PDT 24 420208276 ps
T57 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2796469150 Jun 04 01:01:55 PM PDT 24 Jun 04 01:02:01 PM PDT 24 4636433304 ps
T60 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.841411774 Jun 04 01:02:03 PM PDT 24 Jun 04 01:02:05 PM PDT 24 649164699 ps
T798 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1640563837 Jun 04 01:02:18 PM PDT 24 Jun 04 01:02:20 PM PDT 24 457128865 ps
T799 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3143940907 Jun 04 01:02:21 PM PDT 24 Jun 04 01:02:24 PM PDT 24 514503775 ps
T800 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.2204399742 Jun 04 01:01:45 PM PDT 24 Jun 04 01:01:47 PM PDT 24 396228904 ps
T58 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.4264361273 Jun 04 01:01:56 PM PDT 24 Jun 04 01:02:04 PM PDT 24 9004375254 ps
T65 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3140384263 Jun 04 01:01:46 PM PDT 24 Jun 04 01:01:50 PM PDT 24 432152328 ps
T801 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3119947647 Jun 04 01:02:22 PM PDT 24 Jun 04 01:02:24 PM PDT 24 334936168 ps
T802 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.3989187061 Jun 04 01:02:13 PM PDT 24 Jun 04 01:02:15 PM PDT 24 479933063 ps
T52 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.1195400709 Jun 04 01:01:35 PM PDT 24 Jun 04 01:01:47 PM PDT 24 4104371587 ps
T59 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3082535975 Jun 04 01:01:56 PM PDT 24 Jun 04 01:02:20 PM PDT 24 8657562107 ps
T121 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.651697305 Jun 04 01:01:25 PM PDT 24 Jun 04 01:01:27 PM PDT 24 329645543 ps
T53 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.3479185884 Jun 04 01:02:11 PM PDT 24 Jun 04 01:02:14 PM PDT 24 2294810257 ps
T803 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2358940065 Jun 04 01:02:17 PM PDT 24 Jun 04 01:02:20 PM PDT 24 456050862 ps
T804 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3701093665 Jun 04 01:01:39 PM PDT 24 Jun 04 01:01:41 PM PDT 24 524126947 ps
T68 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.126986362 Jun 04 01:01:56 PM PDT 24 Jun 04 01:01:59 PM PDT 24 595226219 ps
T69 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1143271058 Jun 04 01:01:43 PM PDT 24 Jun 04 01:01:47 PM PDT 24 574131391 ps
T805 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2988327428 Jun 04 01:02:14 PM PDT 24 Jun 04 01:02:15 PM PDT 24 315602140 ps
T806 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.69547083 Jun 04 01:01:46 PM PDT 24 Jun 04 01:01:48 PM PDT 24 486181428 ps
T76 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2825087769 Jun 04 01:02:05 PM PDT 24 Jun 04 01:02:19 PM PDT 24 4512587673 ps
T54 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1116055593 Jun 04 01:01:55 PM PDT 24 Jun 04 01:02:02 PM PDT 24 4582804748 ps
T136 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1195080363 Jun 04 01:02:05 PM PDT 24 Jun 04 01:02:09 PM PDT 24 4907354210 ps
T122 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2012437645 Jun 04 01:01:43 PM PDT 24 Jun 04 01:01:45 PM PDT 24 466837588 ps
T89 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3239189578 Jun 04 01:01:44 PM PDT 24 Jun 04 01:01:46 PM PDT 24 439233681 ps
T70 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3492932464 Jun 04 01:02:04 PM PDT 24 Jun 04 01:02:05 PM PDT 24 474082560 ps
T807 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3444643056 Jun 04 01:01:38 PM PDT 24 Jun 04 01:01:40 PM PDT 24 376635586 ps
T808 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2626158105 Jun 04 01:02:17 PM PDT 24 Jun 04 01:02:19 PM PDT 24 429395285 ps
T809 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2337562149 Jun 04 01:02:15 PM PDT 24 Jun 04 01:02:16 PM PDT 24 299355211 ps
T810 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3391786696 Jun 04 01:02:24 PM PDT 24 Jun 04 01:02:26 PM PDT 24 511504017 ps
T137 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.406226319 Jun 04 01:02:05 PM PDT 24 Jun 04 01:02:07 PM PDT 24 437310348 ps
T811 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.278125085 Jun 04 01:02:21 PM PDT 24 Jun 04 01:02:23 PM PDT 24 590697871 ps
T138 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.573857644 Jun 04 01:01:43 PM PDT 24 Jun 04 01:02:02 PM PDT 24 5411368123 ps
T139 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3428527867 Jun 04 01:01:37 PM PDT 24 Jun 04 01:01:39 PM PDT 24 391296954 ps
T66 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1774342267 Jun 04 01:01:45 PM PDT 24 Jun 04 01:01:48 PM PDT 24 506664073 ps
T812 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.739348273 Jun 04 01:01:42 PM PDT 24 Jun 04 01:01:44 PM PDT 24 429231014 ps
T61 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1414098850 Jun 04 01:02:04 PM PDT 24 Jun 04 01:02:15 PM PDT 24 4333328489 ps
T813 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2732130544 Jun 04 01:01:43 PM PDT 24 Jun 04 01:01:49 PM PDT 24 2466522135 ps
T67 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3645612554 Jun 04 01:01:59 PM PDT 24 Jun 04 01:02:02 PM PDT 24 469451486 ps
T814 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1471970813 Jun 04 01:02:13 PM PDT 24 Jun 04 01:02:15 PM PDT 24 420204416 ps
T815 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.2001216088 Jun 04 01:02:18 PM PDT 24 Jun 04 01:02:20 PM PDT 24 443234686 ps
T816 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2955967658 Jun 04 01:02:12 PM PDT 24 Jun 04 01:02:14 PM PDT 24 384337954 ps
T347 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.98252112 Jun 04 01:01:55 PM PDT 24 Jun 04 01:02:00 PM PDT 24 4760919404 ps
T817 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.4123799796 Jun 04 01:02:05 PM PDT 24 Jun 04 01:02:07 PM PDT 24 292113100 ps
T818 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1596393878 Jun 04 01:02:00 PM PDT 24 Jun 04 01:02:02 PM PDT 24 524026210 ps
T819 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1899076531 Jun 04 01:01:55 PM PDT 24 Jun 04 01:01:58 PM PDT 24 506655802 ps
T123 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.1404500615 Jun 04 01:01:35 PM PDT 24 Jun 04 01:01:38 PM PDT 24 670727380 ps
T124 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.303070928 Jun 04 01:01:56 PM PDT 24 Jun 04 01:01:59 PM PDT 24 499953604 ps
T74 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3927787383 Jun 04 01:01:56 PM PDT 24 Jun 04 01:01:59 PM PDT 24 345622440 ps
T75 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2323684538 Jun 04 01:01:44 PM PDT 24 Jun 04 01:01:47 PM PDT 24 914989759 ps
T820 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.3093005044 Jun 04 01:02:21 PM PDT 24 Jun 04 01:02:23 PM PDT 24 348139388 ps
T821 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3012122828 Jun 04 01:01:44 PM PDT 24 Jun 04 01:01:47 PM PDT 24 514676654 ps
T822 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.78973040 Jun 04 01:01:45 PM PDT 24 Jun 04 01:01:48 PM PDT 24 472837269 ps
T823 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.4266142144 Jun 04 01:02:22 PM PDT 24 Jun 04 01:02:24 PM PDT 24 306583160 ps
T824 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1611888590 Jun 04 01:02:11 PM PDT 24 Jun 04 01:02:13 PM PDT 24 328237031 ps
T825 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2662576789 Jun 04 01:01:46 PM PDT 24 Jun 04 01:01:48 PM PDT 24 490861749 ps
T826 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3184113666 Jun 04 01:02:05 PM PDT 24 Jun 04 01:02:16 PM PDT 24 2425439597 ps
T827 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.1091071952 Jun 04 01:02:21 PM PDT 24 Jun 04 01:02:24 PM PDT 24 531848350 ps
T125 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3234001318 Jun 04 01:01:45 PM PDT 24 Jun 04 01:01:47 PM PDT 24 475110942 ps
T828 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.2895874452 Jun 04 01:01:37 PM PDT 24 Jun 04 01:01:39 PM PDT 24 342735984 ps
T829 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3989840722 Jun 04 01:01:55 PM PDT 24 Jun 04 01:01:57 PM PDT 24 428708336 ps
T126 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.998916484 Jun 04 01:01:35 PM PDT 24 Jun 04 01:01:39 PM PDT 24 1065110558 ps
T830 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1125533860 Jun 04 01:01:37 PM PDT 24 Jun 04 01:01:39 PM PDT 24 451112546 ps
T127 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2729698066 Jun 04 01:02:05 PM PDT 24 Jun 04 01:02:08 PM PDT 24 428099897 ps
T831 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3047101115 Jun 04 01:01:36 PM PDT 24 Jun 04 01:02:04 PM PDT 24 54286005092 ps
T832 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1450274231 Jun 04 01:01:45 PM PDT 24 Jun 04 01:01:47 PM PDT 24 600469340 ps
T833 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1828938561 Jun 04 01:01:25 PM PDT 24 Jun 04 01:01:29 PM PDT 24 389974566 ps
T834 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1852401536 Jun 04 01:01:36 PM PDT 24 Jun 04 01:01:38 PM PDT 24 760142260 ps
T835 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3096059484 Jun 04 01:01:44 PM PDT 24 Jun 04 01:01:46 PM PDT 24 428021859 ps
T77 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3593191822 Jun 04 01:01:29 PM PDT 24 Jun 04 01:01:52 PM PDT 24 7878141682 ps
T128 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.287702287 Jun 04 01:01:48 PM PDT 24 Jun 04 01:01:49 PM PDT 24 559400107 ps
T836 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2818768450 Jun 04 01:01:31 PM PDT 24 Jun 04 01:02:00 PM PDT 24 26315780148 ps
T837 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.933970730 Jun 04 01:02:10 PM PDT 24 Jun 04 01:02:12 PM PDT 24 410404379 ps
T838 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.648331469 Jun 04 01:02:06 PM PDT 24 Jun 04 01:02:08 PM PDT 24 428960307 ps
T129 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3169381025 Jun 04 01:02:04 PM PDT 24 Jun 04 01:02:06 PM PDT 24 511464298 ps
T839 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3935217011 Jun 04 01:02:13 PM PDT 24 Jun 04 01:02:16 PM PDT 24 463292758 ps
T130 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2581842333 Jun 04 01:01:57 PM PDT 24 Jun 04 01:01:59 PM PDT 24 455632016 ps
T840 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.1510611487 Jun 04 01:02:23 PM PDT 24 Jun 04 01:02:26 PM PDT 24 484583047 ps
T131 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.2598657302 Jun 04 01:01:35 PM PDT 24 Jun 04 01:01:42 PM PDT 24 1233035828 ps
T348 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.572410225 Jun 04 01:02:03 PM PDT 24 Jun 04 01:02:19 PM PDT 24 7484277688 ps
T841 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.3908199641 Jun 04 01:01:31 PM PDT 24 Jun 04 01:01:37 PM PDT 24 5227110253 ps
T842 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.2980371966 Jun 04 01:01:46 PM PDT 24 Jun 04 01:01:48 PM PDT 24 485460995 ps
T843 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2289464865 Jun 04 01:02:05 PM PDT 24 Jun 04 01:02:08 PM PDT 24 3262875003 ps
T844 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2996536897 Jun 04 01:01:35 PM PDT 24 Jun 04 01:01:40 PM PDT 24 2519253601 ps
T845 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.4046630038 Jun 04 01:01:45 PM PDT 24 Jun 04 01:01:52 PM PDT 24 5608247413 ps
T846 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.1929359056 Jun 04 01:02:22 PM PDT 24 Jun 04 01:02:24 PM PDT 24 342282443 ps
T847 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.4065226343 Jun 04 01:01:36 PM PDT 24 Jun 04 01:01:40 PM PDT 24 992327094 ps
T848 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.513098346 Jun 04 01:02:12 PM PDT 24 Jun 04 01:02:14 PM PDT 24 301080201 ps
T849 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.1859083644 Jun 04 01:02:03 PM PDT 24 Jun 04 01:02:04 PM PDT 24 316575669 ps
T850 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.783004658 Jun 04 01:01:55 PM PDT 24 Jun 04 01:01:57 PM PDT 24 546148721 ps
T851 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1370932951 Jun 04 01:01:38 PM PDT 24 Jun 04 01:01:42 PM PDT 24 604269244 ps
T852 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2186889166 Jun 04 01:01:36 PM PDT 24 Jun 04 01:01:43 PM PDT 24 2383578610 ps
T853 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1431785274 Jun 04 01:01:43 PM PDT 24 Jun 04 01:01:45 PM PDT 24 344727022 ps
T854 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.752986346 Jun 04 01:02:05 PM PDT 24 Jun 04 01:02:09 PM PDT 24 682347077 ps
T855 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.668108159 Jun 04 01:01:29 PM PDT 24 Jun 04 01:01:32 PM PDT 24 1429240856 ps
T856 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.584086906 Jun 04 01:02:02 PM PDT 24 Jun 04 01:02:03 PM PDT 24 546799217 ps
T857 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2231651189 Jun 04 01:02:23 PM PDT 24 Jun 04 01:02:25 PM PDT 24 503603204 ps
T858 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2150291574 Jun 04 01:01:56 PM PDT 24 Jun 04 01:02:00 PM PDT 24 895410795 ps
T859 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.183524695 Jun 04 01:01:46 PM PDT 24 Jun 04 01:01:50 PM PDT 24 768015814 ps
T860 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2126777072 Jun 04 01:02:04 PM PDT 24 Jun 04 01:02:08 PM PDT 24 516057491 ps
T861 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.745176447 Jun 04 01:01:45 PM PDT 24 Jun 04 01:01:49 PM PDT 24 2497962632 ps
T862 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.276825613 Jun 04 01:02:11 PM PDT 24 Jun 04 01:02:12 PM PDT 24 516826015 ps
T863 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.2343522333 Jun 04 01:01:30 PM PDT 24 Jun 04 01:01:32 PM PDT 24 455129341 ps
T864 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.1444600210 Jun 04 01:01:57 PM PDT 24 Jun 04 01:02:06 PM PDT 24 2097739379 ps
T865 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2268334573 Jun 04 01:01:57 PM PDT 24 Jun 04 01:02:15 PM PDT 24 4271926090 ps
T866 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3545585563 Jun 04 01:01:36 PM PDT 24 Jun 04 01:01:38 PM PDT 24 387397965 ps
T349 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2480932111 Jun 04 01:02:04 PM PDT 24 Jun 04 01:02:12 PM PDT 24 7971742613 ps
T867 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.2687211998 Jun 04 01:01:36 PM PDT 24 Jun 04 01:01:49 PM PDT 24 4103424383 ps
T868 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.3693683773 Jun 04 01:02:11 PM PDT 24 Jun 04 01:02:12 PM PDT 24 327683082 ps
T869 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3965586531 Jun 04 01:01:35 PM PDT 24 Jun 04 01:01:40 PM PDT 24 4693711760 ps
T870 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.615651048 Jun 04 01:01:56 PM PDT 24 Jun 04 01:01:59 PM PDT 24 605060403 ps
T135 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.4164335784 Jun 04 01:01:55 PM PDT 24 Jun 04 01:01:57 PM PDT 24 413537782 ps
T132 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3023489252 Jun 04 01:01:28 PM PDT 24 Jun 04 01:01:34 PM PDT 24 1030341667 ps
T871 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1619712232 Jun 04 01:01:56 PM PDT 24 Jun 04 01:01:58 PM PDT 24 539917911 ps
T872 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2108077339 Jun 04 01:01:40 PM PDT 24 Jun 04 01:01:51 PM PDT 24 4318177902 ps
T873 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2860340469 Jun 04 01:02:05 PM PDT 24 Jun 04 01:02:13 PM PDT 24 5114378068 ps
T874 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1505168361 Jun 04 01:01:42 PM PDT 24 Jun 04 01:01:49 PM PDT 24 3889504266 ps
T875 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.4285831793 Jun 04 01:01:44 PM PDT 24 Jun 04 01:01:56 PM PDT 24 4114040665 ps
T876 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.808596954 Jun 04 01:01:56 PM PDT 24 Jun 04 01:02:19 PM PDT 24 8269520299 ps
T877 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.795860252 Jun 04 01:01:43 PM PDT 24 Jun 04 01:01:54 PM PDT 24 2311229278 ps
T878 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2106519361 Jun 04 01:01:28 PM PDT 24 Jun 04 01:02:57 PM PDT 24 26627937123 ps
T879 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1683729594 Jun 04 01:02:05 PM PDT 24 Jun 04 01:02:06 PM PDT 24 485163494 ps
T880 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.135309826 Jun 04 01:01:45 PM PDT 24 Jun 04 01:01:56 PM PDT 24 4080151249 ps
T881 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3661335795 Jun 04 01:01:27 PM PDT 24 Jun 04 01:01:30 PM PDT 24 474570956 ps
T882 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1614755204 Jun 04 01:01:35 PM PDT 24 Jun 04 01:01:40 PM PDT 24 4750025932 ps
T883 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.165472081 Jun 04 01:01:46 PM PDT 24 Jun 04 01:01:49 PM PDT 24 559257260 ps
T884 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2043660478 Jun 04 01:01:45 PM PDT 24 Jun 04 01:01:47 PM PDT 24 335125063 ps
T133 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1221039844 Jun 04 01:01:44 PM PDT 24 Jun 04 01:01:46 PM PDT 24 500350479 ps
T885 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.333089289 Jun 04 01:01:45 PM PDT 24 Jun 04 01:01:47 PM PDT 24 985364696 ps
T886 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3903515921 Jun 04 01:01:34 PM PDT 24 Jun 04 01:02:14 PM PDT 24 53009365673 ps
T887 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.3389161335 Jun 04 01:01:54 PM PDT 24 Jun 04 01:01:56 PM PDT 24 558227869 ps
T134 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3385110418 Jun 04 01:01:38 PM PDT 24 Jun 04 01:03:37 PM PDT 24 22311567108 ps
T888 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.359776056 Jun 04 01:02:07 PM PDT 24 Jun 04 01:02:10 PM PDT 24 529787802 ps
T889 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3818991957 Jun 04 01:02:12 PM PDT 24 Jun 04 01:02:14 PM PDT 24 305701251 ps
T890 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1923816914 Jun 04 01:01:45 PM PDT 24 Jun 04 01:01:55 PM PDT 24 9085606504 ps
T891 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.1702835595 Jun 04 01:02:13 PM PDT 24 Jun 04 01:02:16 PM PDT 24 437381147 ps
T892 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.2870549900 Jun 04 01:01:46 PM PDT 24 Jun 04 01:01:59 PM PDT 24 4495528573 ps
T893 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2003674767 Jun 04 01:01:37 PM PDT 24 Jun 04 01:01:39 PM PDT 24 593617715 ps
T894 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3690942534 Jun 04 01:01:36 PM PDT 24 Jun 04 01:01:41 PM PDT 24 4223482053 ps
T895 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3227384140 Jun 04 01:01:25 PM PDT 24 Jun 04 01:01:30 PM PDT 24 977818446 ps
T896 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2057756301 Jun 04 01:01:40 PM PDT 24 Jun 04 01:01:41 PM PDT 24 345487057 ps
T897 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3270358724 Jun 04 01:01:36 PM PDT 24 Jun 04 01:01:39 PM PDT 24 538164073 ps
T898 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.4226777314 Jun 04 01:01:26 PM PDT 24 Jun 04 01:01:29 PM PDT 24 754596699 ps
T899 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2138122158 Jun 04 01:02:33 PM PDT 24 Jun 04 01:02:35 PM PDT 24 369109180 ps
T900 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.2105449698 Jun 04 01:01:46 PM PDT 24 Jun 04 01:01:49 PM PDT 24 547580765 ps
T901 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.635238062 Jun 04 01:01:56 PM PDT 24 Jun 04 01:01:58 PM PDT 24 528015761 ps
T902 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.280686104 Jun 04 01:02:00 PM PDT 24 Jun 04 01:02:12 PM PDT 24 4627859933 ps
T903 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3975147871 Jun 04 01:02:06 PM PDT 24 Jun 04 01:02:07 PM PDT 24 418894225 ps
T904 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1359959688 Jun 04 01:01:45 PM PDT 24 Jun 04 01:02:08 PM PDT 24 8350344463 ps
T905 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1108069568 Jun 04 01:01:58 PM PDT 24 Jun 04 01:02:01 PM PDT 24 344613838 ps
T906 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2091142038 Jun 04 01:01:35 PM PDT 24 Jun 04 01:01:38 PM PDT 24 1130684139 ps
T907 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2642403768 Jun 04 01:01:43 PM PDT 24 Jun 04 01:01:46 PM PDT 24 570804978 ps
T908 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1658900191 Jun 04 01:02:05 PM PDT 24 Jun 04 01:02:07 PM PDT 24 462556525 ps
T909 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3765424452 Jun 04 01:02:13 PM PDT 24 Jun 04 01:02:16 PM PDT 24 431739742 ps
T910 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.34452317 Jun 04 01:01:36 PM PDT 24 Jun 04 01:01:40 PM PDT 24 1011030004 ps
T911 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.2994883675 Jun 04 01:02:22 PM PDT 24 Jun 04 01:02:24 PM PDT 24 395158348 ps
T912 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.1059032399 Jun 04 01:02:22 PM PDT 24 Jun 04 01:02:25 PM PDT 24 353601876 ps
T913 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2483799033 Jun 04 01:01:36 PM PDT 24 Jun 04 01:01:39 PM PDT 24 821673681 ps
T914 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.589303700 Jun 04 01:01:31 PM PDT 24 Jun 04 01:01:34 PM PDT 24 1400698017 ps
T915 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.226156285 Jun 04 01:02:04 PM PDT 24 Jun 04 01:02:15 PM PDT 24 4156365904 ps
T916 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2741572403 Jun 04 01:01:56 PM PDT 24 Jun 04 01:01:58 PM PDT 24 502789011 ps
T917 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1984075547 Jun 04 01:01:38 PM PDT 24 Jun 04 01:01:41 PM PDT 24 1054213094 ps
T918 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3447981849 Jun 04 01:02:10 PM PDT 24 Jun 04 01:02:12 PM PDT 24 544654621 ps

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.349953423
Short name T3
Test name
Test status
Simulation time 520564090341 ps
CPU time 1167.46 seconds
Started Jun 04 01:54:30 PM PDT 24
Finished Jun 04 02:13:59 PM PDT 24
Peak memory 201792 kb
Host smart-47689360-2ee9-4d97-ac11-41af11bc8920
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349953423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_
wakeup.349953423
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.2421696126
Short name T44
Test name
Test status
Simulation time 99779447464 ps
CPU time 429.09 seconds
Started Jun 04 01:53:32 PM PDT 24
Finished Jun 04 02:00:42 PM PDT 24
Peak memory 202104 kb
Host smart-861c026b-9a81-4837-bd1b-db2c6c350c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421696126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.2421696126
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.3566925001
Short name T20
Test name
Test status
Simulation time 173608440429 ps
CPU time 142.43 seconds
Started Jun 04 01:56:32 PM PDT 24
Finished Jun 04 01:58:55 PM PDT 24
Peak memory 211488 kb
Host smart-9b6431c5-51ba-4335-8b3e-36f9a9256bee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566925001 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.3566925001
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.3312848802
Short name T39
Test name
Test status
Simulation time 490415435886 ps
CPU time 636.91 seconds
Started Jun 04 01:52:59 PM PDT 24
Finished Jun 04 02:03:37 PM PDT 24
Peak memory 201784 kb
Host smart-c929fa34-df3b-4c49-a835-9b6f4601c1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312848802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.3312848802
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.990065169
Short name T51
Test name
Test status
Simulation time 474791073907 ps
CPU time 551.93 seconds
Started Jun 04 01:53:09 PM PDT 24
Finished Jun 04 02:02:23 PM PDT 24
Peak memory 202284 kb
Host smart-53467d80-5850-44bd-8197-9a4d89e757d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990065169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.990065169
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.2639543097
Short name T12
Test name
Test status
Simulation time 407779345810 ps
CPU time 785.58 seconds
Started Jun 04 01:56:24 PM PDT 24
Finished Jun 04 02:09:30 PM PDT 24
Peak memory 201808 kb
Host smart-5815eac2-0957-417c-8451-e30c45a782ef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639543097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.2639543097
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.3659484242
Short name T37
Test name
Test status
Simulation time 759530960518 ps
CPU time 187.68 seconds
Started Jun 04 01:53:47 PM PDT 24
Finished Jun 04 01:56:56 PM PDT 24
Peak memory 210096 kb
Host smart-b70baf92-8dd6-4375-a5f7-fddb03c3944d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659484242 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.3659484242
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.647051336
Short name T228
Test name
Test status
Simulation time 501781987121 ps
CPU time 1107.61 seconds
Started Jun 04 01:55:54 PM PDT 24
Finished Jun 04 02:14:22 PM PDT 24
Peak memory 201836 kb
Host smart-cfca4fe2-f6d6-41f8-9075-83383ae85893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647051336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.647051336
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.29443025
Short name T42
Test name
Test status
Simulation time 725744785949 ps
CPU time 774.3 seconds
Started Jun 04 01:53:19 PM PDT 24
Finished Jun 04 02:06:15 PM PDT 24
Peak memory 201776 kb
Host smart-76bb449f-a5e6-4613-aae5-b14a6ec684f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29443025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all.29443025
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.4005835534
Short name T35
Test name
Test status
Simulation time 114835416305 ps
CPU time 68.14 seconds
Started Jun 04 01:56:00 PM PDT 24
Finished Jun 04 01:57:09 PM PDT 24
Peak memory 212816 kb
Host smart-d7d0dbe2-ba2b-4ad7-835f-a29953a09cc3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005835534 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.4005835534
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3140384263
Short name T65
Test name
Test status
Simulation time 432152328 ps
CPU time 2.93 seconds
Started Jun 04 01:01:46 PM PDT 24
Finished Jun 04 01:01:50 PM PDT 24
Peak memory 201980 kb
Host smart-37845d32-b7d5-435f-b7c7-713b0d0a1fa5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140384263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.3140384263
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.2494090440
Short name T168
Test name
Test status
Simulation time 568434424221 ps
CPU time 233.01 seconds
Started Jun 04 01:54:17 PM PDT 24
Finished Jun 04 01:58:11 PM PDT 24
Peak memory 201788 kb
Host smart-a8947f07-5b5d-472d-a0dd-b45086d26923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494090440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.2494090440
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.2415332736
Short name T4
Test name
Test status
Simulation time 93218643012 ps
CPU time 491.45 seconds
Started Jun 04 01:54:16 PM PDT 24
Finished Jun 04 02:02:28 PM PDT 24
Peak memory 202048 kb
Host smart-2d47a197-5a9d-4ffc-a1c7-534fae6d72d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415332736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.2415332736
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.2725227252
Short name T245
Test name
Test status
Simulation time 514861831161 ps
CPU time 1209.3 seconds
Started Jun 04 01:53:06 PM PDT 24
Finished Jun 04 02:13:16 PM PDT 24
Peak memory 201788 kb
Host smart-2ac05243-87ab-4382-9616-6c8323342f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725227252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.2725227252
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.2434376916
Short name T178
Test name
Test status
Simulation time 327031784490 ps
CPU time 206.31 seconds
Started Jun 04 01:53:23 PM PDT 24
Finished Jun 04 01:56:50 PM PDT 24
Peak memory 201796 kb
Host smart-23bfb89a-1ba7-4dbf-b8bd-738a5db4a0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434376916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.2434376916
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.3048848738
Short name T41
Test name
Test status
Simulation time 503236315164 ps
CPU time 1271.86 seconds
Started Jun 04 01:53:19 PM PDT 24
Finished Jun 04 02:14:32 PM PDT 24
Peak memory 201800 kb
Host smart-3506001c-53c5-4518-b04e-a22246cfd6e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048848738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.3048848738
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.715423550
Short name T175
Test name
Test status
Simulation time 455787486 ps
CPU time 1.13 seconds
Started Jun 04 01:53:06 PM PDT 24
Finished Jun 04 01:53:08 PM PDT 24
Peak memory 201500 kb
Host smart-42a2d387-b51b-476c-ba29-384f079ad141
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715423550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.715423550
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.1895880131
Short name T80
Test name
Test status
Simulation time 486266162460 ps
CPU time 221.76 seconds
Started Jun 04 01:52:29 PM PDT 24
Finished Jun 04 01:56:13 PM PDT 24
Peak memory 201816 kb
Host smart-52ce5cab-20b4-42d8-a444-877f9061734d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895880131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.1895880131
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.1492749196
Short name T63
Test name
Test status
Simulation time 8463997526 ps
CPU time 10.35 seconds
Started Jun 04 01:52:31 PM PDT 24
Finished Jun 04 01:52:43 PM PDT 24
Peak memory 218368 kb
Host smart-e6c2c708-1062-4e83-8aa4-7bdaaf951349
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492749196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.1492749196
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.1711875130
Short name T154
Test name
Test status
Simulation time 365325890928 ps
CPU time 822.65 seconds
Started Jun 04 01:53:52 PM PDT 24
Finished Jun 04 02:07:35 PM PDT 24
Peak memory 201880 kb
Host smart-99218273-13dd-4a48-b38e-8d59d3ff42b4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711875130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.1711875130
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.1649406150
Short name T160
Test name
Test status
Simulation time 371072471065 ps
CPU time 102.29 seconds
Started Jun 04 01:53:58 PM PDT 24
Finished Jun 04 01:55:41 PM PDT 24
Peak memory 201768 kb
Host smart-cef1fc38-dee8-4aeb-8d6e-15bae4379b4d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649406150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.1649406150
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.651697305
Short name T121
Test name
Test status
Simulation time 329645543 ps
CPU time 1.18 seconds
Started Jun 04 01:01:25 PM PDT 24
Finished Jun 04 01:01:27 PM PDT 24
Peak memory 201656 kb
Host smart-8d252ba8-8357-448d-a4eb-6960f9814567
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651697305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.651697305
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.3795225789
Short name T56
Test name
Test status
Simulation time 354663660188 ps
CPU time 840.85 seconds
Started Jun 04 01:54:15 PM PDT 24
Finished Jun 04 02:08:17 PM PDT 24
Peak memory 201812 kb
Host smart-fef9fc6c-f511-4a9a-85ad-208fa7631aad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795225789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.3795225789
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.1386368404
Short name T164
Test name
Test status
Simulation time 225521131001 ps
CPU time 282.49 seconds
Started Jun 04 01:53:41 PM PDT 24
Finished Jun 04 01:58:24 PM PDT 24
Peak memory 201772 kb
Host smart-25115d07-2052-42d6-b04a-6501cd76275d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386368404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.1386368404
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.440043418
Short name T211
Test name
Test status
Simulation time 494066309932 ps
CPU time 295.07 seconds
Started Jun 04 01:56:47 PM PDT 24
Finished Jun 04 02:01:43 PM PDT 24
Peak memory 201720 kb
Host smart-f3e9e769-4627-4cce-a3ac-c6e8135d82ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440043418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.440043418
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.2571717823
Short name T232
Test name
Test status
Simulation time 509428259246 ps
CPU time 549.77 seconds
Started Jun 04 01:55:50 PM PDT 24
Finished Jun 04 02:05:00 PM PDT 24
Peak memory 201800 kb
Host smart-5d15f250-faa0-42ef-b084-a77860d53f52
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571717823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.2571717823
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.1015399956
Short name T24
Test name
Test status
Simulation time 169687504493 ps
CPU time 226.05 seconds
Started Jun 04 01:56:46 PM PDT 24
Finished Jun 04 02:00:33 PM PDT 24
Peak memory 218516 kb
Host smart-593b277d-1744-4d59-9887-4b09c19b878e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015399956 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.1015399956
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.2794053726
Short name T17
Test name
Test status
Simulation time 222937916970 ps
CPU time 605.05 seconds
Started Jun 04 01:52:59 PM PDT 24
Finished Jun 04 02:03:05 PM PDT 24
Peak memory 210412 kb
Host smart-ee8973b6-0b94-4470-963e-0058846dae67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794053726 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.2794053726
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.3754117010
Short name T118
Test name
Test status
Simulation time 598713728839 ps
CPU time 287.14 seconds
Started Jun 04 01:52:24 PM PDT 24
Finished Jun 04 01:57:12 PM PDT 24
Peak memory 217756 kb
Host smart-2cfa725f-1ef3-4bb2-a3e5-c977434a2492
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754117010 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.3754117010
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.49483048
Short name T5
Test name
Test status
Simulation time 384138027370 ps
CPU time 98.71 seconds
Started Jun 04 01:53:07 PM PDT 24
Finished Jun 04 01:54:47 PM PDT 24
Peak memory 201788 kb
Host smart-2a66936a-8d98-4cd0-8cdb-ca4154f3f616
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49483048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.a
dc_ctrl_filters_wakeup_fixed.49483048
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2818768450
Short name T836
Test name
Test status
Simulation time 26315780148 ps
CPU time 28.78 seconds
Started Jun 04 01:01:31 PM PDT 24
Finished Jun 04 01:02:00 PM PDT 24
Peak memory 201764 kb
Host smart-4b81c6c9-612d-438e-9fed-564f30da51eb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818768450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.2818768450
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3593191822
Short name T77
Test name
Test status
Simulation time 7878141682 ps
CPU time 21.95 seconds
Started Jun 04 01:01:29 PM PDT 24
Finished Jun 04 01:01:52 PM PDT 24
Peak memory 201908 kb
Host smart-2faf9ae1-69da-4fcf-a0a2-60517c5ae6f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593191822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.3593191822
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.1884596151
Short name T311
Test name
Test status
Simulation time 362820045854 ps
CPU time 731.21 seconds
Started Jun 04 01:53:04 PM PDT 24
Finished Jun 04 02:05:16 PM PDT 24
Peak memory 201804 kb
Host smart-ef61353a-1a52-4626-8772-fe1809d3138b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884596151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.1884596151
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.2836044209
Short name T43
Test name
Test status
Simulation time 361048848747 ps
CPU time 893.8 seconds
Started Jun 04 01:52:44 PM PDT 24
Finished Jun 04 02:07:39 PM PDT 24
Peak memory 201816 kb
Host smart-09ec8e45-dd04-4d8e-879f-f05d7aabc34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836044209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.2836044209
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.2406505042
Short name T252
Test name
Test status
Simulation time 331532905177 ps
CPU time 183.15 seconds
Started Jun 04 01:53:23 PM PDT 24
Finished Jun 04 01:56:27 PM PDT 24
Peak memory 201752 kb
Host smart-f3ebac9d-aa41-4412-803b-993b5e881292
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406505042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.2406505042
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.562163890
Short name T287
Test name
Test status
Simulation time 592384453366 ps
CPU time 932.52 seconds
Started Jun 04 01:54:15 PM PDT 24
Finished Jun 04 02:09:49 PM PDT 24
Peak memory 201724 kb
Host smart-5f99d713-5d69-4987-abff-70130bb0e44d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562163890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gati
ng.562163890
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.4068021986
Short name T327
Test name
Test status
Simulation time 500732481659 ps
CPU time 295.9 seconds
Started Jun 04 01:53:13 PM PDT 24
Finished Jun 04 01:58:09 PM PDT 24
Peak memory 201744 kb
Host smart-35dedd1b-aa1e-4b15-8952-fc7f2c6e336b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068021986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.4068021986
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.4117617433
Short name T96
Test name
Test status
Simulation time 358265229416 ps
CPU time 192.88 seconds
Started Jun 04 01:53:47 PM PDT 24
Finished Jun 04 01:57:01 PM PDT 24
Peak memory 201808 kb
Host smart-2a60c28a-8e3e-44c2-956d-584fd75613ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117617433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.4117617433
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.3420789456
Short name T263
Test name
Test status
Simulation time 413902724685 ps
CPU time 378.91 seconds
Started Jun 04 01:52:50 PM PDT 24
Finished Jun 04 01:59:10 PM PDT 24
Peak memory 201820 kb
Host smart-3bf3a0ec-aa9a-4fd7-a199-9b886fe65b64
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420789456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.3420789456
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.2624182006
Short name T16
Test name
Test status
Simulation time 312895530686 ps
CPU time 119.16 seconds
Started Jun 04 01:53:41 PM PDT 24
Finished Jun 04 01:55:40 PM PDT 24
Peak memory 217716 kb
Host smart-80f10374-709d-437e-83f2-b1f1431ce8a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624182006 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.2624182006
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.1524313860
Short name T285
Test name
Test status
Simulation time 175753077781 ps
CPU time 326 seconds
Started Jun 04 01:53:02 PM PDT 24
Finished Jun 04 01:58:29 PM PDT 24
Peak memory 201804 kb
Host smart-1cbcdf4e-836f-4bc4-9fd9-a5ac4d7b0865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524313860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.1524313860
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.2224192805
Short name T201
Test name
Test status
Simulation time 526301072729 ps
CPU time 81.65 seconds
Started Jun 04 01:52:27 PM PDT 24
Finished Jun 04 01:53:52 PM PDT 24
Peak memory 201796 kb
Host smart-de46830e-800a-4e48-9eca-0960708ac223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224192805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.2224192805
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.3115763608
Short name T147
Test name
Test status
Simulation time 341308918520 ps
CPU time 422.92 seconds
Started Jun 04 01:53:48 PM PDT 24
Finished Jun 04 02:00:52 PM PDT 24
Peak memory 201728 kb
Host smart-be579ec3-0f41-4a7b-8173-99ee6051d683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115763608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.3115763608
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.1366755689
Short name T108
Test name
Test status
Simulation time 538618080919 ps
CPU time 278.05 seconds
Started Jun 04 01:53:17 PM PDT 24
Finished Jun 04 01:57:56 PM PDT 24
Peak memory 201748 kb
Host smart-d8ed220b-9219-4ce5-a6b9-21d4f8a5a6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366755689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.1366755689
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3023489252
Short name T132
Test name
Test status
Simulation time 1030341667 ps
CPU time 4.45 seconds
Started Jun 04 01:01:28 PM PDT 24
Finished Jun 04 01:01:34 PM PDT 24
Peak memory 201876 kb
Host smart-08fdb4c7-ff0a-4bf7-9508-d1cb97bc606d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023489252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.3023489252
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.1691122237
Short name T36
Test name
Test status
Simulation time 55815967113 ps
CPU time 109.3 seconds
Started Jun 04 01:53:00 PM PDT 24
Finished Jun 04 01:54:50 PM PDT 24
Peak memory 202168 kb
Host smart-44eb4eaa-3870-44ae-8f02-ebe26d4e0303
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691122237 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.1691122237
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.2206917018
Short name T250
Test name
Test status
Simulation time 134149470878 ps
CPU time 183.93 seconds
Started Jun 04 01:53:08 PM PDT 24
Finished Jun 04 01:56:14 PM PDT 24
Peak memory 218116 kb
Host smart-89a08072-f6f0-445c-92d4-cf9256412e3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206917018 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.2206917018
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.3918206505
Short name T209
Test name
Test status
Simulation time 357025876100 ps
CPU time 62.1 seconds
Started Jun 04 01:53:19 PM PDT 24
Finished Jun 04 01:54:22 PM PDT 24
Peak memory 201784 kb
Host smart-903ac498-36fd-4915-b0cb-fffedd211696
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918206505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.3918206505
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.4139620156
Short name T292
Test name
Test status
Simulation time 365977262264 ps
CPU time 355.55 seconds
Started Jun 04 01:56:47 PM PDT 24
Finished Jun 04 02:02:44 PM PDT 24
Peak memory 201800 kb
Host smart-62093d03-73c5-4ce7-9ea2-f983e929f927
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139620156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.4139620156
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.914936116
Short name T303
Test name
Test status
Simulation time 339994297260 ps
CPU time 671.05 seconds
Started Jun 04 01:53:09 PM PDT 24
Finished Jun 04 02:04:21 PM PDT 24
Peak memory 201864 kb
Host smart-2fe10ae7-6c81-4208-998c-6bd89a718fd9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914936116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gati
ng.914936116
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.4203562362
Short name T109
Test name
Test status
Simulation time 189711162439 ps
CPU time 185.87 seconds
Started Jun 04 01:52:59 PM PDT 24
Finished Jun 04 01:56:06 PM PDT 24
Peak memory 211432 kb
Host smart-dbd3855b-95f9-4a4c-8a1e-0211a8d98a0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203562362 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.4203562362
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.1924367540
Short name T273
Test name
Test status
Simulation time 349702717190 ps
CPU time 787.31 seconds
Started Jun 04 01:53:11 PM PDT 24
Finished Jun 04 02:06:20 PM PDT 24
Peak memory 201832 kb
Host smart-d204741e-20d4-4550-81e6-29e8e27099c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924367540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.1924367540
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.2075694604
Short name T6
Test name
Test status
Simulation time 168653754066 ps
CPU time 40.53 seconds
Started Jun 04 01:53:10 PM PDT 24
Finished Jun 04 01:53:52 PM PDT 24
Peak memory 201876 kb
Host smart-2e8853b7-796f-4fbb-9795-728ab3351558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075694604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.2075694604
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.2015245455
Short name T262
Test name
Test status
Simulation time 195776278944 ps
CPU time 490.88 seconds
Started Jun 04 01:54:55 PM PDT 24
Finished Jun 04 02:03:06 PM PDT 24
Peak memory 201868 kb
Host smart-7bf24478-a1bb-498f-9f29-796bf8cf857c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015245455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.2015245455
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.4109808043
Short name T50
Test name
Test status
Simulation time 614938591112 ps
CPU time 1125.78 seconds
Started Jun 04 01:52:44 PM PDT 24
Finished Jun 04 02:11:31 PM PDT 24
Peak memory 202004 kb
Host smart-2475a9e6-1c33-4683-bb0f-32d45087ee5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109808043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
4109808043
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.565075457
Short name T329
Test name
Test status
Simulation time 186082426780 ps
CPU time 114.61 seconds
Started Jun 04 01:53:07 PM PDT 24
Finished Jun 04 01:55:03 PM PDT 24
Peak memory 201772 kb
Host smart-3de940cd-16eb-48f5-8084-bbdcf501636c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565075457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_
wakeup.565075457
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.2862559435
Short name T296
Test name
Test status
Simulation time 339059908216 ps
CPU time 203.48 seconds
Started Jun 04 01:53:26 PM PDT 24
Finished Jun 04 01:56:50 PM PDT 24
Peak memory 201784 kb
Host smart-dfb4a9a2-91ff-4640-bd1f-0a3bf3c6c7b1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862559435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.2862559435
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.1793849235
Short name T312
Test name
Test status
Simulation time 167537527555 ps
CPU time 93.66 seconds
Started Jun 04 01:53:58 PM PDT 24
Finished Jun 04 01:55:32 PM PDT 24
Peak memory 201880 kb
Host smart-134ba8f9-c193-4f2f-879c-4349044af5a2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793849235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.1793849235
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.2245525608
Short name T40
Test name
Test status
Simulation time 354471749687 ps
CPU time 412.29 seconds
Started Jun 04 01:55:06 PM PDT 24
Finished Jun 04 02:01:59 PM PDT 24
Peak memory 201780 kb
Host smart-d2e2a9c4-d6c5-40a5-8e08-768bc7987689
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245525608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.2245525608
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.3068324798
Short name T200
Test name
Test status
Simulation time 368264824637 ps
CPU time 52.05 seconds
Started Jun 04 01:55:31 PM PDT 24
Finished Jun 04 01:56:23 PM PDT 24
Peak memory 201892 kb
Host smart-04674546-7d98-4670-9074-bbc14402edb5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068324798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.3068324798
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.2762844415
Short name T333
Test name
Test status
Simulation time 388956615858 ps
CPU time 134.67 seconds
Started Jun 04 01:52:44 PM PDT 24
Finished Jun 04 01:54:59 PM PDT 24
Peak memory 201824 kb
Host smart-5611b20e-503d-4675-884c-798b9b604d43
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762844415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.2762844415
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1614755204
Short name T882
Test name
Test status
Simulation time 4750025932 ps
CPU time 4.25 seconds
Started Jun 04 01:01:35 PM PDT 24
Finished Jun 04 01:01:40 PM PDT 24
Peak memory 201916 kb
Host smart-6fabb9a2-6e18-4ad7-b523-c2c2846645cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614755204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.1614755204
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.2211505004
Short name T143
Test name
Test status
Simulation time 213966388838 ps
CPU time 127.35 seconds
Started Jun 04 01:53:09 PM PDT 24
Finished Jun 04 01:55:18 PM PDT 24
Peak memory 201816 kb
Host smart-95048e8e-9b14-4547-afb9-5ebacd2dae94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211505004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.2211505004
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.584182204
Short name T264
Test name
Test status
Simulation time 501236612988 ps
CPU time 1154.7 seconds
Started Jun 04 01:53:16 PM PDT 24
Finished Jun 04 02:12:32 PM PDT 24
Peak memory 201812 kb
Host smart-65b81951-ee65-469c-b50b-976b2e9283e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584182204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.584182204
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.418905354
Short name T643
Test name
Test status
Simulation time 174777269086 ps
CPU time 30.65 seconds
Started Jun 04 01:53:14 PM PDT 24
Finished Jun 04 01:53:46 PM PDT 24
Peak memory 201812 kb
Host smart-bcbdb0ea-be65-400a-bdfa-de4e58b87ff4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418905354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_
wakeup.418905354
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.2190207237
Short name T11
Test name
Test status
Simulation time 329682885909 ps
CPU time 735.32 seconds
Started Jun 04 01:53:39 PM PDT 24
Finished Jun 04 02:05:55 PM PDT 24
Peak memory 201724 kb
Host smart-434b437a-40fc-4b94-b942-441ffff37902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190207237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.2190207237
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.3336405790
Short name T485
Test name
Test status
Simulation time 110519726353 ps
CPU time 271.83 seconds
Started Jun 04 01:55:37 PM PDT 24
Finished Jun 04 02:00:10 PM PDT 24
Peak memory 202116 kb
Host smart-80c10364-a990-455d-8f66-f1c40c0a6cc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336405790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.3336405790
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.127105092
Short name T271
Test name
Test status
Simulation time 1148473212307 ps
CPU time 830.31 seconds
Started Jun 04 01:56:53 PM PDT 24
Finished Jun 04 02:10:44 PM PDT 24
Peak memory 212948 kb
Host smart-3eb2418e-296a-4158-8674-599197349230
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127105092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all.
127105092
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.1003864772
Short name T233
Test name
Test status
Simulation time 490777363337 ps
CPU time 1050.13 seconds
Started Jun 04 01:52:51 PM PDT 24
Finished Jun 04 02:10:23 PM PDT 24
Peak memory 201848 kb
Host smart-11dc6c4e-3c67-4383-8dca-b629730cbe6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003864772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.1003864772
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1828938561
Short name T833
Test name
Test status
Simulation time 389974566 ps
CPU time 3.15 seconds
Started Jun 04 01:01:25 PM PDT 24
Finished Jun 04 01:01:29 PM PDT 24
Peak memory 218256 kb
Host smart-33add900-efce-4d94-8b22-020b7549781b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828938561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.1828938561
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.3735043643
Short name T249
Test name
Test status
Simulation time 233033016880 ps
CPU time 148.18 seconds
Started Jun 04 01:53:07 PM PDT 24
Finished Jun 04 01:55:37 PM PDT 24
Peak memory 201820 kb
Host smart-66011b0a-64bf-4378-989e-91a98f89e68a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735043643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.3735043643
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.4133751157
Short name T741
Test name
Test status
Simulation time 118628047237 ps
CPU time 629.07 seconds
Started Jun 04 01:53:04 PM PDT 24
Finished Jun 04 02:03:35 PM PDT 24
Peak memory 202112 kb
Host smart-31097ede-f625-4f67-b90a-c2d0faaaf0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133751157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.4133751157
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.3660350956
Short name T328
Test name
Test status
Simulation time 333175094934 ps
CPU time 417.79 seconds
Started Jun 04 01:53:00 PM PDT 24
Finished Jun 04 01:59:59 PM PDT 24
Peak memory 201784 kb
Host smart-30cec9fe-d5e7-467a-9936-4967b61ff3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660350956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.3660350956
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.377294169
Short name T280
Test name
Test status
Simulation time 177471562291 ps
CPU time 111.53 seconds
Started Jun 04 01:53:06 PM PDT 24
Finished Jun 04 01:54:59 PM PDT 24
Peak memory 201860 kb
Host smart-f8b20733-d5b4-4caa-808f-f799156da4f0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377294169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_
wakeup.377294169
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.2800305778
Short name T352
Test name
Test status
Simulation time 127300649419 ps
CPU time 450.42 seconds
Started Jun 04 01:53:24 PM PDT 24
Finished Jun 04 02:00:55 PM PDT 24
Peak memory 202168 kb
Host smart-6e2dea22-5e62-4e20-ae58-fb28ec138d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800305778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.2800305778
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.1799133761
Short name T185
Test name
Test status
Simulation time 528608650723 ps
CPU time 1262.53 seconds
Started Jun 04 01:53:40 PM PDT 24
Finished Jun 04 02:14:43 PM PDT 24
Peak memory 201888 kb
Host smart-38730b58-b1ed-4348-ab8c-5f969c88cf2b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799133761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.1799133761
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.3211529417
Short name T220
Test name
Test status
Simulation time 90360994030 ps
CPU time 521.56 seconds
Started Jun 04 01:53:40 PM PDT 24
Finished Jun 04 02:02:23 PM PDT 24
Peak memory 202160 kb
Host smart-766f9a1a-08fb-4680-a9e3-5609e6a8be85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211529417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.3211529417
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.2702981280
Short name T242
Test name
Test status
Simulation time 488688320580 ps
CPU time 237.79 seconds
Started Jun 04 01:53:41 PM PDT 24
Finished Jun 04 01:57:39 PM PDT 24
Peak memory 201884 kb
Host smart-1966a5ca-7bfa-4e76-a1a0-9996fd649a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702981280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.2702981280
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.1249972886
Short name T223
Test name
Test status
Simulation time 587746067818 ps
CPU time 556.64 seconds
Started Jun 04 01:53:58 PM PDT 24
Finished Jun 04 02:03:15 PM PDT 24
Peak memory 210416 kb
Host smart-e132c5f5-9564-4818-97d9-274d73e9fbc1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249972886 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.1249972886
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.810767373
Short name T332
Test name
Test status
Simulation time 356137863928 ps
CPU time 221.02 seconds
Started Jun 04 01:52:38 PM PDT 24
Finished Jun 04 01:56:19 PM PDT 24
Peak memory 201848 kb
Host smart-e36c1bca-e9a1-4bce-aacb-e627ad952550
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810767373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_w
akeup.810767373
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.1896334061
Short name T307
Test name
Test status
Simulation time 328320877666 ps
CPU time 362.69 seconds
Started Jun 04 01:55:22 PM PDT 24
Finished Jun 04 02:01:25 PM PDT 24
Peak memory 201904 kb
Host smart-00a0e851-ac0f-4c3b-9330-4c5bb961f754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896334061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.1896334061
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.2828892441
Short name T350
Test name
Test status
Simulation time 129289130317 ps
CPU time 646.56 seconds
Started Jun 04 01:57:01 PM PDT 24
Finished Jun 04 02:07:49 PM PDT 24
Peak memory 202176 kb
Host smart-90005216-9b69-44dd-81ea-f985b78bb29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828892441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.2828892441
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.2506314085
Short name T227
Test name
Test status
Simulation time 162877981704 ps
CPU time 359.53 seconds
Started Jun 04 01:52:58 PM PDT 24
Finished Jun 04 01:58:59 PM PDT 24
Peak memory 201720 kb
Host smart-5ede4414-eed3-42ea-9698-ef1af4482f66
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506314085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.2506314085
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.2671829876
Short name T222
Test name
Test status
Simulation time 115602272028 ps
CPU time 460.09 seconds
Started Jun 04 01:52:40 PM PDT 24
Finished Jun 04 02:00:21 PM PDT 24
Peak memory 202024 kb
Host smart-772e417d-9fe6-4af1-9cef-e7c17b5b4e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671829876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.2671829876
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3227384140
Short name T895
Test name
Test status
Simulation time 977818446 ps
CPU time 4.58 seconds
Started Jun 04 01:01:25 PM PDT 24
Finished Jun 04 01:01:30 PM PDT 24
Peak memory 201892 kb
Host smart-fb4f0a30-2b85-4e85-97b4-c3421fa6c738
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227384140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.3227384140
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2106519361
Short name T878
Test name
Test status
Simulation time 26627937123 ps
CPU time 88.23 seconds
Started Jun 04 01:01:28 PM PDT 24
Finished Jun 04 01:02:57 PM PDT 24
Peak memory 201916 kb
Host smart-236a0ca4-9fcb-47bb-b656-7b811ee0051a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106519361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.2106519361
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.668108159
Short name T855
Test name
Test status
Simulation time 1429240856 ps
CPU time 1.71 seconds
Started Jun 04 01:01:29 PM PDT 24
Finished Jun 04 01:01:32 PM PDT 24
Peak memory 201664 kb
Host smart-722c7706-6919-4d4b-9be6-d6127b3c641d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668108159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_re
set.668108159
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3661335795
Short name T881
Test name
Test status
Simulation time 474570956 ps
CPU time 2.06 seconds
Started Jun 04 01:01:27 PM PDT 24
Finished Jun 04 01:01:30 PM PDT 24
Peak memory 201644 kb
Host smart-89e1d483-a9a4-4edd-a594-6785300d9ba1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661335795 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.3661335795
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.3841811812
Short name T797
Test name
Test status
Simulation time 420208276 ps
CPU time 1.12 seconds
Started Jun 04 01:01:36 PM PDT 24
Finished Jun 04 01:01:38 PM PDT 24
Peak memory 201664 kb
Host smart-24e0be45-bd12-4d8c-b60d-282e063a11e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841811812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.3841811812
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.3908199641
Short name T841
Test name
Test status
Simulation time 5227110253 ps
CPU time 5.45 seconds
Started Jun 04 01:01:31 PM PDT 24
Finished Jun 04 01:01:37 PM PDT 24
Peak memory 201848 kb
Host smart-f67c7d2f-d76c-4aea-be0b-90793a0ef2c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908199641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.3908199641
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.4226777314
Short name T898
Test name
Test status
Simulation time 754596699 ps
CPU time 2.57 seconds
Started Jun 04 01:01:26 PM PDT 24
Finished Jun 04 01:01:29 PM PDT 24
Peak memory 218152 kb
Host smart-e4997e62-aa0e-44fc-8601-427e1e9a1993
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226777314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.4226777314
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.589303700
Short name T914
Test name
Test status
Simulation time 1400698017 ps
CPU time 2.2 seconds
Started Jun 04 01:01:31 PM PDT 24
Finished Jun 04 01:01:34 PM PDT 24
Peak memory 201680 kb
Host smart-0afff52d-0e39-4e7f-a7fb-7154fa775059
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589303700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_re
set.589303700
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2642403768
Short name T907
Test name
Test status
Simulation time 570804978 ps
CPU time 1.76 seconds
Started Jun 04 01:01:43 PM PDT 24
Finished Jun 04 01:01:46 PM PDT 24
Peak memory 201752 kb
Host smart-ee06a81b-f809-4e5d-9ace-96e508fd7f0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642403768 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.2642403768
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3545585563
Short name T866
Test name
Test status
Simulation time 387397965 ps
CPU time 1.6 seconds
Started Jun 04 01:01:36 PM PDT 24
Finished Jun 04 01:01:38 PM PDT 24
Peak memory 201684 kb
Host smart-22c5b56b-2db8-4c3f-ad60-385967566a41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545585563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.3545585563
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.2343522333
Short name T863
Test name
Test status
Simulation time 455129341 ps
CPU time 0.92 seconds
Started Jun 04 01:01:30 PM PDT 24
Finished Jun 04 01:01:32 PM PDT 24
Peak memory 201608 kb
Host smart-94e33ccb-f91f-4f96-bbba-c8ae8af57782
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343522333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.2343522333
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2996536897
Short name T844
Test name
Test status
Simulation time 2519253601 ps
CPU time 3.47 seconds
Started Jun 04 01:01:35 PM PDT 24
Finished Jun 04 01:01:40 PM PDT 24
Peak memory 201716 kb
Host smart-1d2cebc0-da10-427c-bdf5-d58c37c6fa2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996536897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.2996536897
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.165472081
Short name T883
Test name
Test status
Simulation time 559257260 ps
CPU time 1.22 seconds
Started Jun 04 01:01:46 PM PDT 24
Finished Jun 04 01:01:49 PM PDT 24
Peak memory 201700 kb
Host smart-3bb3b094-49e6-4318-b98c-fa14db769942
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165472081 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.165472081
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.287702287
Short name T128
Test name
Test status
Simulation time 559400107 ps
CPU time 1.04 seconds
Started Jun 04 01:01:48 PM PDT 24
Finished Jun 04 01:01:49 PM PDT 24
Peak memory 201668 kb
Host smart-89f499e5-67ff-4010-902c-8e7c500160f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287702287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.287702287
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1431785274
Short name T853
Test name
Test status
Simulation time 344727022 ps
CPU time 1.04 seconds
Started Jun 04 01:01:43 PM PDT 24
Finished Jun 04 01:01:45 PM PDT 24
Peak memory 201632 kb
Host smart-abb1bc41-ee43-490f-9cdc-6be5c0898697
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431785274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.1431785274
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.795860252
Short name T877
Test name
Test status
Simulation time 2311229278 ps
CPU time 9.57 seconds
Started Jun 04 01:01:43 PM PDT 24
Finished Jun 04 01:01:54 PM PDT 24
Peak memory 201704 kb
Host smart-eaeba4e0-1a04-4ead-a550-796457e9bd07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795860252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_c
trl_same_csr_outstanding.795860252
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1774342267
Short name T66
Test name
Test status
Simulation time 506664073 ps
CPU time 2.37 seconds
Started Jun 04 01:01:45 PM PDT 24
Finished Jun 04 01:01:48 PM PDT 24
Peak memory 202008 kb
Host smart-cc315351-12ba-4163-a7ec-6dce27672e82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774342267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.1774342267
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.2870549900
Short name T892
Test name
Test status
Simulation time 4495528573 ps
CPU time 12.12 seconds
Started Jun 04 01:01:46 PM PDT 24
Finished Jun 04 01:01:59 PM PDT 24
Peak memory 201908 kb
Host smart-922d5f82-231d-4505-82dc-0d3930edc28b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870549900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.2870549900
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1899076531
Short name T819
Test name
Test status
Simulation time 506655802 ps
CPU time 1.28 seconds
Started Jun 04 01:01:55 PM PDT 24
Finished Jun 04 01:01:58 PM PDT 24
Peak memory 201724 kb
Host smart-2ae71ab5-d820-4b3b-9932-5f3faf60c914
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899076531 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.1899076531
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.4164335784
Short name T135
Test name
Test status
Simulation time 413537782 ps
CPU time 1.07 seconds
Started Jun 04 01:01:55 PM PDT 24
Finished Jun 04 01:01:57 PM PDT 24
Peak memory 201648 kb
Host smart-222ff8de-cae6-462b-9699-65ffe87fbf6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164335784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.4164335784
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2741572403
Short name T916
Test name
Test status
Simulation time 502789011 ps
CPU time 0.9 seconds
Started Jun 04 01:01:56 PM PDT 24
Finished Jun 04 01:01:58 PM PDT 24
Peak memory 201636 kb
Host smart-f8a8d4fc-4bbd-4911-be53-e918f5eb7cb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741572403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.2741572403
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1116055593
Short name T54
Test name
Test status
Simulation time 4582804748 ps
CPU time 5.31 seconds
Started Jun 04 01:01:55 PM PDT 24
Finished Jun 04 01:02:02 PM PDT 24
Peak memory 201924 kb
Host smart-455f0cd6-d6b1-4c2c-8e40-63121120855b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116055593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.1116055593
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3927787383
Short name T74
Test name
Test status
Simulation time 345622440 ps
CPU time 2.43 seconds
Started Jun 04 01:01:56 PM PDT 24
Finished Jun 04 01:01:59 PM PDT 24
Peak memory 201904 kb
Host smart-ec4cf3bb-5558-4064-9155-2b9323f1ddab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927787383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.3927787383
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.808596954
Short name T876
Test name
Test status
Simulation time 8269520299 ps
CPU time 22.05 seconds
Started Jun 04 01:01:56 PM PDT 24
Finished Jun 04 01:02:19 PM PDT 24
Peak memory 202020 kb
Host smart-20f16373-9c2e-4dc9-a5fe-73491fe98433
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808596954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_in
tg_err.808596954
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.3389161335
Short name T887
Test name
Test status
Simulation time 558227869 ps
CPU time 1.12 seconds
Started Jun 04 01:01:54 PM PDT 24
Finished Jun 04 01:01:56 PM PDT 24
Peak memory 201716 kb
Host smart-b243b8ac-fda8-4631-80ad-86bc27631710
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389161335 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.3389161335
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.783004658
Short name T850
Test name
Test status
Simulation time 546148721 ps
CPU time 1.44 seconds
Started Jun 04 01:01:55 PM PDT 24
Finished Jun 04 01:01:57 PM PDT 24
Peak memory 201716 kb
Host smart-56f447a6-5a9d-45b3-b65b-ab12a9034b94
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783004658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.783004658
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3989840722
Short name T829
Test name
Test status
Simulation time 428708336 ps
CPU time 1.59 seconds
Started Jun 04 01:01:55 PM PDT 24
Finished Jun 04 01:01:57 PM PDT 24
Peak memory 201580 kb
Host smart-8e962cce-e6e3-47e5-b6d1-856e86249e4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989840722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.3989840722
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.1444600210
Short name T864
Test name
Test status
Simulation time 2097739379 ps
CPU time 7.34 seconds
Started Jun 04 01:01:57 PM PDT 24
Finished Jun 04 01:02:06 PM PDT 24
Peak memory 201644 kb
Host smart-084cc19e-cee7-48e3-bb69-002450e680f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444600210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.1444600210
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.126986362
Short name T68
Test name
Test status
Simulation time 595226219 ps
CPU time 1.5 seconds
Started Jun 04 01:01:56 PM PDT 24
Finished Jun 04 01:01:59 PM PDT 24
Peak memory 201944 kb
Host smart-35489307-80c9-4642-9d9e-8feda57eebce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126986362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.126986362
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.98252112
Short name T347
Test name
Test status
Simulation time 4760919404 ps
CPU time 3.47 seconds
Started Jun 04 01:01:55 PM PDT 24
Finished Jun 04 01:02:00 PM PDT 24
Peak memory 201952 kb
Host smart-779a8778-7b13-4a48-b633-ab5f124bd240
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98252112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_int
g_err.98252112
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1596393878
Short name T818
Test name
Test status
Simulation time 524026210 ps
CPU time 1.8 seconds
Started Jun 04 01:02:00 PM PDT 24
Finished Jun 04 01:02:02 PM PDT 24
Peak memory 201752 kb
Host smart-dce067c3-90e2-483e-b85b-ee251cf3062a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596393878 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.1596393878
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.303070928
Short name T124
Test name
Test status
Simulation time 499953604 ps
CPU time 1.92 seconds
Started Jun 04 01:01:56 PM PDT 24
Finished Jun 04 01:01:59 PM PDT 24
Peak memory 201664 kb
Host smart-74bcaba2-98e9-4cb8-8991-0ef5d70c9630
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303070928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.303070928
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1619712232
Short name T871
Test name
Test status
Simulation time 539917911 ps
CPU time 0.87 seconds
Started Jun 04 01:01:56 PM PDT 24
Finished Jun 04 01:01:58 PM PDT 24
Peak memory 201692 kb
Host smart-45950874-19ee-433b-8aee-6751fa124643
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619712232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.1619712232
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.280686104
Short name T902
Test name
Test status
Simulation time 4627859933 ps
CPU time 11.45 seconds
Started Jun 04 01:02:00 PM PDT 24
Finished Jun 04 01:02:12 PM PDT 24
Peak memory 201980 kb
Host smart-9e34bafe-ecbd-463d-99ed-09a5c62d10fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280686104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_c
trl_same_csr_outstanding.280686104
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3645612554
Short name T67
Test name
Test status
Simulation time 469451486 ps
CPU time 2.66 seconds
Started Jun 04 01:01:59 PM PDT 24
Finished Jun 04 01:02:02 PM PDT 24
Peak memory 202140 kb
Host smart-919e6d06-38e5-4009-a7fb-531d51ce85df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645612554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.3645612554
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2796469150
Short name T57
Test name
Test status
Simulation time 4636433304 ps
CPU time 3.98 seconds
Started Jun 04 01:01:55 PM PDT 24
Finished Jun 04 01:02:01 PM PDT 24
Peak memory 201980 kb
Host smart-ba9509bd-bab5-4699-ba89-e6452d55b9a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796469150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.2796469150
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.615651048
Short name T870
Test name
Test status
Simulation time 605060403 ps
CPU time 1.67 seconds
Started Jun 04 01:01:56 PM PDT 24
Finished Jun 04 01:01:59 PM PDT 24
Peak memory 201704 kb
Host smart-cffd0cc6-c88b-4cb4-8859-c5e03f2de8fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615651048 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.615651048
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2581842333
Short name T130
Test name
Test status
Simulation time 455632016 ps
CPU time 0.97 seconds
Started Jun 04 01:01:57 PM PDT 24
Finished Jun 04 01:01:59 PM PDT 24
Peak memory 201692 kb
Host smart-3748bc3b-7070-4ade-b87d-0e2e976b34f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581842333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.2581842333
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.635238062
Short name T901
Test name
Test status
Simulation time 528015761 ps
CPU time 0.94 seconds
Started Jun 04 01:01:56 PM PDT 24
Finished Jun 04 01:01:58 PM PDT 24
Peak memory 201668 kb
Host smart-27e245fe-751a-48b7-b1e6-b2c99b4e180b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635238062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.635238062
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2268334573
Short name T865
Test name
Test status
Simulation time 4271926090 ps
CPU time 17.12 seconds
Started Jun 04 01:01:57 PM PDT 24
Finished Jun 04 01:02:15 PM PDT 24
Peak memory 201876 kb
Host smart-de130d66-aeed-46bc-acc9-1bc3bd65f6ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268334573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.2268334573
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2150291574
Short name T858
Test name
Test status
Simulation time 895410795 ps
CPU time 3.14 seconds
Started Jun 04 01:01:56 PM PDT 24
Finished Jun 04 01:02:00 PM PDT 24
Peak memory 201988 kb
Host smart-6c302559-b256-4ee8-b123-388536716434
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150291574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.2150291574
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.4264361273
Short name T58
Test name
Test status
Simulation time 9004375254 ps
CPU time 7.35 seconds
Started Jun 04 01:01:56 PM PDT 24
Finished Jun 04 01:02:04 PM PDT 24
Peak memory 201888 kb
Host smart-9dbb43b6-9a03-47af-b1e7-f5cd91540d1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264361273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.4264361273
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3492932464
Short name T70
Test name
Test status
Simulation time 474082560 ps
CPU time 1.35 seconds
Started Jun 04 01:02:04 PM PDT 24
Finished Jun 04 01:02:05 PM PDT 24
Peak memory 209948 kb
Host smart-6618db9d-78c7-44ba-962c-ce1bfb270dcc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492932464 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.3492932464
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.406226319
Short name T137
Test name
Test status
Simulation time 437310348 ps
CPU time 1 seconds
Started Jun 04 01:02:05 PM PDT 24
Finished Jun 04 01:02:07 PM PDT 24
Peak memory 201720 kb
Host smart-1a9bddd3-50c0-4530-9665-6fece665ce38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406226319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.406226319
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1683729594
Short name T879
Test name
Test status
Simulation time 485163494 ps
CPU time 0.75 seconds
Started Jun 04 01:02:05 PM PDT 24
Finished Jun 04 01:02:06 PM PDT 24
Peak memory 201652 kb
Host smart-4c495164-447e-4dc2-a7be-9c9678355f1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683729594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.1683729594
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2860340469
Short name T873
Test name
Test status
Simulation time 5114378068 ps
CPU time 7.75 seconds
Started Jun 04 01:02:05 PM PDT 24
Finished Jun 04 01:02:13 PM PDT 24
Peak memory 201896 kb
Host smart-895eac93-31b2-476d-8140-ad46faa95071
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860340469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.2860340469
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1108069568
Short name T905
Test name
Test status
Simulation time 344613838 ps
CPU time 2.48 seconds
Started Jun 04 01:01:58 PM PDT 24
Finished Jun 04 01:02:01 PM PDT 24
Peak memory 201972 kb
Host smart-18a87c5b-0960-43c4-9ce4-e5efb6100d2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108069568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.1108069568
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3082535975
Short name T59
Test name
Test status
Simulation time 8657562107 ps
CPU time 22.91 seconds
Started Jun 04 01:01:56 PM PDT 24
Finished Jun 04 01:02:20 PM PDT 24
Peak memory 201940 kb
Host smart-beaca262-cd67-4eb9-b8bf-74c0ebcc3b5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082535975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.3082535975
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1658900191
Short name T908
Test name
Test status
Simulation time 462556525 ps
CPU time 1.28 seconds
Started Jun 04 01:02:05 PM PDT 24
Finished Jun 04 01:02:07 PM PDT 24
Peak memory 201700 kb
Host smart-5360abe1-56ae-4162-a1af-cf9b9b219144
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658900191 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.1658900191
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3975147871
Short name T903
Test name
Test status
Simulation time 418894225 ps
CPU time 1 seconds
Started Jun 04 01:02:06 PM PDT 24
Finished Jun 04 01:02:07 PM PDT 24
Peak memory 201700 kb
Host smart-1518dfe2-c2c6-4ce8-bc04-20084448dfc4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975147871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.3975147871
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.584086906
Short name T856
Test name
Test status
Simulation time 546799217 ps
CPU time 0.94 seconds
Started Jun 04 01:02:02 PM PDT 24
Finished Jun 04 01:02:03 PM PDT 24
Peak memory 201640 kb
Host smart-6c42f40b-62c3-4bcf-838d-ad98dd61dce7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584086906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.584086906
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1195080363
Short name T136
Test name
Test status
Simulation time 4907354210 ps
CPU time 3.36 seconds
Started Jun 04 01:02:05 PM PDT 24
Finished Jun 04 01:02:09 PM PDT 24
Peak memory 201868 kb
Host smart-d1364c0a-a10d-4123-a100-afa8510d0187
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195080363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.1195080363
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2126777072
Short name T860
Test name
Test status
Simulation time 516057491 ps
CPU time 3.71 seconds
Started Jun 04 01:02:04 PM PDT 24
Finished Jun 04 01:02:08 PM PDT 24
Peak memory 201940 kb
Host smart-1c2a9a7e-cf8c-44ea-aebc-06b11d52279c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126777072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.2126777072
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1414098850
Short name T61
Test name
Test status
Simulation time 4333328489 ps
CPU time 10.25 seconds
Started Jun 04 01:02:04 PM PDT 24
Finished Jun 04 01:02:15 PM PDT 24
Peak memory 201928 kb
Host smart-ca9da239-2e6c-44fc-8f2f-00d5c0c224b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414098850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.1414098850
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.841411774
Short name T60
Test name
Test status
Simulation time 649164699 ps
CPU time 1.41 seconds
Started Jun 04 01:02:03 PM PDT 24
Finished Jun 04 01:02:05 PM PDT 24
Peak memory 201772 kb
Host smart-6474796e-834f-467a-b488-e80092b58dfe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841411774 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.841411774
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2729698066
Short name T127
Test name
Test status
Simulation time 428099897 ps
CPU time 1.91 seconds
Started Jun 04 01:02:05 PM PDT 24
Finished Jun 04 01:02:08 PM PDT 24
Peak memory 201704 kb
Host smart-8ba3689c-15ab-4b1c-b2a5-b842defffb20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729698066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.2729698066
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.1859083644
Short name T849
Test name
Test status
Simulation time 316575669 ps
CPU time 0.81 seconds
Started Jun 04 01:02:03 PM PDT 24
Finished Jun 04 01:02:04 PM PDT 24
Peak memory 201696 kb
Host smart-71e19683-de3e-4ca2-8c22-3f53c5eed7be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859083644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.1859083644
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3184113666
Short name T826
Test name
Test status
Simulation time 2425439597 ps
CPU time 10.83 seconds
Started Jun 04 01:02:05 PM PDT 24
Finished Jun 04 01:02:16 PM PDT 24
Peak memory 201756 kb
Host smart-392cf90d-f51c-4594-b8db-b233f73fadf4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184113666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.3184113666
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.359776056
Short name T888
Test name
Test status
Simulation time 529787802 ps
CPU time 2.96 seconds
Started Jun 04 01:02:07 PM PDT 24
Finished Jun 04 01:02:10 PM PDT 24
Peak memory 202004 kb
Host smart-3b9d3aed-e519-484c-be93-4e23cf4c59a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359776056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.359776056
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2825087769
Short name T76
Test name
Test status
Simulation time 4512587673 ps
CPU time 13.36 seconds
Started Jun 04 01:02:05 PM PDT 24
Finished Jun 04 01:02:19 PM PDT 24
Peak memory 201940 kb
Host smart-1800eb25-2815-435a-9cf6-bf1e59534324
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825087769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.2825087769
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.648331469
Short name T838
Test name
Test status
Simulation time 428960307 ps
CPU time 1.11 seconds
Started Jun 04 01:02:06 PM PDT 24
Finished Jun 04 01:02:08 PM PDT 24
Peak memory 201732 kb
Host smart-579aab40-3615-43c7-a7f4-eee66c2f1397
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648331469 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.648331469
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3169381025
Short name T129
Test name
Test status
Simulation time 511464298 ps
CPU time 0.98 seconds
Started Jun 04 01:02:04 PM PDT 24
Finished Jun 04 01:02:06 PM PDT 24
Peak memory 201592 kb
Host smart-f09dc152-a37b-4a25-9617-d3ff974e9ab0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169381025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.3169381025
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.4123799796
Short name T817
Test name
Test status
Simulation time 292113100 ps
CPU time 0.89 seconds
Started Jun 04 01:02:05 PM PDT 24
Finished Jun 04 01:02:07 PM PDT 24
Peak memory 201708 kb
Host smart-bb3e93d7-8130-487c-a84a-91d86ed94e0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123799796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.4123799796
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.226156285
Short name T915
Test name
Test status
Simulation time 4156365904 ps
CPU time 10.23 seconds
Started Jun 04 01:02:04 PM PDT 24
Finished Jun 04 01:02:15 PM PDT 24
Peak memory 201960 kb
Host smart-d4eb951a-76d6-4fb2-8d70-14c58b7ce927
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226156285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_c
trl_same_csr_outstanding.226156285
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.752986346
Short name T854
Test name
Test status
Simulation time 682347077 ps
CPU time 2.94 seconds
Started Jun 04 01:02:05 PM PDT 24
Finished Jun 04 01:02:09 PM PDT 24
Peak memory 210140 kb
Host smart-4905df7f-c13d-489a-9134-2fe17b8078c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752986346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.752986346
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.572410225
Short name T348
Test name
Test status
Simulation time 7484277688 ps
CPU time 15.34 seconds
Started Jun 04 01:02:03 PM PDT 24
Finished Jun 04 01:02:19 PM PDT 24
Peak memory 201932 kb
Host smart-12dd333d-0dcd-40f5-8cb8-f490baab88be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572410225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_in
tg_err.572410225
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2231651189
Short name T857
Test name
Test status
Simulation time 503603204 ps
CPU time 1.11 seconds
Started Jun 04 01:02:23 PM PDT 24
Finished Jun 04 01:02:25 PM PDT 24
Peak memory 201644 kb
Host smart-185a0095-0dd6-4ca4-bddd-dc0bbb38dc82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231651189 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.2231651189
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3818991957
Short name T889
Test name
Test status
Simulation time 305701251 ps
CPU time 1.52 seconds
Started Jun 04 01:02:12 PM PDT 24
Finished Jun 04 01:02:14 PM PDT 24
Peak memory 201684 kb
Host smart-d269da05-172d-4690-9e23-9f1bd31098aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818991957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.3818991957
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.3989187061
Short name T802
Test name
Test status
Simulation time 479933063 ps
CPU time 1.23 seconds
Started Jun 04 01:02:13 PM PDT 24
Finished Jun 04 01:02:15 PM PDT 24
Peak memory 201700 kb
Host smart-8bf751ea-d435-493a-87ca-8b2940b98d70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989187061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.3989187061
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.3479185884
Short name T53
Test name
Test status
Simulation time 2294810257 ps
CPU time 3 seconds
Started Jun 04 01:02:11 PM PDT 24
Finished Jun 04 01:02:14 PM PDT 24
Peak memory 201780 kb
Host smart-d52bb7d0-b2fa-4622-8732-7fbec61732c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479185884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.3479185884
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2289464865
Short name T843
Test name
Test status
Simulation time 3262875003 ps
CPU time 2.96 seconds
Started Jun 04 01:02:05 PM PDT 24
Finished Jun 04 01:02:08 PM PDT 24
Peak memory 218252 kb
Host smart-044356ab-143c-4ebc-b961-1d157c3b14d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289464865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.2289464865
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2480932111
Short name T349
Test name
Test status
Simulation time 7971742613 ps
CPU time 7.6 seconds
Started Jun 04 01:02:04 PM PDT 24
Finished Jun 04 01:02:12 PM PDT 24
Peak memory 201812 kb
Host smart-5699ae7a-77d6-493b-9ad0-e5db9fd7ed4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480932111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.2480932111
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.998916484
Short name T126
Test name
Test status
Simulation time 1065110558 ps
CPU time 3.44 seconds
Started Jun 04 01:01:35 PM PDT 24
Finished Jun 04 01:01:39 PM PDT 24
Peak memory 201856 kb
Host smart-705dee78-1833-4c5a-966f-c2201e051614
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998916484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alias
ing.998916484
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3047101115
Short name T831
Test name
Test status
Simulation time 54286005092 ps
CPU time 26.34 seconds
Started Jun 04 01:01:36 PM PDT 24
Finished Jun 04 01:02:04 PM PDT 24
Peak memory 201816 kb
Host smart-58db8397-16b4-48c6-943c-a1cb7e6ece2e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047101115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.3047101115
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1984075547
Short name T917
Test name
Test status
Simulation time 1054213094 ps
CPU time 1.96 seconds
Started Jun 04 01:01:38 PM PDT 24
Finished Jun 04 01:01:41 PM PDT 24
Peak memory 201700 kb
Host smart-791ac882-1f28-41f7-bc66-ff2004e7b0ac
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984075547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.1984075547
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1852401536
Short name T834
Test name
Test status
Simulation time 760142260 ps
CPU time 1.16 seconds
Started Jun 04 01:01:36 PM PDT 24
Finished Jun 04 01:01:38 PM PDT 24
Peak memory 201632 kb
Host smart-357d1123-bb64-4aca-9e4b-abf3656d667d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852401536 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.1852401536
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2012437645
Short name T122
Test name
Test status
Simulation time 466837588 ps
CPU time 1.32 seconds
Started Jun 04 01:01:43 PM PDT 24
Finished Jun 04 01:01:45 PM PDT 24
Peak memory 201720 kb
Host smart-3be0d874-3647-4d5c-84ef-9aa1522f6794
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012437645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.2012437645
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2057756301
Short name T896
Test name
Test status
Simulation time 345487057 ps
CPU time 0.89 seconds
Started Jun 04 01:01:40 PM PDT 24
Finished Jun 04 01:01:41 PM PDT 24
Peak memory 201720 kb
Host smart-98785638-236a-468e-b009-26d5ad8a8579
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057756301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.2057756301
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2186889166
Short name T852
Test name
Test status
Simulation time 2383578610 ps
CPU time 6.2 seconds
Started Jun 04 01:01:36 PM PDT 24
Finished Jun 04 01:01:43 PM PDT 24
Peak memory 201768 kb
Host smart-99851438-4a27-45ef-9411-0bd8e7a3b9c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186889166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.2186889166
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1143271058
Short name T69
Test name
Test status
Simulation time 574131391 ps
CPU time 3.16 seconds
Started Jun 04 01:01:43 PM PDT 24
Finished Jun 04 01:01:47 PM PDT 24
Peak memory 201984 kb
Host smart-dc4196c8-05ac-44fe-8112-8a8444ff1eff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143271058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.1143271058
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3690942534
Short name T894
Test name
Test status
Simulation time 4223482053 ps
CPU time 4.05 seconds
Started Jun 04 01:01:36 PM PDT 24
Finished Jun 04 01:01:41 PM PDT 24
Peak memory 201928 kb
Host smart-b1dce301-7ba5-4ab5-b875-3aab85098789
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690942534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.3690942534
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.1702835595
Short name T891
Test name
Test status
Simulation time 437381147 ps
CPU time 1.7 seconds
Started Jun 04 01:02:13 PM PDT 24
Finished Jun 04 01:02:16 PM PDT 24
Peak memory 201532 kb
Host smart-e852e4fc-e823-45aa-b6f6-3f7ae820248f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702835595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.1702835595
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.2994883675
Short name T911
Test name
Test status
Simulation time 395158348 ps
CPU time 0.84 seconds
Started Jun 04 01:02:22 PM PDT 24
Finished Jun 04 01:02:24 PM PDT 24
Peak memory 201688 kb
Host smart-1c5c78e4-bd8b-4c96-b87d-6fcfc28be6f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994883675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.2994883675
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.3693683773
Short name T868
Test name
Test status
Simulation time 327683082 ps
CPU time 0.86 seconds
Started Jun 04 01:02:11 PM PDT 24
Finished Jun 04 01:02:12 PM PDT 24
Peak memory 201592 kb
Host smart-9650da19-c82e-4996-970e-bcde424307d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693683773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.3693683773
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1611888590
Short name T824
Test name
Test status
Simulation time 328237031 ps
CPU time 1.12 seconds
Started Jun 04 01:02:11 PM PDT 24
Finished Jun 04 01:02:13 PM PDT 24
Peak memory 201676 kb
Host smart-de141dc2-bf7b-4d47-a926-fc8a363de968
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611888590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.1611888590
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.933970730
Short name T837
Test name
Test status
Simulation time 410404379 ps
CPU time 1.15 seconds
Started Jun 04 01:02:10 PM PDT 24
Finished Jun 04 01:02:12 PM PDT 24
Peak memory 201668 kb
Host smart-37c0218c-0d5b-488a-bae2-7ba40dc60205
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933970730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.933970730
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1471970813
Short name T814
Test name
Test status
Simulation time 420204416 ps
CPU time 1.65 seconds
Started Jun 04 01:02:13 PM PDT 24
Finished Jun 04 01:02:15 PM PDT 24
Peak memory 201668 kb
Host smart-87265832-d761-4654-8b70-2a74eaf00da2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471970813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.1471970813
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.1929359056
Short name T846
Test name
Test status
Simulation time 342282443 ps
CPU time 0.86 seconds
Started Jun 04 01:02:22 PM PDT 24
Finished Jun 04 01:02:24 PM PDT 24
Peak memory 201696 kb
Host smart-6fb485a6-aad7-48be-972a-3c53d60c9299
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929359056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.1929359056
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3143940907
Short name T799
Test name
Test status
Simulation time 514503775 ps
CPU time 1.69 seconds
Started Jun 04 01:02:21 PM PDT 24
Finished Jun 04 01:02:24 PM PDT 24
Peak memory 201684 kb
Host smart-25ede1ec-699a-4cd3-beee-63658fc4b1ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143940907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.3143940907
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3765424452
Short name T909
Test name
Test status
Simulation time 431739742 ps
CPU time 1.73 seconds
Started Jun 04 01:02:13 PM PDT 24
Finished Jun 04 01:02:16 PM PDT 24
Peak memory 201612 kb
Host smart-2833815e-cde3-4902-a4c1-99e278359f90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765424452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.3765424452
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.513098346
Short name T848
Test name
Test status
Simulation time 301080201 ps
CPU time 0.8 seconds
Started Jun 04 01:02:12 PM PDT 24
Finished Jun 04 01:02:14 PM PDT 24
Peak memory 201688 kb
Host smart-5497ed2b-2445-4fdf-a0dc-f35f9212d23b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513098346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.513098346
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.1404500615
Short name T123
Test name
Test status
Simulation time 670727380 ps
CPU time 1.97 seconds
Started Jun 04 01:01:35 PM PDT 24
Finished Jun 04 01:01:38 PM PDT 24
Peak memory 201832 kb
Host smart-1a0122ba-6448-41bf-b661-cdb64cec1503
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404500615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.1404500615
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3903515921
Short name T886
Test name
Test status
Simulation time 53009365673 ps
CPU time 39.9 seconds
Started Jun 04 01:01:34 PM PDT 24
Finished Jun 04 01:02:14 PM PDT 24
Peak memory 201980 kb
Host smart-0492fe4c-ef80-4c29-a414-3742c6e0e790
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903515921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.3903515921
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2483799033
Short name T913
Test name
Test status
Simulation time 821673681 ps
CPU time 1.62 seconds
Started Jun 04 01:01:36 PM PDT 24
Finished Jun 04 01:01:39 PM PDT 24
Peak memory 201664 kb
Host smart-e810e173-dcaf-44c2-ae17-a93d34bcd691
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483799033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.2483799033
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3270358724
Short name T897
Test name
Test status
Simulation time 538164073 ps
CPU time 2.01 seconds
Started Jun 04 01:01:36 PM PDT 24
Finished Jun 04 01:01:39 PM PDT 24
Peak memory 201676 kb
Host smart-1233c8b4-cb47-402f-9ada-aa942f45dddd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270358724 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.3270358724
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2003674767
Short name T893
Test name
Test status
Simulation time 593617715 ps
CPU time 1.16 seconds
Started Jun 04 01:01:37 PM PDT 24
Finished Jun 04 01:01:39 PM PDT 24
Peak memory 201716 kb
Host smart-0937e207-264f-4be6-a974-9299578882c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003674767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.2003674767
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3444643056
Short name T807
Test name
Test status
Simulation time 376635586 ps
CPU time 1.45 seconds
Started Jun 04 01:01:38 PM PDT 24
Finished Jun 04 01:01:40 PM PDT 24
Peak memory 201692 kb
Host smart-7e91aa87-2717-43bc-995c-cd76338286ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444643056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.3444643056
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.1195400709
Short name T52
Test name
Test status
Simulation time 4104371587 ps
CPU time 11.07 seconds
Started Jun 04 01:01:35 PM PDT 24
Finished Jun 04 01:01:47 PM PDT 24
Peak memory 201816 kb
Host smart-7acf01f9-db4f-45f6-8f82-dc28c9e598a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195400709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.1195400709
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.4065226343
Short name T847
Test name
Test status
Simulation time 992327094 ps
CPU time 3.32 seconds
Started Jun 04 01:01:36 PM PDT 24
Finished Jun 04 01:01:40 PM PDT 24
Peak memory 201880 kb
Host smart-b231388e-3082-47bb-9184-0b2ad72031ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065226343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.4065226343
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1359959688
Short name T904
Test name
Test status
Simulation time 8350344463 ps
CPU time 22.15 seconds
Started Jun 04 01:01:45 PM PDT 24
Finished Jun 04 01:02:08 PM PDT 24
Peak memory 201988 kb
Host smart-1dc97f1f-9837-4348-ab33-b4440a97dbf7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359959688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.1359959688
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.276825613
Short name T862
Test name
Test status
Simulation time 516826015 ps
CPU time 0.9 seconds
Started Jun 04 01:02:11 PM PDT 24
Finished Jun 04 01:02:12 PM PDT 24
Peak memory 201616 kb
Host smart-bb2d596d-a167-4002-8ecd-0bec3275a846
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276825613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.276825613
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1640563837
Short name T798
Test name
Test status
Simulation time 457128865 ps
CPU time 1.7 seconds
Started Jun 04 01:02:18 PM PDT 24
Finished Jun 04 01:02:20 PM PDT 24
Peak memory 201604 kb
Host smart-61efff15-34de-4b9e-95e2-66a5d1e522ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640563837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.1640563837
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1098111377
Short name T796
Test name
Test status
Simulation time 516044447 ps
CPU time 0.96 seconds
Started Jun 04 01:02:22 PM PDT 24
Finished Jun 04 01:02:25 PM PDT 24
Peak memory 201688 kb
Host smart-dd2ace1a-7318-409c-bbca-4fcffa3d6523
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098111377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.1098111377
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2626158105
Short name T808
Test name
Test status
Simulation time 429395285 ps
CPU time 0.97 seconds
Started Jun 04 01:02:17 PM PDT 24
Finished Jun 04 01:02:19 PM PDT 24
Peak memory 201600 kb
Host smart-c25d122b-be78-479e-8036-700e59abc92a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626158105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.2626158105
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2988327428
Short name T805
Test name
Test status
Simulation time 315602140 ps
CPU time 0.83 seconds
Started Jun 04 01:02:14 PM PDT 24
Finished Jun 04 01:02:15 PM PDT 24
Peak memory 201820 kb
Host smart-77dff594-3b01-450b-aaa8-a626c007e2e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988327428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.2988327428
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.3093005044
Short name T820
Test name
Test status
Simulation time 348139388 ps
CPU time 1.43 seconds
Started Jun 04 01:02:21 PM PDT 24
Finished Jun 04 01:02:23 PM PDT 24
Peak memory 201688 kb
Host smart-c857d701-896b-4d2b-90cc-d41db3040719
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093005044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.3093005044
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3935217011
Short name T839
Test name
Test status
Simulation time 463292758 ps
CPU time 1.17 seconds
Started Jun 04 01:02:13 PM PDT 24
Finished Jun 04 01:02:16 PM PDT 24
Peak memory 201624 kb
Host smart-bb6f6424-39b4-46e3-89c8-2a7da83961ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935217011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.3935217011
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3119947647
Short name T801
Test name
Test status
Simulation time 334936168 ps
CPU time 0.81 seconds
Started Jun 04 01:02:22 PM PDT 24
Finished Jun 04 01:02:24 PM PDT 24
Peak memory 201696 kb
Host smart-2626ff14-0bca-40b1-9a57-e8c2746bf207
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119947647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.3119947647
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.2001216088
Short name T815
Test name
Test status
Simulation time 443234686 ps
CPU time 0.81 seconds
Started Jun 04 01:02:18 PM PDT 24
Finished Jun 04 01:02:20 PM PDT 24
Peak memory 201600 kb
Host smart-560ea7c3-7f4f-4758-aee7-ddcac9072063
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001216088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.2001216088
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2337562149
Short name T809
Test name
Test status
Simulation time 299355211 ps
CPU time 0.82 seconds
Started Jun 04 01:02:15 PM PDT 24
Finished Jun 04 01:02:16 PM PDT 24
Peak memory 201668 kb
Host smart-aac7a9ea-cd77-4197-b1f2-18cf34860e5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337562149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.2337562149
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.2598657302
Short name T131
Test name
Test status
Simulation time 1233035828 ps
CPU time 5.22 seconds
Started Jun 04 01:01:35 PM PDT 24
Finished Jun 04 01:01:42 PM PDT 24
Peak memory 201788 kb
Host smart-733f5e03-a6bc-4f79-a01b-dc2dd9a36532
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598657302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.2598657302
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3385110418
Short name T134
Test name
Test status
Simulation time 22311567108 ps
CPU time 118.74 seconds
Started Jun 04 01:01:38 PM PDT 24
Finished Jun 04 01:03:37 PM PDT 24
Peak memory 202012 kb
Host smart-f5906a57-429e-4be1-806b-feb6fb5dc425
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385110418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.3385110418
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2091142038
Short name T906
Test name
Test status
Simulation time 1130684139 ps
CPU time 1.46 seconds
Started Jun 04 01:01:35 PM PDT 24
Finished Jun 04 01:01:38 PM PDT 24
Peak memory 201644 kb
Host smart-79625a01-6534-4a25-96cb-0e3b34a77849
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091142038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.2091142038
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.333089289
Short name T885
Test name
Test status
Simulation time 985364696 ps
CPU time 1.11 seconds
Started Jun 04 01:01:45 PM PDT 24
Finished Jun 04 01:01:47 PM PDT 24
Peak memory 201764 kb
Host smart-892e7b22-295e-46ec-9ec8-ec0a959e0d6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333089289 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.333089289
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.2895874452
Short name T828
Test name
Test status
Simulation time 342735984 ps
CPU time 0.96 seconds
Started Jun 04 01:01:37 PM PDT 24
Finished Jun 04 01:01:39 PM PDT 24
Peak memory 201648 kb
Host smart-01a752e0-433f-4555-a225-4b287a336dc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895874452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.2895874452
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3701093665
Short name T804
Test name
Test status
Simulation time 524126947 ps
CPU time 1.2 seconds
Started Jun 04 01:01:39 PM PDT 24
Finished Jun 04 01:01:41 PM PDT 24
Peak memory 201696 kb
Host smart-a4e46934-55af-48bb-a5de-75986b7bcbfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701093665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.3701093665
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.590271789
Short name T55
Test name
Test status
Simulation time 4995891592 ps
CPU time 13.21 seconds
Started Jun 04 01:01:36 PM PDT 24
Finished Jun 04 01:01:50 PM PDT 24
Peak memory 201888 kb
Host smart-ba572f70-b451-4cf7-97b7-f123e2e83983
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590271789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ct
rl_same_csr_outstanding.590271789
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1370932951
Short name T851
Test name
Test status
Simulation time 604269244 ps
CPU time 2.48 seconds
Started Jun 04 01:01:38 PM PDT 24
Finished Jun 04 01:01:42 PM PDT 24
Peak memory 218224 kb
Host smart-9b065bd0-8fdc-440f-a21b-cdd304def31f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370932951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.1370932951
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2108077339
Short name T872
Test name
Test status
Simulation time 4318177902 ps
CPU time 11 seconds
Started Jun 04 01:01:40 PM PDT 24
Finished Jun 04 01:01:51 PM PDT 24
Peak memory 202020 kb
Host smart-3f28aa7b-a0de-4daa-a038-f2ea213b2869
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108077339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.2108077339
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3447981849
Short name T918
Test name
Test status
Simulation time 544654621 ps
CPU time 0.92 seconds
Started Jun 04 01:02:10 PM PDT 24
Finished Jun 04 01:02:12 PM PDT 24
Peak memory 201628 kb
Host smart-fd5191dd-25b5-43a3-a1cc-5ce6adeaf266
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447981849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.3447981849
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.1510611487
Short name T840
Test name
Test status
Simulation time 484583047 ps
CPU time 1.28 seconds
Started Jun 04 01:02:23 PM PDT 24
Finished Jun 04 01:02:26 PM PDT 24
Peak memory 201524 kb
Host smart-2522a4e3-c64f-4d9f-a686-4c7eedcabe1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510611487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.1510611487
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2358940065
Short name T803
Test name
Test status
Simulation time 456050862 ps
CPU time 1.88 seconds
Started Jun 04 01:02:17 PM PDT 24
Finished Jun 04 01:02:20 PM PDT 24
Peak memory 201604 kb
Host smart-595a1eac-49f5-43e5-a27d-2e96229cd093
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358940065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.2358940065
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2955967658
Short name T816
Test name
Test status
Simulation time 384337954 ps
CPU time 1.56 seconds
Started Jun 04 01:02:12 PM PDT 24
Finished Jun 04 01:02:14 PM PDT 24
Peak memory 201648 kb
Host smart-5c8f60b7-2b51-435e-849a-c380e5ba6e4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955967658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.2955967658
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3391786696
Short name T810
Test name
Test status
Simulation time 511504017 ps
CPU time 0.95 seconds
Started Jun 04 01:02:24 PM PDT 24
Finished Jun 04 01:02:26 PM PDT 24
Peak memory 201612 kb
Host smart-cc2a3bbe-2de8-4b67-9d48-516b3b871c60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391786696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.3391786696
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.1059032399
Short name T912
Test name
Test status
Simulation time 353601876 ps
CPU time 1.54 seconds
Started Jun 04 01:02:22 PM PDT 24
Finished Jun 04 01:02:25 PM PDT 24
Peak memory 201692 kb
Host smart-8ff7d054-6f3d-4d6d-ba5d-d3bd64967033
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059032399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.1059032399
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.278125085
Short name T811
Test name
Test status
Simulation time 590697871 ps
CPU time 0.83 seconds
Started Jun 04 01:02:21 PM PDT 24
Finished Jun 04 01:02:23 PM PDT 24
Peak memory 201644 kb
Host smart-47502501-5843-4f0d-aa6d-8ca224bebc35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278125085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.278125085
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.4266142144
Short name T823
Test name
Test status
Simulation time 306583160 ps
CPU time 0.82 seconds
Started Jun 04 01:02:22 PM PDT 24
Finished Jun 04 01:02:24 PM PDT 24
Peak memory 201644 kb
Host smart-bb066bd8-3e93-4683-8e35-edcf3b3a235f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266142144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.4266142144
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.1091071952
Short name T827
Test name
Test status
Simulation time 531848350 ps
CPU time 1.85 seconds
Started Jun 04 01:02:21 PM PDT 24
Finished Jun 04 01:02:24 PM PDT 24
Peak memory 201636 kb
Host smart-e8b924bc-6883-49a4-8d43-69afedcf9e7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091071952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.1091071952
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2138122158
Short name T899
Test name
Test status
Simulation time 369109180 ps
CPU time 0.87 seconds
Started Jun 04 01:02:33 PM PDT 24
Finished Jun 04 01:02:35 PM PDT 24
Peak memory 201604 kb
Host smart-81fefe9e-d808-4e93-9738-bd284aeea2af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138122158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.2138122158
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.739348273
Short name T812
Test name
Test status
Simulation time 429231014 ps
CPU time 1.31 seconds
Started Jun 04 01:01:42 PM PDT 24
Finished Jun 04 01:01:44 PM PDT 24
Peak memory 201700 kb
Host smart-70ed4a6e-d633-4442-b4eb-09747ee6db18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739348273 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.739348273
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3428527867
Short name T139
Test name
Test status
Simulation time 391296954 ps
CPU time 1.29 seconds
Started Jun 04 01:01:37 PM PDT 24
Finished Jun 04 01:01:39 PM PDT 24
Peak memory 201716 kb
Host smart-b4f78d9d-e62a-4c26-99c6-53df58d1d6c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428527867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.3428527867
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1125533860
Short name T830
Test name
Test status
Simulation time 451112546 ps
CPU time 1.74 seconds
Started Jun 04 01:01:37 PM PDT 24
Finished Jun 04 01:01:39 PM PDT 24
Peak memory 201676 kb
Host smart-5ddbd2b8-88da-499f-bede-86767a54e5b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125533860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.1125533860
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3965586531
Short name T869
Test name
Test status
Simulation time 4693711760 ps
CPU time 4.04 seconds
Started Jun 04 01:01:35 PM PDT 24
Finished Jun 04 01:01:40 PM PDT 24
Peak memory 202016 kb
Host smart-b8d432df-0028-47f3-9b8b-d15bd16e015c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965586531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.3965586531
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.34452317
Short name T910
Test name
Test status
Simulation time 1011030004 ps
CPU time 2.86 seconds
Started Jun 04 01:01:36 PM PDT 24
Finished Jun 04 01:01:40 PM PDT 24
Peak memory 218240 kb
Host smart-2cd54a5c-8322-4288-99b4-be1926ebad61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34452317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.34452317
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.2687211998
Short name T867
Test name
Test status
Simulation time 4103424383 ps
CPU time 12.54 seconds
Started Jun 04 01:01:36 PM PDT 24
Finished Jun 04 01:01:49 PM PDT 24
Peak memory 201988 kb
Host smart-948baab9-5d8f-4b24-ac2f-b861935b145f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687211998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.2687211998
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3239189578
Short name T89
Test name
Test status
Simulation time 439233681 ps
CPU time 1.37 seconds
Started Jun 04 01:01:44 PM PDT 24
Finished Jun 04 01:01:46 PM PDT 24
Peak memory 201664 kb
Host smart-a323db6d-ae74-4512-b652-d235e7a6f218
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239189578 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.3239189578
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.2980371966
Short name T842
Test name
Test status
Simulation time 485460995 ps
CPU time 1.31 seconds
Started Jun 04 01:01:46 PM PDT 24
Finished Jun 04 01:01:48 PM PDT 24
Peak memory 201648 kb
Host smart-3e8b0eb0-3574-4c11-88c7-4efb38b2e877
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980371966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.2980371966
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2662576789
Short name T825
Test name
Test status
Simulation time 490861749 ps
CPU time 0.89 seconds
Started Jun 04 01:01:46 PM PDT 24
Finished Jun 04 01:01:48 PM PDT 24
Peak memory 201664 kb
Host smart-9497a94c-c891-44f6-8cac-cc5e69927654
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662576789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.2662576789
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.573857644
Short name T138
Test name
Test status
Simulation time 5411368123 ps
CPU time 18.09 seconds
Started Jun 04 01:01:43 PM PDT 24
Finished Jun 04 01:02:02 PM PDT 24
Peak memory 201948 kb
Host smart-5b98737f-4a06-46ec-aa8b-9ebf1d501524
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573857644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ct
rl_same_csr_outstanding.573857644
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2323684538
Short name T75
Test name
Test status
Simulation time 914989759 ps
CPU time 2.06 seconds
Started Jun 04 01:01:44 PM PDT 24
Finished Jun 04 01:01:47 PM PDT 24
Peak memory 210148 kb
Host smart-0571f89e-5da6-435c-ad69-836eff92a405
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323684538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.2323684538
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.135309826
Short name T880
Test name
Test status
Simulation time 4080151249 ps
CPU time 10.66 seconds
Started Jun 04 01:01:45 PM PDT 24
Finished Jun 04 01:01:56 PM PDT 24
Peak memory 201864 kb
Host smart-b13d6667-c917-4f85-ab3b-52b87ba8fa66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135309826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_int
g_err.135309826
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3012122828
Short name T821
Test name
Test status
Simulation time 514676654 ps
CPU time 1.96 seconds
Started Jun 04 01:01:44 PM PDT 24
Finished Jun 04 01:01:47 PM PDT 24
Peak memory 201648 kb
Host smart-876bd715-e37a-4b51-993f-0c46bd4f1768
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012122828 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.3012122828
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1221039844
Short name T133
Test name
Test status
Simulation time 500350479 ps
CPU time 1 seconds
Started Jun 04 01:01:44 PM PDT 24
Finished Jun 04 01:01:46 PM PDT 24
Peak memory 201720 kb
Host smart-9c1656bd-b7cf-4bb5-94ca-d98042140b5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221039844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.1221039844
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.69547083
Short name T806
Test name
Test status
Simulation time 486181428 ps
CPU time 1.14 seconds
Started Jun 04 01:01:46 PM PDT 24
Finished Jun 04 01:01:48 PM PDT 24
Peak memory 201636 kb
Host smart-a544a4e7-b0e7-4e56-8c84-0adc2521de86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69547083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.69547083
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.4046630038
Short name T845
Test name
Test status
Simulation time 5608247413 ps
CPU time 5.28 seconds
Started Jun 04 01:01:45 PM PDT 24
Finished Jun 04 01:01:52 PM PDT 24
Peak memory 201876 kb
Host smart-cb6dd737-5452-411b-a4c7-15c51ce0ccdb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046630038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.4046630038
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.4285831793
Short name T875
Test name
Test status
Simulation time 4114040665 ps
CPU time 10.54 seconds
Started Jun 04 01:01:44 PM PDT 24
Finished Jun 04 01:01:56 PM PDT 24
Peak memory 201908 kb
Host smart-9971fc0f-980f-407e-bbea-8d08d69e223b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285831793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.4285831793
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.2105449698
Short name T900
Test name
Test status
Simulation time 547580765 ps
CPU time 1.43 seconds
Started Jun 04 01:01:46 PM PDT 24
Finished Jun 04 01:01:49 PM PDT 24
Peak memory 201700 kb
Host smart-ae993150-e3d8-478a-93af-9cd6d7f7d775
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105449698 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.2105449698
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2043660478
Short name T884
Test name
Test status
Simulation time 335125063 ps
CPU time 1.34 seconds
Started Jun 04 01:01:45 PM PDT 24
Finished Jun 04 01:01:47 PM PDT 24
Peak memory 201680 kb
Host smart-32c97cdd-0c6f-4e1c-a49f-151499ccb106
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043660478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.2043660478
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.78973040
Short name T822
Test name
Test status
Simulation time 472837269 ps
CPU time 1.75 seconds
Started Jun 04 01:01:45 PM PDT 24
Finished Jun 04 01:01:48 PM PDT 24
Peak memory 201640 kb
Host smart-677bcff3-a368-4def-8257-904075fba050
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78973040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.78973040
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.745176447
Short name T861
Test name
Test status
Simulation time 2497962632 ps
CPU time 2.62 seconds
Started Jun 04 01:01:45 PM PDT 24
Finished Jun 04 01:01:49 PM PDT 24
Peak memory 201796 kb
Host smart-8fbf84fa-2b4a-4104-9b04-1682877c9117
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745176447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ct
rl_same_csr_outstanding.745176447
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3096059484
Short name T835
Test name
Test status
Simulation time 428021859 ps
CPU time 1.9 seconds
Started Jun 04 01:01:44 PM PDT 24
Finished Jun 04 01:01:46 PM PDT 24
Peak memory 201928 kb
Host smart-f613d4bb-c3ee-4f11-afbe-331ed0d8da50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096059484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.3096059484
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1923816914
Short name T890
Test name
Test status
Simulation time 9085606504 ps
CPU time 8.15 seconds
Started Jun 04 01:01:45 PM PDT 24
Finished Jun 04 01:01:55 PM PDT 24
Peak memory 201964 kb
Host smart-7856a809-2c37-4373-85d0-6f0e1cc708ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923816914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.1923816914
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1450274231
Short name T832
Test name
Test status
Simulation time 600469340 ps
CPU time 1.16 seconds
Started Jun 04 01:01:45 PM PDT 24
Finished Jun 04 01:01:47 PM PDT 24
Peak memory 201728 kb
Host smart-95ac065a-a0f8-4dff-bee8-54de8cc467d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450274231 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.1450274231
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3234001318
Short name T125
Test name
Test status
Simulation time 475110942 ps
CPU time 1 seconds
Started Jun 04 01:01:45 PM PDT 24
Finished Jun 04 01:01:47 PM PDT 24
Peak memory 201712 kb
Host smart-406daf21-d4e3-4c04-9eec-41f19a1a45e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234001318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.3234001318
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.2204399742
Short name T800
Test name
Test status
Simulation time 396228904 ps
CPU time 1.11 seconds
Started Jun 04 01:01:45 PM PDT 24
Finished Jun 04 01:01:47 PM PDT 24
Peak memory 201716 kb
Host smart-4c0c3fcb-65a0-4d78-bf10-d5c69c9f76d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204399742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.2204399742
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2732130544
Short name T813
Test name
Test status
Simulation time 2466522135 ps
CPU time 5.83 seconds
Started Jun 04 01:01:43 PM PDT 24
Finished Jun 04 01:01:49 PM PDT 24
Peak memory 201748 kb
Host smart-07fe90ed-df08-4ac6-9a87-128089eaa5c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732130544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.2732130544
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.183524695
Short name T859
Test name
Test status
Simulation time 768015814 ps
CPU time 2.6 seconds
Started Jun 04 01:01:46 PM PDT 24
Finished Jun 04 01:01:50 PM PDT 24
Peak memory 217728 kb
Host smart-49b34935-5a25-40bd-8e52-cc04715bcab6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183524695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.183524695
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1505168361
Short name T874
Test name
Test status
Simulation time 3889504266 ps
CPU time 6.35 seconds
Started Jun 04 01:01:42 PM PDT 24
Finished Jun 04 01:01:49 PM PDT 24
Peak memory 201984 kb
Host smart-d09cf39d-e664-47d6-8abe-8e27ceeea43a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505168361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.1505168361
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.3751333085
Short name T474
Test name
Test status
Simulation time 467859306 ps
CPU time 1.12 seconds
Started Jun 04 01:52:29 PM PDT 24
Finished Jun 04 01:52:33 PM PDT 24
Peak memory 201392 kb
Host smart-26a826e3-16c1-481b-8f2f-3bc1ba2a4080
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751333085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.3751333085
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.756581157
Short name T592
Test name
Test status
Simulation time 260643581918 ps
CPU time 375.55 seconds
Started Jun 04 01:52:28 PM PDT 24
Finished Jun 04 01:58:46 PM PDT 24
Peak memory 201928 kb
Host smart-ed1c7946-1c07-4d11-ba52-62524f0c263d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756581157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gatin
g.756581157
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.4002740665
Short name T255
Test name
Test status
Simulation time 166171108777 ps
CPU time 221.83 seconds
Started Jun 04 01:52:28 PM PDT 24
Finished Jun 04 01:56:13 PM PDT 24
Peak memory 201704 kb
Host smart-81db6c64-911a-4b6e-a7e1-d33614720008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002740665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.4002740665
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.3627694794
Short name T539
Test name
Test status
Simulation time 171912544667 ps
CPU time 385.35 seconds
Started Jun 04 01:52:27 PM PDT 24
Finished Jun 04 01:58:54 PM PDT 24
Peak memory 201876 kb
Host smart-8e2640e1-e92e-430f-b2ba-90d4c199d1ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627694794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.3627694794
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.1267147082
Short name T107
Test name
Test status
Simulation time 165481711542 ps
CPU time 34.88 seconds
Started Jun 04 01:52:27 PM PDT 24
Finished Jun 04 01:53:05 PM PDT 24
Peak memory 201796 kb
Host smart-a0d058d1-5111-4d34-8496-b51fc6c2e6de
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267147082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.1267147082
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.1165636173
Short name T153
Test name
Test status
Simulation time 174362752187 ps
CPU time 448.45 seconds
Started Jun 04 01:52:27 PM PDT 24
Finished Jun 04 01:59:58 PM PDT 24
Peak memory 201776 kb
Host smart-87205927-0b2e-422b-ac79-ad44b5732130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165636173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.1165636173
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.1413855797
Short name T358
Test name
Test status
Simulation time 491893744215 ps
CPU time 1107.73 seconds
Started Jun 04 01:52:29 PM PDT 24
Finished Jun 04 02:10:59 PM PDT 24
Peak memory 201868 kb
Host smart-93cbcf1e-ea7c-405f-91b6-b7403ebf3457
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413855797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.1413855797
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.200243129
Short name T254
Test name
Test status
Simulation time 531619812324 ps
CPU time 308.09 seconds
Started Jun 04 01:52:25 PM PDT 24
Finished Jun 04 01:57:35 PM PDT 24
Peak memory 201716 kb
Host smart-fc066ed1-ecf9-4e78-a94e-94dae51b32ce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200243129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_w
akeup.200243129
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.4261860967
Short name T503
Test name
Test status
Simulation time 200993749688 ps
CPU time 242.8 seconds
Started Jun 04 01:52:32 PM PDT 24
Finished Jun 04 01:56:37 PM PDT 24
Peak memory 201752 kb
Host smart-d30ab976-ccf4-48e0-b5bb-88d264bc7a77
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261860967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.4261860967
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.328444679
Short name T47
Test name
Test status
Simulation time 130970237221 ps
CPU time 402.52 seconds
Started Jun 04 01:52:28 PM PDT 24
Finished Jun 04 01:59:13 PM PDT 24
Peak memory 202184 kb
Host smart-72895078-503d-40e3-8bfd-54079b6227dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328444679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.328444679
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.1839681044
Short name T9
Test name
Test status
Simulation time 40889878850 ps
CPU time 93.12 seconds
Started Jun 04 01:52:33 PM PDT 24
Finished Jun 04 01:54:08 PM PDT 24
Peak memory 201676 kb
Host smart-c4a9a627-e0aa-461f-9167-cd7b0f4c290a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839681044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.1839681044
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.1012937203
Short name T393
Test name
Test status
Simulation time 4761921652 ps
CPU time 11.55 seconds
Started Jun 04 01:52:33 PM PDT 24
Finished Jun 04 01:52:46 PM PDT 24
Peak memory 201544 kb
Host smart-a13afd58-5de4-48b0-bd20-b5e692fc525d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012937203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.1012937203
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.568444880
Short name T192
Test name
Test status
Simulation time 6124811760 ps
CPU time 4.59 seconds
Started Jun 04 01:52:34 PM PDT 24
Finished Jun 04 01:52:40 PM PDT 24
Peak memory 201640 kb
Host smart-2b0a72dd-2c26-422c-98fa-f0e5b1ea3ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568444880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.568444880
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.745270979
Short name T183
Test name
Test status
Simulation time 537091646321 ps
CPU time 1318.99 seconds
Started Jun 04 01:52:29 PM PDT 24
Finished Jun 04 02:14:31 PM PDT 24
Peak memory 201800 kb
Host smart-d1dacb27-07ec-442b-98b0-5a3b1cc9ceb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745270979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.745270979
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.3060346815
Short name T678
Test name
Test status
Simulation time 454237614 ps
CPU time 0.71 seconds
Started Jun 04 01:52:35 PM PDT 24
Finished Jun 04 01:52:38 PM PDT 24
Peak memory 201480 kb
Host smart-2fe3448e-eaab-485f-962b-cef72943de16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060346815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.3060346815
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.259200309
Short name T206
Test name
Test status
Simulation time 561946202265 ps
CPU time 249.03 seconds
Started Jun 04 01:52:36 PM PDT 24
Finished Jun 04 01:56:46 PM PDT 24
Peak memory 201864 kb
Host smart-126ffc89-7bea-4b7e-9fe7-f21c872aabf4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259200309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gatin
g.259200309
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.584296316
Short name T279
Test name
Test status
Simulation time 518415247320 ps
CPU time 1201.01 seconds
Started Jun 04 01:52:34 PM PDT 24
Finished Jun 04 02:12:37 PM PDT 24
Peak memory 201832 kb
Host smart-3e51b1f7-2aef-4622-a2cc-85ccc3e5f10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584296316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.584296316
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.2935197971
Short name T774
Test name
Test status
Simulation time 496199993768 ps
CPU time 604.96 seconds
Started Jun 04 01:52:36 PM PDT 24
Finished Jun 04 02:02:42 PM PDT 24
Peak memory 201736 kb
Host smart-56c54d4b-e35f-4124-966e-92d193feda37
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935197971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.2935197971
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.2327698969
Short name T182
Test name
Test status
Simulation time 500704886467 ps
CPU time 627.85 seconds
Started Jun 04 01:52:26 PM PDT 24
Finished Jun 04 02:02:56 PM PDT 24
Peak memory 201852 kb
Host smart-1dca7fcf-d916-4e5b-9c9f-c8e6c5a8fa04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327698969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.2327698969
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.261337862
Short name T641
Test name
Test status
Simulation time 163233344262 ps
CPU time 36.26 seconds
Started Jun 04 01:52:35 PM PDT 24
Finished Jun 04 01:53:13 PM PDT 24
Peak memory 201724 kb
Host smart-c69997a3-118c-4e6a-9425-0f7c312ee7ba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=261337862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixed
.261337862
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.3878718574
Short name T33
Test name
Test status
Simulation time 170562492377 ps
CPU time 205.6 seconds
Started Jun 04 01:52:29 PM PDT 24
Finished Jun 04 01:55:57 PM PDT 24
Peak memory 201868 kb
Host smart-94184cc8-6d56-4c1c-8467-30c0d81d43a1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878718574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.3878718574
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.3712433578
Short name T537
Test name
Test status
Simulation time 386701005442 ps
CPU time 221.65 seconds
Started Jun 04 01:52:29 PM PDT 24
Finished Jun 04 01:56:13 PM PDT 24
Peak memory 201768 kb
Host smart-503ed15e-2b09-4491-ac18-8679d5145b13
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712433578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.3712433578
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.1991248600
Short name T447
Test name
Test status
Simulation time 122155133907 ps
CPU time 621.49 seconds
Started Jun 04 01:52:28 PM PDT 24
Finished Jun 04 02:02:52 PM PDT 24
Peak memory 202088 kb
Host smart-381c065f-6160-4eec-bc9f-167affc901a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991248600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.1991248600
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.2911029263
Short name T399
Test name
Test status
Simulation time 21729452806 ps
CPU time 13.25 seconds
Started Jun 04 01:52:34 PM PDT 24
Finished Jun 04 01:52:49 PM PDT 24
Peak memory 201564 kb
Host smart-af28e7c7-a438-4da8-ac65-d8bae091be1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911029263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.2911029263
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.3195237285
Short name T419
Test name
Test status
Simulation time 4040356994 ps
CPU time 2.17 seconds
Started Jun 04 01:52:30 PM PDT 24
Finished Jun 04 01:52:34 PM PDT 24
Peak memory 201628 kb
Host smart-63300639-8f23-4630-aa77-f63a7fdf618b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195237285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.3195237285
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.1449287089
Short name T78
Test name
Test status
Simulation time 8115745600 ps
CPU time 10.68 seconds
Started Jun 04 01:52:31 PM PDT 24
Finished Jun 04 01:52:44 PM PDT 24
Peak memory 218344 kb
Host smart-652812a4-e999-49f6-a704-5a27c563dd3e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449287089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.1449287089
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.3165189991
Short name T397
Test name
Test status
Simulation time 5475442051 ps
CPU time 13.71 seconds
Started Jun 04 01:52:27 PM PDT 24
Finished Jun 04 01:52:44 PM PDT 24
Peak memory 201636 kb
Host smart-120ac06e-11f9-459c-87e7-93830fbc6eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165189991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.3165189991
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.1467810850
Short name T413
Test name
Test status
Simulation time 166802117112 ps
CPU time 609.96 seconds
Started Jun 04 01:52:30 PM PDT 24
Finished Jun 04 02:02:42 PM PDT 24
Peak memory 210320 kb
Host smart-ee23d4af-ea93-4c6d-aabf-ee9813779142
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467810850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
1467810850
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.1593630443
Short name T25
Test name
Test status
Simulation time 44924680978 ps
CPU time 223.81 seconds
Started Jun 04 01:52:30 PM PDT 24
Finished Jun 04 01:56:16 PM PDT 24
Peak memory 210404 kb
Host smart-3bba62df-ba8e-4e19-9521-1ee4bff66371
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593630443 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.1593630443
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.3959552619
Short name T636
Test name
Test status
Simulation time 426889653 ps
CPU time 1.56 seconds
Started Jun 04 01:52:58 PM PDT 24
Finished Jun 04 01:53:00 PM PDT 24
Peak memory 201424 kb
Host smart-d7431d66-1190-489b-995b-ea5fe3b59751
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959552619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.3959552619
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.1783347364
Short name T723
Test name
Test status
Simulation time 327131792716 ps
CPU time 185.23 seconds
Started Jun 04 01:52:55 PM PDT 24
Finished Jun 04 01:56:02 PM PDT 24
Peak memory 201840 kb
Host smart-f6ccc985-b165-4aa1-94e6-205658a554f5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783347364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.1783347364
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.2925654303
Short name T167
Test name
Test status
Simulation time 168158275291 ps
CPU time 374.94 seconds
Started Jun 04 01:52:52 PM PDT 24
Finished Jun 04 01:59:08 PM PDT 24
Peak memory 201768 kb
Host smart-5676900e-bab7-4f0c-8248-ea5b2c97b2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925654303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.2925654303
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.3842087707
Short name T551
Test name
Test status
Simulation time 492780342689 ps
CPU time 1204.87 seconds
Started Jun 04 01:53:09 PM PDT 24
Finished Jun 04 02:13:15 PM PDT 24
Peak memory 201808 kb
Host smart-bbeef3a5-657c-4e85-89c6-af013a13ad2c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842087707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.3842087707
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.292117700
Short name T304
Test name
Test status
Simulation time 163416075867 ps
CPU time 385.85 seconds
Started Jun 04 01:52:51 PM PDT 24
Finished Jun 04 01:59:19 PM PDT 24
Peak memory 201816 kb
Host smart-015b05f6-839d-4181-9793-5586046bae04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292117700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.292117700
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.1324757549
Short name T732
Test name
Test status
Simulation time 157862534487 ps
CPU time 374.82 seconds
Started Jun 04 01:52:52 PM PDT 24
Finished Jun 04 01:59:08 PM PDT 24
Peak memory 201764 kb
Host smart-03f7b5a4-0563-414a-87c3-aec4b40d3853
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324757549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.1324757549
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.712193317
Short name T600
Test name
Test status
Simulation time 545872025205 ps
CPU time 636.93 seconds
Started Jun 04 01:53:03 PM PDT 24
Finished Jun 04 02:03:41 PM PDT 24
Peak memory 201844 kb
Host smart-85522d3f-5616-4e45-9628-3b5e1d9a4163
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712193317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_
wakeup.712193317
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.1186421513
Short name T505
Test name
Test status
Simulation time 588535140758 ps
CPU time 283.1 seconds
Started Jun 04 01:53:03 PM PDT 24
Finished Jun 04 01:57:47 PM PDT 24
Peak memory 201808 kb
Host smart-6c41151d-724e-421c-8326-ba2a4f01a65d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186421513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.1186421513
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.326393038
Short name T572
Test name
Test status
Simulation time 112812917238 ps
CPU time 388.45 seconds
Started Jun 04 01:53:03 PM PDT 24
Finished Jun 04 01:59:33 PM PDT 24
Peak memory 202180 kb
Host smart-78901f29-eb3d-4648-9802-7a8d509d22c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326393038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.326393038
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.1137771041
Short name T368
Test name
Test status
Simulation time 39675175516 ps
CPU time 91.55 seconds
Started Jun 04 01:53:04 PM PDT 24
Finished Jun 04 01:54:37 PM PDT 24
Peak memory 201608 kb
Host smart-dda16b6c-6d87-40f6-9a23-9eb6ffeb1ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137771041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.1137771041
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.3300794674
Short name T389
Test name
Test status
Simulation time 3854131252 ps
CPU time 3.2 seconds
Started Jun 04 01:52:59 PM PDT 24
Finished Jun 04 01:53:04 PM PDT 24
Peak memory 201608 kb
Host smart-d494c48b-3e58-43ba-b8bb-a690a758b70e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300794674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.3300794674
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.2743107168
Short name T660
Test name
Test status
Simulation time 5973507450 ps
CPU time 4.36 seconds
Started Jun 04 01:52:59 PM PDT 24
Finished Jun 04 01:53:04 PM PDT 24
Peak memory 201616 kb
Host smart-c378bdfb-3bdb-481a-b04e-cf2d335e3d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743107168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.2743107168
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.860993712
Short name T619
Test name
Test status
Simulation time 375223712751 ps
CPU time 147.42 seconds
Started Jun 04 01:52:58 PM PDT 24
Finished Jun 04 01:55:26 PM PDT 24
Peak memory 201876 kb
Host smart-37f66cae-bbcc-40e9-b647-56f8f1d1957d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860993712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all.
860993712
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.3592122554
Short name T649
Test name
Test status
Simulation time 405077154 ps
CPU time 1.57 seconds
Started Jun 04 01:52:54 PM PDT 24
Finished Jun 04 01:52:57 PM PDT 24
Peak memory 201508 kb
Host smart-4b5d249f-710f-4575-b2b8-c6dcb2a2c7ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592122554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.3592122554
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.2872859158
Short name T586
Test name
Test status
Simulation time 349669919679 ps
CPU time 553.5 seconds
Started Jun 04 01:52:55 PM PDT 24
Finished Jun 04 02:02:10 PM PDT 24
Peak memory 201784 kb
Host smart-7f579247-89bd-4f00-814b-575fd6961bbd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872859158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.2872859158
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.4129649767
Short name T320
Test name
Test status
Simulation time 493417222727 ps
CPU time 1112.01 seconds
Started Jun 04 01:52:54 PM PDT 24
Finished Jun 04 02:11:28 PM PDT 24
Peak memory 201852 kb
Host smart-53e5197a-4117-4f16-b906-aab04a37c589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129649767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.4129649767
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.2532911900
Short name T584
Test name
Test status
Simulation time 328088026575 ps
CPU time 373.89 seconds
Started Jun 04 01:52:55 PM PDT 24
Finished Jun 04 01:59:10 PM PDT 24
Peak memory 201784 kb
Host smart-5fd5f395-84a9-45eb-8515-46d075378727
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532911900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.2532911900
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.476764325
Short name T782
Test name
Test status
Simulation time 322390957145 ps
CPU time 756.12 seconds
Started Jun 04 01:52:51 PM PDT 24
Finished Jun 04 02:05:30 PM PDT 24
Peak memory 201712 kb
Host smart-db1cad11-2dd2-4f22-9ce9-d28e7b4ca7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476764325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.476764325
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.342489001
Short name T433
Test name
Test status
Simulation time 163961094935 ps
CPU time 99.34 seconds
Started Jun 04 01:52:55 PM PDT 24
Finished Jun 04 01:54:35 PM PDT 24
Peak memory 201788 kb
Host smart-886025b9-994c-400d-b2cd-1554af2ec472
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=342489001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fixe
d.342489001
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.953552503
Short name T531
Test name
Test status
Simulation time 187754678442 ps
CPU time 50.64 seconds
Started Jun 04 01:53:04 PM PDT 24
Finished Jun 04 01:53:55 PM PDT 24
Peak memory 201864 kb
Host smart-73c08363-f10c-45d3-bf63-9b79032abbe6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953552503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_
wakeup.953552503
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.1331303441
Short name T644
Test name
Test status
Simulation time 619222129075 ps
CPU time 758.04 seconds
Started Jun 04 01:53:01 PM PDT 24
Finished Jun 04 02:05:40 PM PDT 24
Peak memory 201816 kb
Host smart-1f1461a9-ecf6-43b0-be8d-ba62dba57405
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331303441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.1331303441
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.2849133059
Short name T226
Test name
Test status
Simulation time 132213733247 ps
CPU time 664.66 seconds
Started Jun 04 01:52:56 PM PDT 24
Finished Jun 04 02:04:01 PM PDT 24
Peak memory 201808 kb
Host smart-c9cfca91-e7e1-4452-bb5a-0ec13ce44cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849133059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.2849133059
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.2229074628
Short name T483
Test name
Test status
Simulation time 28109149126 ps
CPU time 37.31 seconds
Started Jun 04 01:53:08 PM PDT 24
Finished Jun 04 01:53:47 PM PDT 24
Peak memory 201644 kb
Host smart-81cc7369-4f2e-4821-9628-ce525fdf66bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229074628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.2229074628
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.1041429289
Short name T196
Test name
Test status
Simulation time 3608797513 ps
CPU time 8.76 seconds
Started Jun 04 01:52:51 PM PDT 24
Finished Jun 04 01:53:01 PM PDT 24
Peak memory 201588 kb
Host smart-e9d1a608-1e7c-43cc-9875-56a402a4e95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041429289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.1041429289
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.2924731772
Short name T790
Test name
Test status
Simulation time 5782048418 ps
CPU time 2.35 seconds
Started Jun 04 01:52:58 PM PDT 24
Finished Jun 04 01:53:01 PM PDT 24
Peak memory 201632 kb
Host smart-211de8ce-54d5-415e-9c8e-ffd9cf69ee63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924731772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.2924731772
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.1228104140
Short name T104
Test name
Test status
Simulation time 322777912043 ps
CPU time 396.77 seconds
Started Jun 04 01:52:57 PM PDT 24
Finished Jun 04 01:59:35 PM PDT 24
Peak memory 201776 kb
Host smart-e7f4acb5-f746-4b96-bdb9-e3d1f9a4f70f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228104140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.1228104140
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.2967632639
Short name T340
Test name
Test status
Simulation time 252692049727 ps
CPU time 49.89 seconds
Started Jun 04 01:52:59 PM PDT 24
Finished Jun 04 01:53:50 PM PDT 24
Peak memory 210120 kb
Host smart-dbd6584c-ead6-492d-8daf-0dedcc5011a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967632639 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.2967632639
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.45760183
Short name T786
Test name
Test status
Simulation time 344514362934 ps
CPU time 830.71 seconds
Started Jun 04 01:52:56 PM PDT 24
Finished Jun 04 02:06:48 PM PDT 24
Peak memory 201504 kb
Host smart-ccca2adc-42c7-492f-ac29-413315895d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45760183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.45760183
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.1637917491
Short name T506
Test name
Test status
Simulation time 329917807543 ps
CPU time 313.35 seconds
Started Jun 04 01:53:00 PM PDT 24
Finished Jun 04 01:58:14 PM PDT 24
Peak memory 201724 kb
Host smart-95351f02-cb06-4e1b-b6ae-02a1bc929541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637917491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.1637917491
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.3554831155
Short name T545
Test name
Test status
Simulation time 162226175643 ps
CPU time 94.41 seconds
Started Jun 04 01:52:56 PM PDT 24
Finished Jun 04 01:54:31 PM PDT 24
Peak memory 201808 kb
Host smart-86cdbf93-cea1-473f-94ed-67901c7b5311
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554831155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.3554831155
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.675613766
Short name T203
Test name
Test status
Simulation time 171710879103 ps
CPU time 215.79 seconds
Started Jun 04 01:53:07 PM PDT 24
Finished Jun 04 01:56:44 PM PDT 24
Peak memory 201780 kb
Host smart-e86c5a1f-e279-4eda-a48f-a564bbd4cfc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675613766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.675613766
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.2915409217
Short name T188
Test name
Test status
Simulation time 163451420126 ps
CPU time 37.28 seconds
Started Jun 04 01:53:01 PM PDT 24
Finished Jun 04 01:53:39 PM PDT 24
Peak memory 201764 kb
Host smart-236ac6a4-f743-43aa-b794-3b24f274c2dc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915409217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.2915409217
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.676770651
Short name T84
Test name
Test status
Simulation time 420203766005 ps
CPU time 57.8 seconds
Started Jun 04 01:53:08 PM PDT 24
Finished Jun 04 01:54:08 PM PDT 24
Peak memory 201744 kb
Host smart-d340f40d-e962-49c2-8583-2f30ec932654
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676770651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
adc_ctrl_filters_wakeup_fixed.676770651
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.3223906326
Short name T515
Test name
Test status
Simulation time 46457417382 ps
CPU time 74.75 seconds
Started Jun 04 01:53:05 PM PDT 24
Finished Jun 04 01:54:21 PM PDT 24
Peak memory 201628 kb
Host smart-6405116d-4cc9-4e3f-91fe-31471fae02f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223906326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.3223906326
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.1604037205
Short name T400
Test name
Test status
Simulation time 4431402866 ps
CPU time 10.92 seconds
Started Jun 04 01:53:03 PM PDT 24
Finished Jun 04 01:53:15 PM PDT 24
Peak memory 201608 kb
Host smart-0d19f5a0-690b-4b1b-b3f8-2eba2605c735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604037205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.1604037205
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.1057174768
Short name T609
Test name
Test status
Simulation time 5900487502 ps
CPU time 3.14 seconds
Started Jun 04 01:53:04 PM PDT 24
Finished Jun 04 01:53:08 PM PDT 24
Peak memory 201640 kb
Host smart-e4d563ae-dfa6-4c72-ab75-a1a8955d54c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057174768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.1057174768
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.3533627800
Short name T310
Test name
Test status
Simulation time 279418905193 ps
CPU time 580.22 seconds
Started Jun 04 01:53:09 PM PDT 24
Finished Jun 04 02:02:51 PM PDT 24
Peak memory 210428 kb
Host smart-e19af61f-dc9c-46f6-b9ec-93924af79ba6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533627800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.3533627800
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.314475150
Short name T388
Test name
Test status
Simulation time 391008176 ps
CPU time 1.47 seconds
Started Jun 04 01:53:01 PM PDT 24
Finished Jun 04 01:53:03 PM PDT 24
Peak memory 201500 kb
Host smart-8794390d-536b-4cb9-bbb6-10648e41feda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314475150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.314475150
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.2115604850
Short name T313
Test name
Test status
Simulation time 167198010579 ps
CPU time 101.51 seconds
Started Jun 04 01:53:00 PM PDT 24
Finished Jun 04 01:54:42 PM PDT 24
Peak memory 201812 kb
Host smart-0ac22244-5f48-47bc-abdc-cb65978e2f54
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115604850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.2115604850
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.279769820
Short name T616
Test name
Test status
Simulation time 509043075533 ps
CPU time 1251.9 seconds
Started Jun 04 01:53:03 PM PDT 24
Finished Jun 04 02:13:56 PM PDT 24
Peak memory 201800 kb
Host smart-a0173acf-a4f3-473b-98ff-0c7d9affdd78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279769820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.279769820
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.3872308980
Short name T427
Test name
Test status
Simulation time 167351505588 ps
CPU time 101.03 seconds
Started Jun 04 01:53:07 PM PDT 24
Finished Jun 04 01:54:49 PM PDT 24
Peak memory 201820 kb
Host smart-47f40ebc-9de8-4832-be89-ee2331efaf1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872308980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.3872308980
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.3998230216
Short name T484
Test name
Test status
Simulation time 158823730857 ps
CPU time 372.88 seconds
Started Jun 04 01:53:00 PM PDT 24
Finished Jun 04 01:59:14 PM PDT 24
Peak memory 201820 kb
Host smart-285b0371-7d93-4617-b194-e652304cd07c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998230216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.3998230216
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.85828829
Short name T652
Test name
Test status
Simulation time 160563804685 ps
CPU time 151.38 seconds
Started Jun 04 01:53:08 PM PDT 24
Finished Jun 04 01:55:41 PM PDT 24
Peak memory 201836 kb
Host smart-60ef9737-5a2b-4ccc-8bf9-7400221c239d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85828829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.85828829
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.446713990
Short name T589
Test name
Test status
Simulation time 167681078822 ps
CPU time 375.56 seconds
Started Jun 04 01:53:11 PM PDT 24
Finished Jun 04 01:59:27 PM PDT 24
Peak memory 201800 kb
Host smart-4f7548a7-40aa-47a2-89df-abe216190bba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=446713990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fixe
d.446713990
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.1059884249
Short name T173
Test name
Test status
Simulation time 366601678790 ps
CPU time 443.01 seconds
Started Jun 04 01:53:04 PM PDT 24
Finished Jun 04 02:00:29 PM PDT 24
Peak memory 201692 kb
Host smart-48a9a166-dc4d-409c-a92d-e4500bff4e05
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059884249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.1059884249
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.3848378448
Short name T683
Test name
Test status
Simulation time 198755480587 ps
CPU time 48.61 seconds
Started Jun 04 01:53:03 PM PDT 24
Finished Jun 04 01:53:53 PM PDT 24
Peak memory 201752 kb
Host smart-2d2a4a98-eb43-47e6-b8ec-5d16c2ad3137
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848378448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.3848378448
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.3507844106
Short name T593
Test name
Test status
Simulation time 127404865673 ps
CPU time 450.22 seconds
Started Jun 04 01:53:01 PM PDT 24
Finished Jun 04 02:00:32 PM PDT 24
Peak memory 202184 kb
Host smart-084f6ebc-0d66-426e-b2e6-818cc23594c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507844106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.3507844106
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.786476823
Short name T634
Test name
Test status
Simulation time 35646584037 ps
CPU time 76.31 seconds
Started Jun 04 01:53:06 PM PDT 24
Finished Jun 04 01:54:23 PM PDT 24
Peak memory 201620 kb
Host smart-e5bd4117-4607-429c-a0a0-67d5905f1806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786476823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.786476823
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.3832787009
Short name T151
Test name
Test status
Simulation time 5594343670 ps
CPU time 2.17 seconds
Started Jun 04 01:53:04 PM PDT 24
Finished Jun 04 01:53:07 PM PDT 24
Peak memory 201620 kb
Host smart-23a6fb5f-7f7f-4ac6-bed5-06d1c028eac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832787009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.3832787009
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.1047644770
Short name T363
Test name
Test status
Simulation time 5985720303 ps
CPU time 14.88 seconds
Started Jun 04 01:53:08 PM PDT 24
Finished Jun 04 01:53:25 PM PDT 24
Peak memory 201632 kb
Host smart-94417d16-6603-4549-a592-db471dd6ff5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047644770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.1047644770
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.1493952053
Short name T715
Test name
Test status
Simulation time 199308301939 ps
CPU time 226.16 seconds
Started Jun 04 01:53:08 PM PDT 24
Finished Jun 04 01:56:56 PM PDT 24
Peak memory 201836 kb
Host smart-3804b357-91de-41d1-ae9c-c1ec1af68ea1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493952053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.1493952053
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.2279639092
Short name T729
Test name
Test status
Simulation time 68093752157 ps
CPU time 114.66 seconds
Started Jun 04 01:53:08 PM PDT 24
Finished Jun 04 01:55:04 PM PDT 24
Peak memory 210192 kb
Host smart-ff404aeb-9ae2-4192-ad3e-eb54bd67bb01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279639092 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.2279639092
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.3433677158
Short name T365
Test name
Test status
Simulation time 378566477 ps
CPU time 1.62 seconds
Started Jun 04 01:53:02 PM PDT 24
Finished Jun 04 01:53:04 PM PDT 24
Peak memory 201472 kb
Host smart-df811b54-ec12-4112-9ddf-8b1441907017
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433677158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.3433677158
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.3649938409
Short name T251
Test name
Test status
Simulation time 175862463768 ps
CPU time 75.22 seconds
Started Jun 04 01:53:06 PM PDT 24
Finished Jun 04 01:54:23 PM PDT 24
Peak memory 201864 kb
Host smart-35d5543a-1c0c-41e5-bdc3-67887128b8c9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649938409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.3649938409
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.1361437447
Short name T791
Test name
Test status
Simulation time 318639924326 ps
CPU time 361.85 seconds
Started Jun 04 01:53:08 PM PDT 24
Finished Jun 04 01:59:12 PM PDT 24
Peak memory 201788 kb
Host smart-fde683b2-d29f-4ae9-a213-8ed9a49a8237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361437447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.1361437447
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.2211287095
Short name T779
Test name
Test status
Simulation time 172158332737 ps
CPU time 110.86 seconds
Started Jun 04 01:53:02 PM PDT 24
Finished Jun 04 01:54:54 PM PDT 24
Peak memory 201856 kb
Host smart-1a94a4f2-228f-4174-8f9a-b96604f5e9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211287095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.2211287095
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.2674582847
Short name T402
Test name
Test status
Simulation time 331986953864 ps
CPU time 387.09 seconds
Started Jun 04 01:53:07 PM PDT 24
Finished Jun 04 01:59:36 PM PDT 24
Peak memory 201772 kb
Host smart-f4b491f9-1b32-4cd9-85a6-af2836583c2e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674582847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.2674582847
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.3795131476
Short name T207
Test name
Test status
Simulation time 322060659862 ps
CPU time 763.3 seconds
Started Jun 04 01:53:05 PM PDT 24
Finished Jun 04 02:05:49 PM PDT 24
Peak memory 201820 kb
Host smart-8b005218-3046-42f8-baeb-b70a93f73857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795131476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.3795131476
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.2577836938
Short name T718
Test name
Test status
Simulation time 165465600096 ps
CPU time 149.06 seconds
Started Jun 04 01:53:05 PM PDT 24
Finished Jun 04 01:55:35 PM PDT 24
Peak memory 201688 kb
Host smart-7495659f-759e-40ba-bf6e-7154d21f86d3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577836938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.2577836938
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.3256982645
Short name T523
Test name
Test status
Simulation time 190113792301 ps
CPU time 114.92 seconds
Started Jun 04 01:53:01 PM PDT 24
Finished Jun 04 01:54:57 PM PDT 24
Peak memory 201812 kb
Host smart-60b2c4fa-bd2e-4fc3-9a61-3b79c3fd0682
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256982645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.3256982645
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.1842161854
Short name T179
Test name
Test status
Simulation time 78242131940 ps
CPU time 261.7 seconds
Started Jun 04 01:53:02 PM PDT 24
Finished Jun 04 01:57:24 PM PDT 24
Peak memory 202168 kb
Host smart-867d3d24-1847-4084-90fe-f04d01885b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842161854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.1842161854
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.4153763914
Short name T621
Test name
Test status
Simulation time 35674109448 ps
CPU time 84.33 seconds
Started Jun 04 01:53:05 PM PDT 24
Finished Jun 04 01:54:30 PM PDT 24
Peak memory 201480 kb
Host smart-e849971d-783d-49a1-8911-fd542a92296b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153763914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.4153763914
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.393305628
Short name T141
Test name
Test status
Simulation time 3806914201 ps
CPU time 5.46 seconds
Started Jun 04 01:53:05 PM PDT 24
Finished Jun 04 01:53:12 PM PDT 24
Peak memory 201620 kb
Host smart-700b74d1-4844-4381-ac7f-4a9470070a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393305628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.393305628
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.2476408198
Short name T120
Test name
Test status
Simulation time 5706043251 ps
CPU time 15.14 seconds
Started Jun 04 01:53:02 PM PDT 24
Finished Jun 04 01:53:18 PM PDT 24
Peak memory 201604 kb
Host smart-596fd84d-6fcc-4b7f-85cc-4753ab68c993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476408198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.2476408198
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.591746033
Short name T494
Test name
Test status
Simulation time 177159093794 ps
CPU time 368.9 seconds
Started Jun 04 01:53:04 PM PDT 24
Finished Jun 04 01:59:14 PM PDT 24
Peak memory 201844 kb
Host smart-71230ad1-b445-4d1e-b7d6-6798d7752656
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591746033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all.
591746033
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.1770222868
Short name T522
Test name
Test status
Simulation time 510278608 ps
CPU time 1.81 seconds
Started Jun 04 01:53:08 PM PDT 24
Finished Jun 04 01:53:11 PM PDT 24
Peak memory 201520 kb
Host smart-5e8c8cf8-c225-4979-8765-bcf8fa24924f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770222868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.1770222868
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.1409849234
Short name T293
Test name
Test status
Simulation time 335139715322 ps
CPU time 522.45 seconds
Started Jun 04 01:53:10 PM PDT 24
Finished Jun 04 02:01:53 PM PDT 24
Peak memory 201792 kb
Host smart-737bc3bc-bb9d-43da-ace6-1ef498b27cfb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409849234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.1409849234
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.1934178675
Short name T569
Test name
Test status
Simulation time 497346240190 ps
CPU time 1290.89 seconds
Started Jun 04 01:53:04 PM PDT 24
Finished Jun 04 02:14:37 PM PDT 24
Peak memory 201772 kb
Host smart-74780609-563e-4395-a87b-9cfe6e07bb33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934178675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.1934178675
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.412868968
Short name T719
Test name
Test status
Simulation time 163500086125 ps
CPU time 183.39 seconds
Started Jun 04 01:53:00 PM PDT 24
Finished Jun 04 01:56:04 PM PDT 24
Peak memory 201804 kb
Host smart-710c346b-bfc6-41f6-9f1e-3c39819610fa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=412868968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrup
t_fixed.412868968
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.1831386859
Short name T272
Test name
Test status
Simulation time 319058416521 ps
CPU time 762.85 seconds
Started Jun 04 01:53:04 PM PDT 24
Finished Jun 04 02:05:48 PM PDT 24
Peak memory 201760 kb
Host smart-432411dc-0a57-478e-be7c-19bde4645361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831386859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.1831386859
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.1895401497
Short name T502
Test name
Test status
Simulation time 332197868502 ps
CPU time 193.05 seconds
Started Jun 04 01:53:04 PM PDT 24
Finished Jun 04 01:56:18 PM PDT 24
Peak memory 201772 kb
Host smart-3923e92f-739d-459d-80a3-cb08e5dff610
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895401497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.1895401497
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.1513213021
Short name T533
Test name
Test status
Simulation time 598024215864 ps
CPU time 79.28 seconds
Started Jun 04 01:53:10 PM PDT 24
Finished Jun 04 01:54:31 PM PDT 24
Peak memory 201792 kb
Host smart-5c6a7532-b0ad-4b69-975d-4144ca4f8e6f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513213021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.1513213021
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.198352961
Short name T221
Test name
Test status
Simulation time 103419769403 ps
CPU time 563.78 seconds
Started Jun 04 01:52:58 PM PDT 24
Finished Jun 04 02:02:23 PM PDT 24
Peak memory 202172 kb
Host smart-ecfd2084-7118-4f57-9c31-7ce48ce9045b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198352961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.198352961
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.3034979543
Short name T783
Test name
Test status
Simulation time 25645382394 ps
CPU time 16.81 seconds
Started Jun 04 01:53:10 PM PDT 24
Finished Jun 04 01:53:28 PM PDT 24
Peak memory 201616 kb
Host smart-21df3d97-4fe0-4749-a7f3-cd6a7288bb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034979543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.3034979543
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.3190793164
Short name T174
Test name
Test status
Simulation time 4187398093 ps
CPU time 3.11 seconds
Started Jun 04 01:53:08 PM PDT 24
Finished Jun 04 01:53:13 PM PDT 24
Peak memory 201608 kb
Host smart-bc7a9617-ae4f-4551-a7ce-b9d9058aff60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190793164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.3190793164
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.3290520148
Short name T29
Test name
Test status
Simulation time 6039353395 ps
CPU time 12.55 seconds
Started Jun 04 01:53:07 PM PDT 24
Finished Jun 04 01:53:21 PM PDT 24
Peak memory 201636 kb
Host smart-c37cf67c-bfee-45e1-840b-c03285c99e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290520148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.3290520148
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.2138099711
Short name T184
Test name
Test status
Simulation time 553353752935 ps
CPU time 449.47 seconds
Started Jun 04 01:53:10 PM PDT 24
Finished Jun 04 02:00:41 PM PDT 24
Peak memory 201824 kb
Host smart-37c8f95a-7265-43aa-88ad-639f6f85c5d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138099711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.2138099711
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.1911355799
Short name T22
Test name
Test status
Simulation time 60845394221 ps
CPU time 26.68 seconds
Started Jun 04 01:53:10 PM PDT 24
Finished Jun 04 01:53:38 PM PDT 24
Peak memory 210492 kb
Host smart-7b7a4c48-fd76-44e5-abaa-c0301a636dbe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911355799 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.1911355799
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.410400589
Short name T412
Test name
Test status
Simulation time 375528851 ps
CPU time 1.04 seconds
Started Jun 04 01:53:03 PM PDT 24
Finished Jun 04 01:53:05 PM PDT 24
Peak memory 201504 kb
Host smart-49e14efc-4675-447c-ac89-a8928baf58a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410400589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.410400589
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.4073274841
Short name T794
Test name
Test status
Simulation time 335664736626 ps
CPU time 375.47 seconds
Started Jun 04 01:53:10 PM PDT 24
Finished Jun 04 01:59:27 PM PDT 24
Peak memory 201708 kb
Host smart-afba34f5-b885-49ad-8a36-3f638bd4f4d3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073274841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.4073274841
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.3249089153
Short name T325
Test name
Test status
Simulation time 350136797650 ps
CPU time 201.33 seconds
Started Jun 04 01:53:07 PM PDT 24
Finished Jun 04 01:56:30 PM PDT 24
Peak memory 201764 kb
Host smart-aa45df17-1452-4735-8b7e-fbbb920625b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249089153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.3249089153
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.919632917
Short name T229
Test name
Test status
Simulation time 329616291433 ps
CPU time 110.94 seconds
Started Jun 04 01:53:11 PM PDT 24
Finished Jun 04 01:55:03 PM PDT 24
Peak memory 201748 kb
Host smart-37ee3e30-c8ba-4c9a-a5e6-068afb2aa0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919632917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.919632917
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.1546109227
Short name T445
Test name
Test status
Simulation time 496053397037 ps
CPU time 1116.99 seconds
Started Jun 04 01:53:06 PM PDT 24
Finished Jun 04 02:11:44 PM PDT 24
Peak memory 201788 kb
Host smart-c058ba14-57a4-4e68-862c-d0a07c1e6344
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546109227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.1546109227
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.3804771361
Short name T705
Test name
Test status
Simulation time 328634902644 ps
CPU time 208.96 seconds
Started Jun 04 01:53:06 PM PDT 24
Finished Jun 04 01:56:35 PM PDT 24
Peak memory 201792 kb
Host smart-2fa2a5c0-c455-4e70-9dea-5872ac87abf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804771361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.3804771361
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.658088340
Short name T559
Test name
Test status
Simulation time 172326916081 ps
CPU time 396.71 seconds
Started Jun 04 01:53:08 PM PDT 24
Finished Jun 04 01:59:46 PM PDT 24
Peak memory 201856 kb
Host smart-2c50892c-b7b8-4e4e-a672-7d1106a3b281
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=658088340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fixe
d.658088340
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.716175734
Short name T253
Test name
Test status
Simulation time 361074349655 ps
CPU time 207.72 seconds
Started Jun 04 01:53:11 PM PDT 24
Finished Jun 04 01:56:40 PM PDT 24
Peak memory 201852 kb
Host smart-5ac92c26-7550-47bf-9b0f-fd3347b2b58e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716175734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_
wakeup.716175734
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.4075256589
Short name T657
Test name
Test status
Simulation time 217435197083 ps
CPU time 31.95 seconds
Started Jun 04 01:53:12 PM PDT 24
Finished Jun 04 01:53:45 PM PDT 24
Peak memory 201732 kb
Host smart-8990ec69-c278-4543-9ee6-750095c15f53
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075256589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.4075256589
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.340416637
Short name T435
Test name
Test status
Simulation time 91468084065 ps
CPU time 488.51 seconds
Started Jun 04 01:53:03 PM PDT 24
Finished Jun 04 02:01:12 PM PDT 24
Peak memory 202020 kb
Host smart-fbf91007-b3ee-4fe0-927f-30a0aa998877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340416637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.340416637
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.3913215035
Short name T504
Test name
Test status
Simulation time 44058524728 ps
CPU time 106.86 seconds
Started Jun 04 01:53:01 PM PDT 24
Finished Jun 04 01:54:49 PM PDT 24
Peak memory 201588 kb
Host smart-f137447e-53b5-434b-bf6f-615f95a28311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913215035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.3913215035
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.844266507
Short name T374
Test name
Test status
Simulation time 4906219461 ps
CPU time 12.64 seconds
Started Jun 04 01:53:06 PM PDT 24
Finished Jun 04 01:53:19 PM PDT 24
Peak memory 201504 kb
Host smart-0971e486-3932-4e0b-a2ed-e3b83fcb2a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844266507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.844266507
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.3108642507
Short name T703
Test name
Test status
Simulation time 5740234730 ps
CPU time 14.84 seconds
Started Jun 04 01:53:07 PM PDT 24
Finished Jun 04 01:53:23 PM PDT 24
Peak memory 201604 kb
Host smart-718a54e6-d77b-47c9-9277-88b936649db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108642507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.3108642507
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.3139073508
Short name T155
Test name
Test status
Simulation time 406051938048 ps
CPU time 889.14 seconds
Started Jun 04 01:53:08 PM PDT 24
Finished Jun 04 02:07:58 PM PDT 24
Peak memory 201792 kb
Host smart-c6d4be7e-6ae3-4fdc-b56f-e5967b6d228d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139073508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.3139073508
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.2458575117
Short name T246
Test name
Test status
Simulation time 293135371219 ps
CPU time 348.47 seconds
Started Jun 04 01:53:07 PM PDT 24
Finished Jun 04 01:58:57 PM PDT 24
Peak memory 210376 kb
Host smart-8c804054-674e-4cd7-9ccc-7dbb0c3ae556
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458575117 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.2458575117
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.1998200936
Short name T613
Test name
Test status
Simulation time 507069732 ps
CPU time 1.84 seconds
Started Jun 04 01:53:22 PM PDT 24
Finished Jun 04 01:53:25 PM PDT 24
Peak memory 201508 kb
Host smart-d9f0f0c8-61d0-4811-afc5-ac212b971de8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998200936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.1998200936
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.4190326988
Short name T665
Test name
Test status
Simulation time 497876363445 ps
CPU time 232.54 seconds
Started Jun 04 01:53:04 PM PDT 24
Finished Jun 04 01:56:57 PM PDT 24
Peak memory 201780 kb
Host smart-7985f5d0-5e92-4960-a12c-55f8ce8d8a91
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190326988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.4190326988
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.3760179380
Short name T650
Test name
Test status
Simulation time 163246271318 ps
CPU time 414.63 seconds
Started Jun 04 01:53:09 PM PDT 24
Finished Jun 04 02:00:05 PM PDT 24
Peak memory 201728 kb
Host smart-215c8010-5ed2-4898-b9b9-dbeda902479c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760179380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.3760179380
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.2497626742
Short name T628
Test name
Test status
Simulation time 318712264842 ps
CPU time 191.44 seconds
Started Jun 04 01:53:10 PM PDT 24
Finished Jun 04 01:56:23 PM PDT 24
Peak memory 201828 kb
Host smart-eb6ca45d-5ef1-4e43-82e7-f32aa23acbc4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497626742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.2497626742
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.2474890156
Short name T527
Test name
Test status
Simulation time 495026525436 ps
CPU time 1172.38 seconds
Started Jun 04 01:53:02 PM PDT 24
Finished Jun 04 02:12:35 PM PDT 24
Peak memory 201780 kb
Host smart-892fb2eb-504c-4173-abed-3128b49311cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474890156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.2474890156
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.2458498698
Short name T630
Test name
Test status
Simulation time 165269988779 ps
CPU time 199.83 seconds
Started Jun 04 01:53:07 PM PDT 24
Finished Jun 04 01:56:28 PM PDT 24
Peak memory 201696 kb
Host smart-5ead8a40-2576-434c-9f99-f5031cb863b9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458498698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.2458498698
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.550496706
Short name T693
Test name
Test status
Simulation time 181842193043 ps
CPU time 61.92 seconds
Started Jun 04 01:53:02 PM PDT 24
Finished Jun 04 01:54:05 PM PDT 24
Peak memory 201824 kb
Host smart-be75b94d-b4df-4073-9c88-238b9cb8d52b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550496706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_
wakeup.550496706
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.1789221274
Short name T45
Test name
Test status
Simulation time 104326260945 ps
CPU time 537.65 seconds
Started Jun 04 01:53:07 PM PDT 24
Finished Jun 04 02:02:06 PM PDT 24
Peak memory 202180 kb
Host smart-f60cd3fe-88ba-438b-8a29-6133150d1a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789221274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.1789221274
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.2117694253
Short name T86
Test name
Test status
Simulation time 36398217887 ps
CPU time 22.07 seconds
Started Jun 04 01:53:13 PM PDT 24
Finished Jun 04 01:53:36 PM PDT 24
Peak memory 201632 kb
Host smart-0bbe700b-5594-4277-83aa-a0bc5a279a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117694253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.2117694253
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.3758803245
Short name T654
Test name
Test status
Simulation time 3984737088 ps
CPU time 2.7 seconds
Started Jun 04 01:53:07 PM PDT 24
Finished Jun 04 01:53:12 PM PDT 24
Peak memory 201592 kb
Host smart-11e8d06c-a4df-483f-8ebb-1b367c71b9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758803245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.3758803245
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.1099558012
Short name T653
Test name
Test status
Simulation time 6058002265 ps
CPU time 8.16 seconds
Started Jun 04 01:53:05 PM PDT 24
Finished Jun 04 01:53:14 PM PDT 24
Peak memory 201636 kb
Host smart-f44c9faf-5604-4e78-adcc-344de0cf2cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099558012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.1099558012
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.283722364
Short name T771
Test name
Test status
Simulation time 717299545056 ps
CPU time 1493.48 seconds
Started Jun 04 01:53:01 PM PDT 24
Finished Jun 04 02:17:56 PM PDT 24
Peak memory 201800 kb
Host smart-6d523cf1-0c1d-47fb-8ee4-1a8d7c077eb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283722364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all.
283722364
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.1393505975
Short name T216
Test name
Test status
Simulation time 165001474911 ps
CPU time 190.87 seconds
Started Jun 04 01:53:08 PM PDT 24
Finished Jun 04 01:56:20 PM PDT 24
Peak memory 210556 kb
Host smart-9a53cc4c-1ee0-4cfe-8581-82cf6423992b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393505975 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.1393505975
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.2921537476
Short name T578
Test name
Test status
Simulation time 414975108 ps
CPU time 1.09 seconds
Started Jun 04 01:53:10 PM PDT 24
Finished Jun 04 01:53:12 PM PDT 24
Peak memory 201468 kb
Host smart-52cbbf9c-a717-40c2-bb8d-4b853005f6b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921537476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.2921537476
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.1040257385
Short name T161
Test name
Test status
Simulation time 490409104343 ps
CPU time 304.75 seconds
Started Jun 04 01:53:05 PM PDT 24
Finished Jun 04 01:58:11 PM PDT 24
Peak memory 201784 kb
Host smart-f7d8c33d-d605-49f3-a224-e7ba045cab65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040257385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.1040257385
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.2684304085
Short name T458
Test name
Test status
Simulation time 489767729893 ps
CPU time 303.64 seconds
Started Jun 04 01:53:09 PM PDT 24
Finished Jun 04 01:58:14 PM PDT 24
Peak memory 201824 kb
Host smart-ba6d47d1-deca-4ecc-9d20-4499f137d6dc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684304085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.2684304085
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.3116317176
Short name T241
Test name
Test status
Simulation time 343667421711 ps
CPU time 202.42 seconds
Started Jun 04 01:53:13 PM PDT 24
Finished Jun 04 01:56:36 PM PDT 24
Peak memory 201872 kb
Host smart-3267dcb7-d99d-43cc-a8eb-64b3d27cd75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116317176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.3116317176
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.3283397219
Short name T396
Test name
Test status
Simulation time 328661955220 ps
CPU time 724.75 seconds
Started Jun 04 01:53:06 PM PDT 24
Finished Jun 04 02:05:12 PM PDT 24
Peak memory 201772 kb
Host smart-ec4b466d-5587-4848-8cd5-9d491e3d42f5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283397219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.3283397219
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.854611658
Short name T343
Test name
Test status
Simulation time 170910919571 ps
CPU time 22.64 seconds
Started Jun 04 01:53:06 PM PDT 24
Finished Jun 04 01:53:30 PM PDT 24
Peak memory 201880 kb
Host smart-7a5dcdf3-e0b9-4cd3-877c-148098a912ad
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854611658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_
wakeup.854611658
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.59231656
Short name T528
Test name
Test status
Simulation time 197208486586 ps
CPU time 107.95 seconds
Started Jun 04 01:53:12 PM PDT 24
Finished Jun 04 01:55:01 PM PDT 24
Peak memory 201784 kb
Host smart-69bd399e-3844-4bf6-8117-a662a76bd791
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59231656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.a
dc_ctrl_filters_wakeup_fixed.59231656
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.2163448628
Short name T632
Test name
Test status
Simulation time 99637090585 ps
CPU time 313.81 seconds
Started Jun 04 01:53:11 PM PDT 24
Finished Jun 04 01:58:26 PM PDT 24
Peak memory 202068 kb
Host smart-9abaad22-3ca4-4a51-92b1-2d1b4bdd99d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163448628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.2163448628
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.14510372
Short name T637
Test name
Test status
Simulation time 25124829486 ps
CPU time 30.05 seconds
Started Jun 04 01:53:09 PM PDT 24
Finished Jun 04 01:53:41 PM PDT 24
Peak memory 201564 kb
Host smart-67dbdc66-9aed-4182-a303-2cfd56fa662b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14510372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.14510372
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.4029324438
Short name T436
Test name
Test status
Simulation time 2796549124 ps
CPU time 2.46 seconds
Started Jun 04 01:53:07 PM PDT 24
Finished Jun 04 01:53:12 PM PDT 24
Peak memory 201588 kb
Host smart-961db0a6-affd-4244-929b-59c204ffb5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029324438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.4029324438
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.2927384661
Short name T546
Test name
Test status
Simulation time 6138122739 ps
CPU time 15.73 seconds
Started Jun 04 01:53:06 PM PDT 24
Finished Jun 04 01:53:23 PM PDT 24
Peak memory 201644 kb
Host smart-7f9315b8-e4eb-4323-adf4-7ca2ede96bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927384661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.2927384661
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.679886097
Short name T21
Test name
Test status
Simulation time 11620192469 ps
CPU time 31.41 seconds
Started Jun 04 01:53:15 PM PDT 24
Finished Jun 04 01:53:47 PM PDT 24
Peak memory 210084 kb
Host smart-2853a2aa-0429-4d40-9166-43653db0f8db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679886097 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.679886097
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.1430353481
Short name T648
Test name
Test status
Simulation time 452345301 ps
CPU time 1.65 seconds
Started Jun 04 01:53:08 PM PDT 24
Finished Jun 04 01:53:12 PM PDT 24
Peak memory 201452 kb
Host smart-df4c072c-05af-4ac1-8e1e-50ea423b3afa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430353481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.1430353481
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.2636918708
Short name T94
Test name
Test status
Simulation time 163336702641 ps
CPU time 116.6 seconds
Started Jun 04 01:53:15 PM PDT 24
Finished Jun 04 01:55:12 PM PDT 24
Peak memory 201848 kb
Host smart-f9c05c28-5a79-430d-adb6-39f96cfc8ca6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636918708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.2636918708
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.1818597923
Short name T770
Test name
Test status
Simulation time 165784848212 ps
CPU time 56.01 seconds
Started Jun 04 01:53:12 PM PDT 24
Finished Jun 04 01:54:09 PM PDT 24
Peak memory 201736 kb
Host smart-a738ff64-a03f-4837-9493-5587e250567e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818597923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.1818597923
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.3552318305
Short name T323
Test name
Test status
Simulation time 481129727201 ps
CPU time 319.65 seconds
Started Jun 04 01:53:14 PM PDT 24
Finished Jun 04 01:58:35 PM PDT 24
Peak memory 201776 kb
Host smart-eb41daf7-5a5b-48ea-82d4-6b331c190659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552318305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.3552318305
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.3413925029
Short name T681
Test name
Test status
Simulation time 494684732540 ps
CPU time 108.34 seconds
Started Jun 04 01:53:21 PM PDT 24
Finished Jun 04 01:55:10 PM PDT 24
Peak memory 201736 kb
Host smart-3be17c29-b7bc-4f3a-bb49-0785f7558da0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413925029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.3413925029
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.3623761813
Short name T265
Test name
Test status
Simulation time 490345673451 ps
CPU time 994.54 seconds
Started Jun 04 01:53:11 PM PDT 24
Finished Jun 04 02:09:47 PM PDT 24
Peak memory 201768 kb
Host smart-9ac63acf-2174-49f6-8849-d96ac4812b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623761813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.3623761813
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.3496031763
Short name T438
Test name
Test status
Simulation time 491043805889 ps
CPU time 1037.93 seconds
Started Jun 04 01:53:11 PM PDT 24
Finished Jun 04 02:10:30 PM PDT 24
Peak memory 201756 kb
Host smart-bde4f75e-2f47-4227-a873-383454d17752
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496031763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.3496031763
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.475391046
Short name T541
Test name
Test status
Simulation time 360721054564 ps
CPU time 466.39 seconds
Started Jun 04 01:53:13 PM PDT 24
Finished Jun 04 02:01:00 PM PDT 24
Peak memory 201820 kb
Host smart-2fd2e719-ed6f-493e-8b6f-b00f7a3cb819
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475391046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_
wakeup.475391046
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.4294117916
Short name T495
Test name
Test status
Simulation time 407406235294 ps
CPU time 703.39 seconds
Started Jun 04 01:53:14 PM PDT 24
Finished Jun 04 02:04:58 PM PDT 24
Peak memory 201784 kb
Host smart-68356bf1-cda5-4477-aeb2-8e556b1b890c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294117916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.4294117916
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.2138709881
Short name T724
Test name
Test status
Simulation time 72425587140 ps
CPU time 261.76 seconds
Started Jun 04 01:53:08 PM PDT 24
Finished Jun 04 01:57:31 PM PDT 24
Peak memory 202028 kb
Host smart-72f6c3f9-f612-4533-8293-19cc5d92a285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138709881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.2138709881
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.3995449739
Short name T581
Test name
Test status
Simulation time 35626721118 ps
CPU time 21.57 seconds
Started Jun 04 01:53:22 PM PDT 24
Finished Jun 04 01:53:44 PM PDT 24
Peak memory 201556 kb
Host smart-fec36db1-ea9c-462e-99b0-63af78fa2907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995449739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.3995449739
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.157267277
Short name T532
Test name
Test status
Simulation time 4022763680 ps
CPU time 9.23 seconds
Started Jun 04 01:53:07 PM PDT 24
Finished Jun 04 01:53:18 PM PDT 24
Peak memory 201620 kb
Host smart-c1c27acf-e8ec-4702-8513-9bee03f363dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157267277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.157267277
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.2723763128
Short name T476
Test name
Test status
Simulation time 5566752795 ps
CPU time 3.67 seconds
Started Jun 04 01:53:09 PM PDT 24
Finished Jun 04 01:53:14 PM PDT 24
Peak memory 201648 kb
Host smart-43a053a9-b13d-4135-9ac6-64d682b6ad51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723763128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.2723763128
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.1066098131
Short name T684
Test name
Test status
Simulation time 984141483 ps
CPU time 1.79 seconds
Started Jun 04 01:53:10 PM PDT 24
Finished Jun 04 01:53:13 PM PDT 24
Peak memory 201516 kb
Host smart-ceed48d0-c1cc-4cfe-b288-023746b05cb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066098131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.1066098131
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.1114491405
Short name T88
Test name
Test status
Simulation time 90112196136 ps
CPU time 166.98 seconds
Started Jun 04 01:53:12 PM PDT 24
Finished Jun 04 01:56:00 PM PDT 24
Peak memory 210320 kb
Host smart-07bb3d93-6be8-4508-ae08-ff04562ff07f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114491405 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.1114491405
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.3242913424
Short name T601
Test name
Test status
Simulation time 431934226 ps
CPU time 1.58 seconds
Started Jun 04 01:52:29 PM PDT 24
Finished Jun 04 01:52:33 PM PDT 24
Peak memory 201352 kb
Host smart-6f92a7ba-b140-4575-a376-9b0e422407e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242913424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.3242913424
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.2101785089
Short name T645
Test name
Test status
Simulation time 165845191964 ps
CPU time 377.92 seconds
Started Jun 04 01:52:33 PM PDT 24
Finished Jun 04 01:58:53 PM PDT 24
Peak memory 201892 kb
Host smart-9b6a7603-19d6-4699-a7bc-79a77b4e32a5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101785089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.2101785089
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.3983491889
Short name T204
Test name
Test status
Simulation time 483318915304 ps
CPU time 165.82 seconds
Started Jun 04 01:52:28 PM PDT 24
Finished Jun 04 01:55:21 PM PDT 24
Peak memory 201884 kb
Host smart-f19ffcb0-ab4e-4749-91ba-28dcf495e046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983491889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.3983491889
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.2829036433
Short name T461
Test name
Test status
Simulation time 492770963926 ps
CPU time 583.43 seconds
Started Jun 04 01:52:35 PM PDT 24
Finished Jun 04 02:02:20 PM PDT 24
Peak memory 201808 kb
Host smart-e567f818-e200-4d28-891b-e0e80d515ed3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829036433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.2829036433
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.4163144902
Short name T190
Test name
Test status
Simulation time 504775614765 ps
CPU time 149.57 seconds
Started Jun 04 01:52:29 PM PDT 24
Finished Jun 04 01:55:01 PM PDT 24
Peak memory 201828 kb
Host smart-eca518e8-a4e1-42ba-96b4-a962d7ec4dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163144902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.4163144902
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.4055059470
Short name T610
Test name
Test status
Simulation time 324689145800 ps
CPU time 375.13 seconds
Started Jun 04 01:52:37 PM PDT 24
Finished Jun 04 01:58:53 PM PDT 24
Peak memory 201728 kb
Host smart-eb65f0a9-1d8c-46e4-bd01-b0a95d3bc1e2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055059470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.4055059470
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.3535382247
Short name T536
Test name
Test status
Simulation time 164550517356 ps
CPU time 370.9 seconds
Started Jun 04 01:52:34 PM PDT 24
Finished Jun 04 01:58:46 PM PDT 24
Peak memory 201828 kb
Host smart-0e11e785-fa33-45c8-93fb-d0ef2f984394
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535382247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.3535382247
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.2605164475
Short name T440
Test name
Test status
Simulation time 596181046084 ps
CPU time 422.06 seconds
Started Jun 04 01:52:27 PM PDT 24
Finished Jun 04 01:59:32 PM PDT 24
Peak memory 201800 kb
Host smart-dfd08712-1548-45c7-a5b5-5f4123de9fcf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605164475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.2605164475
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.1966194643
Short name T217
Test name
Test status
Simulation time 79074329104 ps
CPU time 289.13 seconds
Started Jun 04 01:52:28 PM PDT 24
Finished Jun 04 01:57:20 PM PDT 24
Peak memory 202040 kb
Host smart-8c3edf9d-366c-4a56-be3d-6784b8e3cde9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966194643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.1966194643
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.1217577883
Short name T744
Test name
Test status
Simulation time 41674032161 ps
CPU time 27.07 seconds
Started Jun 04 01:52:31 PM PDT 24
Finished Jun 04 01:53:00 PM PDT 24
Peak memory 201616 kb
Host smart-d599115b-09f5-4279-bec7-66abebaeaa51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217577883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.1217577883
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.2316600096
Short name T689
Test name
Test status
Simulation time 5098946489 ps
CPU time 6.26 seconds
Started Jun 04 01:52:28 PM PDT 24
Finished Jun 04 01:52:37 PM PDT 24
Peak memory 201608 kb
Host smart-86fc82ac-fee1-4c91-b098-42af74a2e550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316600096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.2316600096
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.1093104037
Short name T64
Test name
Test status
Simulation time 4638255737 ps
CPU time 10.68 seconds
Started Jun 04 01:52:29 PM PDT 24
Finished Jun 04 01:52:42 PM PDT 24
Peak memory 217192 kb
Host smart-991cbde4-9da7-47a0-8cc1-8a1c98704b8e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093104037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.1093104037
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.2668038206
Short name T763
Test name
Test status
Simulation time 5823635185 ps
CPU time 4.14 seconds
Started Jun 04 01:52:28 PM PDT 24
Finished Jun 04 01:52:35 PM PDT 24
Peak memory 201624 kb
Host smart-a379d041-4b64-4474-a1df-46622a2a01ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668038206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.2668038206
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.3294004739
Short name T626
Test name
Test status
Simulation time 164024933540 ps
CPU time 364.63 seconds
Started Jun 04 01:52:33 PM PDT 24
Finished Jun 04 01:58:40 PM PDT 24
Peak memory 201800 kb
Host smart-1b7babb8-428b-4e09-b03d-f73042838722
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294004739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
3294004739
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.1793501788
Short name T543
Test name
Test status
Simulation time 98162160198 ps
CPU time 117.6 seconds
Started Jun 04 01:52:33 PM PDT 24
Finished Jun 04 01:54:32 PM PDT 24
Peak memory 210408 kb
Host smart-52cace50-df2d-41fb-8e28-0abb6d6dc351
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793501788 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.1793501788
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.3465830067
Short name T71
Test name
Test status
Simulation time 437954519 ps
CPU time 1.09 seconds
Started Jun 04 01:53:12 PM PDT 24
Finished Jun 04 01:53:14 PM PDT 24
Peak memory 201444 kb
Host smart-d0b5f550-8ae1-4bb0-87bb-ffc87fd5cc22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465830067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.3465830067
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.2995924252
Short name T754
Test name
Test status
Simulation time 167362384628 ps
CPU time 393.25 seconds
Started Jun 04 01:53:08 PM PDT 24
Finished Jun 04 01:59:43 PM PDT 24
Peak memory 201812 kb
Host smart-0879630c-9849-4150-bc2c-81a45f697c26
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995924252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.2995924252
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.75128271
Short name T238
Test name
Test status
Simulation time 162385577432 ps
CPU time 91.94 seconds
Started Jun 04 01:53:07 PM PDT 24
Finished Jun 04 01:54:41 PM PDT 24
Peak memory 201812 kb
Host smart-b6d80b32-c409-4907-a948-b006c1b7a076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75128271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.75128271
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.2021911811
Short name T97
Test name
Test status
Simulation time 164544369630 ps
CPU time 396.97 seconds
Started Jun 04 01:53:18 PM PDT 24
Finished Jun 04 01:59:56 PM PDT 24
Peak memory 201756 kb
Host smart-09d42c62-f9bc-4467-a1c8-17c7233abc1e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021911811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.2021911811
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.2857355027
Short name T598
Test name
Test status
Simulation time 167729868532 ps
CPU time 158.6 seconds
Started Jun 04 01:53:10 PM PDT 24
Finished Jun 04 01:55:50 PM PDT 24
Peak memory 201760 kb
Host smart-536451f6-e94c-4f62-9964-15eb7d582d9d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857355027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.2857355027
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.2695759715
Short name T315
Test name
Test status
Simulation time 364688482783 ps
CPU time 260.91 seconds
Started Jun 04 01:53:12 PM PDT 24
Finished Jun 04 01:57:33 PM PDT 24
Peak memory 201852 kb
Host smart-2991b512-2cae-4b8b-b18e-3b2677f4757c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695759715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.2695759715
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.1577295803
Short name T521
Test name
Test status
Simulation time 594859004076 ps
CPU time 341.25 seconds
Started Jun 04 01:53:14 PM PDT 24
Finished Jun 04 01:58:56 PM PDT 24
Peak memory 201776 kb
Host smart-0532e5bf-46a3-465b-bbae-83f1ca97f640
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577295803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.1577295803
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.224691291
Short name T711
Test name
Test status
Simulation time 128983242655 ps
CPU time 390.47 seconds
Started Jun 04 01:53:10 PM PDT 24
Finished Jun 04 01:59:42 PM PDT 24
Peak memory 202116 kb
Host smart-137a04e8-e94f-408d-be3d-9f71ef759a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224691291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.224691291
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.2061227515
Short name T46
Test name
Test status
Simulation time 26548519781 ps
CPU time 9.97 seconds
Started Jun 04 01:53:22 PM PDT 24
Finished Jun 04 01:53:33 PM PDT 24
Peak memory 201616 kb
Host smart-661e8a59-b128-42ff-9d50-97c1b901d10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061227515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.2061227515
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.2020990091
Short name T439
Test name
Test status
Simulation time 3622103793 ps
CPU time 3.29 seconds
Started Jun 04 01:53:12 PM PDT 24
Finished Jun 04 01:53:16 PM PDT 24
Peak memory 201580 kb
Host smart-7db17d5d-cc44-4a5a-bd1a-698d5474d1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020990091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.2020990091
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.2662611032
Short name T518
Test name
Test status
Simulation time 5980345543 ps
CPU time 3.73 seconds
Started Jun 04 01:53:15 PM PDT 24
Finished Jun 04 01:53:19 PM PDT 24
Peak memory 201636 kb
Host smart-e5e3b0dd-0844-4d62-a923-18954e36bf9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662611032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.2662611032
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.3216688385
Short name T34
Test name
Test status
Simulation time 83940140202 ps
CPU time 45.62 seconds
Started Jun 04 01:53:20 PM PDT 24
Finished Jun 04 01:54:07 PM PDT 24
Peak memory 201744 kb
Host smart-4b2a1d26-df6b-45c3-9f3f-788ddc081ef5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216688385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.3216688385
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.4200282323
Short name T618
Test name
Test status
Simulation time 508326422 ps
CPU time 0.68 seconds
Started Jun 04 01:53:25 PM PDT 24
Finished Jun 04 01:53:27 PM PDT 24
Peak memory 201492 kb
Host smart-32b4adad-d3c0-45a7-bbe7-d3b4eb20b7ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200282323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.4200282323
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.3416911017
Short name T730
Test name
Test status
Simulation time 495012489735 ps
CPU time 1114.48 seconds
Started Jun 04 01:53:12 PM PDT 24
Finished Jun 04 02:11:47 PM PDT 24
Peak memory 201752 kb
Host smart-6e88af65-f73a-456b-b662-2d7d96230903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416911017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.3416911017
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.1352694678
Short name T513
Test name
Test status
Simulation time 497593662478 ps
CPU time 1122.19 seconds
Started Jun 04 01:53:14 PM PDT 24
Finished Jun 04 02:11:57 PM PDT 24
Peak memory 201780 kb
Host smart-066e6154-a956-4564-9d18-b74b9e13b78c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352694678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.1352694678
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.1538031822
Short name T102
Test name
Test status
Simulation time 484161590385 ps
CPU time 599.58 seconds
Started Jun 04 01:53:06 PM PDT 24
Finished Jun 04 02:03:08 PM PDT 24
Peak memory 201828 kb
Host smart-e37ee215-8d68-4104-88ca-bb6a60c08311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538031822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.1538031822
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.2793833328
Short name T517
Test name
Test status
Simulation time 489321269937 ps
CPU time 266.23 seconds
Started Jun 04 01:53:22 PM PDT 24
Finished Jun 04 01:57:49 PM PDT 24
Peak memory 201824 kb
Host smart-e65f475e-10ba-4d91-98a3-104d48c48264
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793833328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.2793833328
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.937370573
Short name T477
Test name
Test status
Simulation time 596788888960 ps
CPU time 376.46 seconds
Started Jun 04 01:53:17 PM PDT 24
Finished Jun 04 01:59:34 PM PDT 24
Peak memory 201804 kb
Host smart-db72b4e5-8b8a-4a9c-9c8d-126419ced10e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937370573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
adc_ctrl_filters_wakeup_fixed.937370573
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.2806893198
Short name T501
Test name
Test status
Simulation time 101496357486 ps
CPU time 487.58 seconds
Started Jun 04 01:53:20 PM PDT 24
Finished Jun 04 02:01:28 PM PDT 24
Peak memory 202116 kb
Host smart-3782d8bc-7859-41ec-a48c-b56e9c584a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806893198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.2806893198
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.127394324
Short name T383
Test name
Test status
Simulation time 33112643925 ps
CPU time 74.08 seconds
Started Jun 04 01:53:19 PM PDT 24
Finished Jun 04 01:54:33 PM PDT 24
Peak memory 201604 kb
Host smart-05e22e43-4679-4b44-a5e6-66f111be18e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127394324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.127394324
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.2903016615
Short name T425
Test name
Test status
Simulation time 4693791637 ps
CPU time 3.56 seconds
Started Jun 04 01:53:12 PM PDT 24
Finished Jun 04 01:53:17 PM PDT 24
Peak memory 201600 kb
Host smart-be9b696d-48e5-4955-8e2b-7680dca7c59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903016615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.2903016615
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.1204781172
Short name T496
Test name
Test status
Simulation time 5670676669 ps
CPU time 14.99 seconds
Started Jun 04 01:53:21 PM PDT 24
Finished Jun 04 01:53:37 PM PDT 24
Peak memory 201612 kb
Host smart-3e763019-4d81-4ed7-9db2-80b42adbd4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204781172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.1204781172
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.2919992982
Short name T159
Test name
Test status
Simulation time 200697981304 ps
CPU time 244.75 seconds
Started Jun 04 01:53:17 PM PDT 24
Finished Jun 04 01:57:23 PM PDT 24
Peak memory 201736 kb
Host smart-c949b136-23ad-416d-85ea-9a243059d6a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919992982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.2919992982
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.2586749852
Short name T38
Test name
Test status
Simulation time 56948150768 ps
CPU time 27.77 seconds
Started Jun 04 01:53:19 PM PDT 24
Finished Jun 04 01:53:48 PM PDT 24
Peak memory 210072 kb
Host smart-7f7b0693-9e3a-4056-8df3-fdf8f6611497
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586749852 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.2586749852
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.533138739
Short name T755
Test name
Test status
Simulation time 482309475 ps
CPU time 0.85 seconds
Started Jun 04 01:53:24 PM PDT 24
Finished Jun 04 01:53:26 PM PDT 24
Peak memory 201492 kb
Host smart-2eb6f0af-9f07-45ae-aa9c-9c958c08b850
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533138739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.533138739
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.2004169668
Short name T101
Test name
Test status
Simulation time 352983158136 ps
CPU time 417.74 seconds
Started Jun 04 01:53:13 PM PDT 24
Finished Jun 04 02:00:12 PM PDT 24
Peak memory 201756 kb
Host smart-ba5801b7-7c79-425e-98f5-c92683ab8e91
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004169668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.2004169668
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.2694429175
Short name T169
Test name
Test status
Simulation time 379422608952 ps
CPU time 70.7 seconds
Started Jun 04 01:53:20 PM PDT 24
Finished Jun 04 01:54:31 PM PDT 24
Peak memory 201848 kb
Host smart-6649bf8e-8196-4653-ac69-bfa31ae7babd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694429175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.2694429175
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.296136001
Short name T237
Test name
Test status
Simulation time 492853675431 ps
CPU time 191.92 seconds
Started Jun 04 01:53:14 PM PDT 24
Finished Jun 04 01:56:27 PM PDT 24
Peak memory 201876 kb
Host smart-367d888e-9ec1-4031-a3c8-f6b11d01a44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296136001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.296136001
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.323037652
Short name T369
Test name
Test status
Simulation time 503152945774 ps
CPU time 578.28 seconds
Started Jun 04 01:53:23 PM PDT 24
Finished Jun 04 02:03:02 PM PDT 24
Peak memory 201764 kb
Host smart-b3d8fa71-9600-492c-8730-34cf0dbf7e36
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=323037652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrup
t_fixed.323037652
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.4094109900
Short name T520
Test name
Test status
Simulation time 165183264292 ps
CPU time 389 seconds
Started Jun 04 01:53:19 PM PDT 24
Finished Jun 04 01:59:49 PM PDT 24
Peak memory 201884 kb
Host smart-da881f29-ff33-4993-b7de-a6390183b7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094109900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.4094109900
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.3652159712
Short name T429
Test name
Test status
Simulation time 334849024619 ps
CPU time 244.38 seconds
Started Jun 04 01:53:22 PM PDT 24
Finished Jun 04 01:57:27 PM PDT 24
Peak memory 201768 kb
Host smart-a12aad5a-01b8-4d4c-b96e-5f9774abd1dd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652159712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.3652159712
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.3796074873
Short name T113
Test name
Test status
Simulation time 483233188287 ps
CPU time 244.34 seconds
Started Jun 04 01:53:21 PM PDT 24
Finished Jun 04 01:57:27 PM PDT 24
Peak memory 201880 kb
Host smart-b62cf447-436d-455d-90be-89a12c35eed0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796074873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.3796074873
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.3800026028
Short name T453
Test name
Test status
Simulation time 211930255437 ps
CPU time 540.84 seconds
Started Jun 04 01:53:16 PM PDT 24
Finished Jun 04 02:02:18 PM PDT 24
Peak memory 201820 kb
Host smart-3d3763a2-aa6c-4e8d-bcd6-1eccded798cf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800026028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.3800026028
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.364640215
Short name T639
Test name
Test status
Simulation time 96893468246 ps
CPU time 445.11 seconds
Started Jun 04 01:53:17 PM PDT 24
Finished Jun 04 02:00:43 PM PDT 24
Peak memory 202132 kb
Host smart-468b39e4-a938-46be-805f-5937ee1a2c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364640215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.364640215
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.158187290
Short name T624
Test name
Test status
Simulation time 30714460513 ps
CPU time 17.8 seconds
Started Jun 04 01:53:28 PM PDT 24
Finished Jun 04 01:53:46 PM PDT 24
Peak memory 201604 kb
Host smart-f3af9e94-7f16-4050-b5b9-1284a6325a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158187290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.158187290
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.1371225440
Short name T205
Test name
Test status
Simulation time 4226330123 ps
CPU time 11.54 seconds
Started Jun 04 01:53:13 PM PDT 24
Finished Jun 04 01:53:25 PM PDT 24
Peak memory 201564 kb
Host smart-7538db4e-acdf-4f1a-8788-845a82389f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371225440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.1371225440
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.1424638128
Short name T1
Test name
Test status
Simulation time 5689085081 ps
CPU time 3.61 seconds
Started Jun 04 01:53:25 PM PDT 24
Finished Jun 04 01:53:29 PM PDT 24
Peak memory 201544 kb
Host smart-2bf695b6-fee0-4170-9db8-91f334bd6495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424638128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.1424638128
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.3714614785
Short name T114
Test name
Test status
Simulation time 218414952536 ps
CPU time 542.41 seconds
Started Jun 04 01:53:19 PM PDT 24
Finished Jun 04 02:02:23 PM PDT 24
Peak memory 201808 kb
Host smart-653d1db1-cf6a-4322-98bf-32e7fa1720b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714614785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.3714614785
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.1751580559
Short name T662
Test name
Test status
Simulation time 155426768713 ps
CPU time 104.67 seconds
Started Jun 04 01:53:19 PM PDT 24
Finished Jun 04 01:55:04 PM PDT 24
Peak memory 217916 kb
Host smart-f18bec92-54b1-494b-a17d-391411c0a777
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751580559 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.1751580559
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.1478076725
Short name T749
Test name
Test status
Simulation time 492572375 ps
CPU time 0.93 seconds
Started Jun 04 01:53:20 PM PDT 24
Finished Jun 04 01:53:22 PM PDT 24
Peak memory 201468 kb
Host smart-9ccf316b-25cc-47b8-acc4-fa43b03ff257
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478076725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.1478076725
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.2934470049
Short name T761
Test name
Test status
Simulation time 167949402095 ps
CPU time 104.11 seconds
Started Jun 04 01:53:20 PM PDT 24
Finished Jun 04 01:55:05 PM PDT 24
Peak memory 201768 kb
Host smart-dfd2ced5-2868-495d-821c-d4a05e7f6305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934470049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.2934470049
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.2043632302
Short name T180
Test name
Test status
Simulation time 320696483996 ps
CPU time 212.54 seconds
Started Jun 04 01:53:18 PM PDT 24
Finished Jun 04 01:56:51 PM PDT 24
Peak memory 201748 kb
Host smart-867455c0-4681-4ed9-ab85-d8589d29b129
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043632302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.2043632302
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.2587379164
Short name T635
Test name
Test status
Simulation time 167235666649 ps
CPU time 186.82 seconds
Started Jun 04 01:53:17 PM PDT 24
Finished Jun 04 01:56:24 PM PDT 24
Peak memory 201788 kb
Host smart-a945a6c4-18ab-4324-b44a-cacfed87422b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587379164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.2587379164
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.896384274
Short name T117
Test name
Test status
Simulation time 329140372222 ps
CPU time 394.71 seconds
Started Jun 04 01:53:15 PM PDT 24
Finished Jun 04 01:59:51 PM PDT 24
Peak memory 201808 kb
Host smart-bec49e38-f12f-4b13-b2b1-d33ee11318cd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=896384274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fixe
d.896384274
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.4267843802
Short name T231
Test name
Test status
Simulation time 376996073659 ps
CPU time 227.16 seconds
Started Jun 04 01:53:22 PM PDT 24
Finished Jun 04 01:57:10 PM PDT 24
Peak memory 201884 kb
Host smart-5ecdf36d-7482-40f8-8aab-e3dbbb399e28
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267843802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.4267843802
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.3179290807
Short name T415
Test name
Test status
Simulation time 201260330340 ps
CPU time 446.14 seconds
Started Jun 04 01:53:20 PM PDT 24
Finished Jun 04 02:00:47 PM PDT 24
Peak memory 201776 kb
Host smart-04b562e9-23dd-468d-95d4-68a8f2bedd54
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179290807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.3179290807
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.2654603142
Short name T218
Test name
Test status
Simulation time 109470161734 ps
CPU time 410.88 seconds
Started Jun 04 01:53:21 PM PDT 24
Finished Jun 04 02:00:12 PM PDT 24
Peak memory 202112 kb
Host smart-bf09ad50-48d4-451f-9817-49f2a35ad409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654603142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.2654603142
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.3182079078
Short name T550
Test name
Test status
Simulation time 35333526374 ps
CPU time 19.88 seconds
Started Jun 04 01:53:22 PM PDT 24
Finished Jun 04 01:53:43 PM PDT 24
Peak memory 201632 kb
Host smart-456269b2-64a8-49db-8ccc-473b5ea8836e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182079078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.3182079078
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.737875534
Short name T376
Test name
Test status
Simulation time 3323488601 ps
CPU time 3.19 seconds
Started Jun 04 01:53:18 PM PDT 24
Finished Jun 04 01:53:22 PM PDT 24
Peak memory 201616 kb
Host smart-41514143-f86c-4c86-9e24-3f9373240cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737875534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.737875534
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.2058745304
Short name T478
Test name
Test status
Simulation time 5871466498 ps
CPU time 13.8 seconds
Started Jun 04 01:53:16 PM PDT 24
Finished Jun 04 01:53:30 PM PDT 24
Peak memory 201576 kb
Host smart-d5187ab6-a5a2-4e21-9aee-7d6872b9d348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058745304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.2058745304
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.2152422346
Short name T708
Test name
Test status
Simulation time 278544405209 ps
CPU time 217.24 seconds
Started Jun 04 01:53:14 PM PDT 24
Finished Jun 04 01:56:52 PM PDT 24
Peak memory 218256 kb
Host smart-6a1a6bdf-2f12-42fd-a8d5-dcaf9023303d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152422346 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.2152422346
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.1243405016
Short name T371
Test name
Test status
Simulation time 478735669 ps
CPU time 1.8 seconds
Started Jun 04 01:53:25 PM PDT 24
Finished Jun 04 01:53:27 PM PDT 24
Peak memory 201496 kb
Host smart-a6d0d5bb-d75e-4763-8e8c-0a01b17f7f8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243405016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.1243405016
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.2999042044
Short name T661
Test name
Test status
Simulation time 336475659818 ps
CPU time 376.9 seconds
Started Jun 04 01:53:21 PM PDT 24
Finished Jun 04 01:59:39 PM PDT 24
Peak memory 201804 kb
Host smart-e0ecde9f-2c6c-45fe-9440-e1ef00d0ea46
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999042044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.2999042044
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.3875871440
Short name T629
Test name
Test status
Simulation time 326936301643 ps
CPU time 743.22 seconds
Started Jun 04 01:53:21 PM PDT 24
Finished Jun 04 02:05:45 PM PDT 24
Peak memory 201796 kb
Host smart-0a6074f6-d8cb-4ee3-b51f-38e47c438843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875871440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.3875871440
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.1162961157
Short name T199
Test name
Test status
Simulation time 495679720133 ps
CPU time 205.14 seconds
Started Jun 04 01:53:25 PM PDT 24
Finished Jun 04 01:56:51 PM PDT 24
Peak memory 201892 kb
Host smart-87101844-757e-49c9-8a07-dc331e87193d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162961157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.1162961157
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.3690155028
Short name T580
Test name
Test status
Simulation time 160168073356 ps
CPU time 99.7 seconds
Started Jun 04 01:53:20 PM PDT 24
Finished Jun 04 01:55:01 PM PDT 24
Peak memory 201752 kb
Host smart-64caa0bc-3825-4759-85a8-2d4a7bdfa3c3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690155028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.3690155028
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.1204223089
Short name T316
Test name
Test status
Simulation time 484331721415 ps
CPU time 523.79 seconds
Started Jun 04 01:53:19 PM PDT 24
Finished Jun 04 02:02:03 PM PDT 24
Peak memory 201736 kb
Host smart-fb994df7-d815-4970-be0b-5f63d712e788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204223089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.1204223089
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.719880339
Short name T442
Test name
Test status
Simulation time 325136130119 ps
CPU time 727.1 seconds
Started Jun 04 01:53:22 PM PDT 24
Finished Jun 04 02:05:30 PM PDT 24
Peak memory 201788 kb
Host smart-452ca325-4054-4524-981b-2a7e60c7e2fd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=719880339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fixe
d.719880339
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.505732625
Short name T157
Test name
Test status
Simulation time 183818464499 ps
CPU time 212.63 seconds
Started Jun 04 01:53:20 PM PDT 24
Finished Jun 04 01:56:53 PM PDT 24
Peak memory 201804 kb
Host smart-30f11086-5f35-436f-b9bf-ebc95a8d9511
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505732625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_
wakeup.505732625
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.2895094450
Short name T676
Test name
Test status
Simulation time 200593365600 ps
CPU time 227.96 seconds
Started Jun 04 01:53:25 PM PDT 24
Finished Jun 04 01:57:14 PM PDT 24
Peak memory 201800 kb
Host smart-5bfd0d22-4a38-48db-a44a-55ca73cb6b02
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895094450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.2895094450
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.391692050
Short name T758
Test name
Test status
Simulation time 39912427875 ps
CPU time 88.67 seconds
Started Jun 04 01:53:26 PM PDT 24
Finished Jun 04 01:54:56 PM PDT 24
Peak memory 201608 kb
Host smart-c902f550-604f-408f-ade6-e661abba62ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391692050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.391692050
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.1053240700
Short name T492
Test name
Test status
Simulation time 4727042967 ps
CPU time 12.98 seconds
Started Jun 04 01:53:23 PM PDT 24
Finished Jun 04 01:53:37 PM PDT 24
Peak memory 201564 kb
Host smart-73502020-2d59-46e8-a7b7-d842b40af8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053240700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.1053240700
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.4161669140
Short name T658
Test name
Test status
Simulation time 6096008944 ps
CPU time 4.52 seconds
Started Jun 04 01:53:19 PM PDT 24
Finished Jun 04 01:53:24 PM PDT 24
Peak memory 201592 kb
Host smart-96875620-863d-45d1-99a5-fca47d4398bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161669140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.4161669140
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.400841308
Short name T357
Test name
Test status
Simulation time 542241938318 ps
CPU time 1142.79 seconds
Started Jun 04 01:53:19 PM PDT 24
Finished Jun 04 02:12:22 PM PDT 24
Peak memory 202112 kb
Host smart-153b57f8-7ae6-46ef-820d-299a851847d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400841308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all.
400841308
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.448789678
Short name T733
Test name
Test status
Simulation time 226998403205 ps
CPU time 264.8 seconds
Started Jun 04 01:53:25 PM PDT 24
Finished Jun 04 01:57:50 PM PDT 24
Peak memory 210404 kb
Host smart-c5798b13-a3db-4e04-a34f-dc961ec7fb34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448789678 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.448789678
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.2563337867
Short name T726
Test name
Test status
Simulation time 317946597 ps
CPU time 0.92 seconds
Started Jun 04 01:53:28 PM PDT 24
Finished Jun 04 01:53:29 PM PDT 24
Peak memory 201472 kb
Host smart-ce3adedd-161b-4531-b829-e1a22877f1c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563337867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.2563337867
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.4246084609
Short name T170
Test name
Test status
Simulation time 331608875082 ps
CPU time 208.69 seconds
Started Jun 04 01:53:22 PM PDT 24
Finished Jun 04 01:56:52 PM PDT 24
Peak memory 201756 kb
Host smart-24773bfc-2a1f-4a11-b8e2-85735edd960b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246084609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.4246084609
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.3757395084
Short name T370
Test name
Test status
Simulation time 488750112824 ps
CPU time 1152.6 seconds
Started Jun 04 01:53:22 PM PDT 24
Finished Jun 04 02:12:36 PM PDT 24
Peak memory 201792 kb
Host smart-7a5e8aa4-199c-4aef-bee9-2bc64dfe7145
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757395084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.3757395084
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.481553638
Short name T334
Test name
Test status
Simulation time 166565937568 ps
CPU time 90.92 seconds
Started Jun 04 01:53:21 PM PDT 24
Finished Jun 04 01:54:53 PM PDT 24
Peak memory 201780 kb
Host smart-a673d1e4-e2a3-4c5e-b5e5-c578ffb3f756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481553638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.481553638
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.2499112604
Short name T456
Test name
Test status
Simulation time 320560398430 ps
CPU time 124.62 seconds
Started Jun 04 01:53:22 PM PDT 24
Finished Jun 04 01:55:28 PM PDT 24
Peak memory 201852 kb
Host smart-49d4967f-ae60-4802-93e0-985de0b9f9a1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499112604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.2499112604
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.2677566654
Short name T409
Test name
Test status
Simulation time 626355204509 ps
CPU time 697.64 seconds
Started Jun 04 01:53:22 PM PDT 24
Finished Jun 04 02:05:01 PM PDT 24
Peak memory 201812 kb
Host smart-896463fc-afc7-4d11-823b-b668355109d2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677566654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.2677566654
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.488411722
Short name T82
Test name
Test status
Simulation time 110216014988 ps
CPU time 405.11 seconds
Started Jun 04 01:53:24 PM PDT 24
Finished Jun 04 02:00:09 PM PDT 24
Peak memory 202096 kb
Host smart-ffc64694-324b-4648-b238-2718f2aef628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488411722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.488411722
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.2858120284
Short name T472
Test name
Test status
Simulation time 25468059561 ps
CPU time 60.76 seconds
Started Jun 04 01:53:27 PM PDT 24
Finished Jun 04 01:54:29 PM PDT 24
Peak memory 201620 kb
Host smart-0629d16a-2bee-4d21-b510-aa0fe1e66178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858120284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.2858120284
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.2245096672
Short name T428
Test name
Test status
Simulation time 3559739521 ps
CPU time 5.02 seconds
Started Jun 04 01:53:22 PM PDT 24
Finished Jun 04 01:53:28 PM PDT 24
Peak memory 201540 kb
Host smart-b6210e0e-dc99-4473-a022-d0c2461f8676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245096672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.2245096672
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.1599747371
Short name T748
Test name
Test status
Simulation time 5770926674 ps
CPU time 12.86 seconds
Started Jun 04 01:53:18 PM PDT 24
Finished Jun 04 01:53:32 PM PDT 24
Peak memory 201640 kb
Host smart-9e128744-3049-4153-92f6-3c030c7df9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599747371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.1599747371
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.1655979489
Short name T330
Test name
Test status
Simulation time 191240493543 ps
CPU time 441.92 seconds
Started Jun 04 01:53:27 PM PDT 24
Finished Jun 04 02:00:50 PM PDT 24
Peak memory 201764 kb
Host smart-caa0420f-b120-4b0c-ba50-2bc2c3de864e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655979489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.1655979489
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.1672104762
Short name T706
Test name
Test status
Simulation time 26583840421 ps
CPU time 62.74 seconds
Started Jun 04 01:53:29 PM PDT 24
Finished Jun 04 01:54:32 PM PDT 24
Peak memory 210424 kb
Host smart-d00e6b1c-d2e8-4ae7-929c-80d3d65f9812
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672104762 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.1672104762
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.1485240781
Short name T751
Test name
Test status
Simulation time 420454210 ps
CPU time 0.88 seconds
Started Jun 04 01:53:32 PM PDT 24
Finished Jun 04 01:53:34 PM PDT 24
Peak memory 201488 kb
Host smart-a7046422-8f8e-4bde-9d49-b53300207cba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485240781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.1485240781
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.902444356
Short name T103
Test name
Test status
Simulation time 162722773742 ps
CPU time 168.39 seconds
Started Jun 04 01:53:25 PM PDT 24
Finished Jun 04 01:56:15 PM PDT 24
Peak memory 201820 kb
Host smart-b32d8ab2-55cd-4a18-a5d4-f6fcb5308d49
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902444356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gati
ng.902444356
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.2159643502
Short name T282
Test name
Test status
Simulation time 354482697482 ps
CPU time 852.77 seconds
Started Jun 04 01:53:30 PM PDT 24
Finished Jun 04 02:07:44 PM PDT 24
Peak memory 201776 kb
Host smart-f6abca5f-3337-4cb6-91c4-d129947d7d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159643502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.2159643502
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.478571103
Short name T743
Test name
Test status
Simulation time 165029418375 ps
CPU time 384.26 seconds
Started Jun 04 01:53:32 PM PDT 24
Finished Jun 04 01:59:57 PM PDT 24
Peak memory 201772 kb
Host smart-fa542065-c027-489b-8abc-02742dea9d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478571103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.478571103
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.175417648
Short name T606
Test name
Test status
Simulation time 482396218266 ps
CPU time 612.17 seconds
Started Jun 04 01:53:24 PM PDT 24
Finished Jun 04 02:03:37 PM PDT 24
Peak memory 201804 kb
Host smart-1c9cd069-8f52-484a-a8cb-5de14c405d2c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=175417648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrup
t_fixed.175417648
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.1537307732
Short name T28
Test name
Test status
Simulation time 162915648023 ps
CPU time 184.31 seconds
Started Jun 04 01:53:23 PM PDT 24
Finished Jun 04 01:56:28 PM PDT 24
Peak memory 201620 kb
Host smart-d775f45d-a220-435a-a220-500744631689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537307732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.1537307732
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.3693282984
Short name T481
Test name
Test status
Simulation time 494262002136 ps
CPU time 599.73 seconds
Started Jun 04 01:53:31 PM PDT 24
Finished Jun 04 02:03:32 PM PDT 24
Peak memory 201816 kb
Host smart-b1009f6a-25a5-4311-82e8-c72a6d010fa3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693282984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.3693282984
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.2990111352
Short name T566
Test name
Test status
Simulation time 335599251018 ps
CPU time 376.04 seconds
Started Jun 04 01:53:25 PM PDT 24
Finished Jun 04 01:59:42 PM PDT 24
Peak memory 201832 kb
Host smart-9fda17f0-0839-4b41-8f66-ac620f8e3025
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990111352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.2990111352
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.3597666005
Short name T434
Test name
Test status
Simulation time 596816157278 ps
CPU time 368.95 seconds
Started Jun 04 01:53:23 PM PDT 24
Finished Jun 04 01:59:33 PM PDT 24
Peak memory 201872 kb
Host smart-993449cf-af72-44bd-9b64-38cc6ce22588
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597666005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.3597666005
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.276838098
Short name T687
Test name
Test status
Simulation time 36824337662 ps
CPU time 40.6 seconds
Started Jun 04 01:53:33 PM PDT 24
Finished Jun 04 01:54:14 PM PDT 24
Peak memory 201540 kb
Host smart-7714fdc1-1a1e-4928-86f1-25eeb084f12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276838098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.276838098
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.1467902254
Short name T471
Test name
Test status
Simulation time 3541755704 ps
CPU time 9.63 seconds
Started Jun 04 01:53:38 PM PDT 24
Finished Jun 04 01:53:49 PM PDT 24
Peak memory 201556 kb
Host smart-b8e91f9b-c5ef-427c-bab1-94a4c5aab6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467902254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.1467902254
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.2975990097
Short name T418
Test name
Test status
Simulation time 5832743961 ps
CPU time 1.95 seconds
Started Jun 04 01:53:25 PM PDT 24
Finished Jun 04 01:53:27 PM PDT 24
Peak memory 201464 kb
Host smart-2100a367-6acc-4cf1-b4bf-23b491766824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975990097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.2975990097
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.1241972414
Short name T574
Test name
Test status
Simulation time 342924250453 ps
CPU time 82.11 seconds
Started Jun 04 01:53:34 PM PDT 24
Finished Jun 04 01:54:57 PM PDT 24
Peak memory 201748 kb
Host smart-f41ef77c-a149-4f83-a30e-cc46ece9ac21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241972414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.1241972414
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.171428152
Short name T314
Test name
Test status
Simulation time 105214413184 ps
CPU time 274.33 seconds
Started Jun 04 01:53:33 PM PDT 24
Finished Jun 04 01:58:08 PM PDT 24
Peak memory 210400 kb
Host smart-eee0e9d6-b638-439c-8076-502def9383ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171428152 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.171428152
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.1100629033
Short name T728
Test name
Test status
Simulation time 463361330 ps
CPU time 1.13 seconds
Started Jun 04 01:53:38 PM PDT 24
Finished Jun 04 01:53:40 PM PDT 24
Peak memory 201416 kb
Host smart-eb27411f-0385-41ea-83ce-de778399353a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100629033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.1100629033
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.160379938
Short name T27
Test name
Test status
Simulation time 321096252701 ps
CPU time 745.75 seconds
Started Jun 04 01:53:39 PM PDT 24
Finished Jun 04 02:06:06 PM PDT 24
Peak memory 201876 kb
Host smart-f739bca5-c34e-4609-8cda-ecfa79443170
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160379938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gati
ng.160379938
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.805125890
Short name T2
Test name
Test status
Simulation time 383027615046 ps
CPU time 926 seconds
Started Jun 04 01:53:45 PM PDT 24
Finished Jun 04 02:09:11 PM PDT 24
Peak memory 201888 kb
Host smart-430e8d0f-ee36-4fa1-80bf-82c2a191e4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805125890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.805125890
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.2124588552
Short name T277
Test name
Test status
Simulation time 167623073187 ps
CPU time 116.95 seconds
Started Jun 04 01:53:33 PM PDT 24
Finished Jun 04 01:55:30 PM PDT 24
Peak memory 201844 kb
Host smart-3947c374-6887-4d18-ad5e-f5409688b292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124588552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.2124588552
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.676705327
Short name T582
Test name
Test status
Simulation time 326786412052 ps
CPU time 114.02 seconds
Started Jun 04 01:53:43 PM PDT 24
Finished Jun 04 01:55:37 PM PDT 24
Peak memory 201908 kb
Host smart-dc0e461c-71ae-4bd4-ae8b-79bbf14e3c88
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=676705327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrup
t_fixed.676705327
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.97491852
Short name T306
Test name
Test status
Simulation time 164402633241 ps
CPU time 389.51 seconds
Started Jun 04 01:53:32 PM PDT 24
Finished Jun 04 02:00:02 PM PDT 24
Peak memory 201616 kb
Host smart-4c8994dc-2749-4db5-92ed-8b39bec4df0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97491852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.97491852
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.1417009606
Short name T177
Test name
Test status
Simulation time 326619714820 ps
CPU time 615.01 seconds
Started Jun 04 01:53:36 PM PDT 24
Finished Jun 04 02:03:52 PM PDT 24
Peak memory 201748 kb
Host smart-f5b0a4c8-275b-4922-98d6-6ef57f23b0ae
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417009606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.1417009606
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.3613917004
Short name T563
Test name
Test status
Simulation time 390429968952 ps
CPU time 872.02 seconds
Started Jun 04 01:53:41 PM PDT 24
Finished Jun 04 02:08:14 PM PDT 24
Peak memory 201884 kb
Host smart-034c42f1-5b23-447f-bdca-e1716903f20e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613917004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.3613917004
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.3936175929
Short name T441
Test name
Test status
Simulation time 36731182736 ps
CPU time 44.75 seconds
Started Jun 04 01:53:38 PM PDT 24
Finished Jun 04 01:54:24 PM PDT 24
Peak memory 201596 kb
Host smart-b65df392-adc7-4ce5-a4ee-100d768ab2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936175929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.3936175929
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.2869887617
Short name T140
Test name
Test status
Simulation time 3556993120 ps
CPU time 8.07 seconds
Started Jun 04 01:53:39 PM PDT 24
Finished Jun 04 01:53:47 PM PDT 24
Peak memory 201624 kb
Host smart-baac4b12-6674-436d-9286-f4a5e644ae4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869887617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.2869887617
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.1830214521
Short name T112
Test name
Test status
Simulation time 5621468899 ps
CPU time 14.57 seconds
Started Jun 04 01:53:31 PM PDT 24
Finished Jun 04 01:53:46 PM PDT 24
Peak memory 201604 kb
Host smart-94d49c94-db30-4e5e-b497-6f27fcf7ed13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830214521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.1830214521
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.1672474607
Short name T460
Test name
Test status
Simulation time 471415289 ps
CPU time 0.76 seconds
Started Jun 04 01:53:47 PM PDT 24
Finished Jun 04 01:53:49 PM PDT 24
Peak memory 201440 kb
Host smart-0de7c843-4b92-456f-8b2f-7dab24f149dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672474607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.1672474607
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.98546561
Short name T309
Test name
Test status
Simulation time 346672324450 ps
CPU time 885.82 seconds
Started Jun 04 01:53:48 PM PDT 24
Finished Jun 04 02:08:35 PM PDT 24
Peak memory 201772 kb
Host smart-5b5a5213-41fe-49ce-b004-d39b7b901c8b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98546561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gatin
g.98546561
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.539351004
Short name T181
Test name
Test status
Simulation time 490578508101 ps
CPU time 282.01 seconds
Started Jun 04 01:53:40 PM PDT 24
Finished Jun 04 01:58:23 PM PDT 24
Peak memory 201804 kb
Host smart-6650f87e-59fa-4b90-a969-e3d80353657f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=539351004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrup
t_fixed.539351004
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.626546520
Short name T778
Test name
Test status
Simulation time 159518154539 ps
CPU time 85.02 seconds
Started Jun 04 01:53:45 PM PDT 24
Finished Jun 04 01:55:10 PM PDT 24
Peak memory 201876 kb
Host smart-0a23291e-dc97-4ee9-b5a9-184ae7f1ea0d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=626546520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fixe
d.626546520
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.895815111
Short name T753
Test name
Test status
Simulation time 379412677470 ps
CPU time 875.49 seconds
Started Jun 04 01:53:48 PM PDT 24
Finished Jun 04 02:08:24 PM PDT 24
Peak memory 201812 kb
Host smart-89eae594-8530-42a2-9d6d-8484148d2e87
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895815111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_
wakeup.895815111
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.2495919666
Short name T189
Test name
Test status
Simulation time 199014075514 ps
CPU time 28.74 seconds
Started Jun 04 01:53:48 PM PDT 24
Finished Jun 04 01:54:17 PM PDT 24
Peak memory 201804 kb
Host smart-bb9e2524-5796-4dda-8b97-9103ae3ad90a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495919666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.2495919666
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.1806654409
Short name T454
Test name
Test status
Simulation time 118156941747 ps
CPU time 662.89 seconds
Started Jun 04 01:53:47 PM PDT 24
Finished Jun 04 02:04:51 PM PDT 24
Peak memory 202116 kb
Host smart-630ced52-e660-4a6b-a698-6c462ee0e8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806654409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.1806654409
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.2322786916
Short name T775
Test name
Test status
Simulation time 24514112033 ps
CPU time 56.14 seconds
Started Jun 04 01:53:48 PM PDT 24
Finished Jun 04 01:54:44 PM PDT 24
Peak memory 201572 kb
Host smart-03c3dd95-bee1-4596-bda1-68a209744085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322786916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.2322786916
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.1744892201
Short name T787
Test name
Test status
Simulation time 2943103905 ps
CPU time 2.49 seconds
Started Jun 04 01:53:46 PM PDT 24
Finished Jun 04 01:53:49 PM PDT 24
Peak memory 201600 kb
Host smart-341e1f47-f470-4765-b515-a80cdf356833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744892201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.1744892201
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.2717167786
Short name T98
Test name
Test status
Simulation time 5975441533 ps
CPU time 15.4 seconds
Started Jun 04 01:53:38 PM PDT 24
Finished Jun 04 01:53:54 PM PDT 24
Peak memory 201644 kb
Host smart-d24905e7-0df3-41cf-8378-e6c030d50ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717167786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.2717167786
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.1625594638
Short name T663
Test name
Test status
Simulation time 200797583862 ps
CPU time 117.47 seconds
Started Jun 04 01:53:45 PM PDT 24
Finished Jun 04 01:55:43 PM PDT 24
Peak memory 201804 kb
Host smart-9c46b7b9-ff66-49e0-b89d-4ac8c9686bd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625594638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.1625594638
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.3754661106
Short name T698
Test name
Test status
Simulation time 480467851 ps
CPU time 0.87 seconds
Started Jun 04 01:53:51 PM PDT 24
Finished Jun 04 01:53:52 PM PDT 24
Peak memory 201492 kb
Host smart-202d8fdc-259a-40c7-a71d-e717a677a5d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754661106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.3754661106
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.583060188
Short name T171
Test name
Test status
Simulation time 347134927194 ps
CPU time 211.3 seconds
Started Jun 04 01:53:47 PM PDT 24
Finished Jun 04 01:57:18 PM PDT 24
Peak memory 201868 kb
Host smart-e81a0798-f167-4f1b-9760-681aa60badef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583060188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gati
ng.583060188
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.2062491098
Short name T750
Test name
Test status
Simulation time 160879658706 ps
CPU time 100.39 seconds
Started Jun 04 01:53:47 PM PDT 24
Finished Jun 04 01:55:28 PM PDT 24
Peak memory 201772 kb
Host smart-08e1f1ba-4f0c-44d1-8aea-4f01792e9693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062491098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.2062491098
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.1832761773
Short name T777
Test name
Test status
Simulation time 168308520577 ps
CPU time 105.02 seconds
Started Jun 04 01:53:46 PM PDT 24
Finished Jun 04 01:55:31 PM PDT 24
Peak memory 201772 kb
Host smart-04a5f814-6939-4368-b779-0eebe6db07e2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832761773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.1832761773
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.4205348089
Short name T230
Test name
Test status
Simulation time 323603192506 ps
CPU time 278.54 seconds
Started Jun 04 01:53:47 PM PDT 24
Finished Jun 04 01:58:26 PM PDT 24
Peak memory 201800 kb
Host smart-67ec8fa9-424a-4077-b472-8a6dd58200f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205348089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.4205348089
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.36092124
Short name T81
Test name
Test status
Simulation time 493583087389 ps
CPU time 206.66 seconds
Started Jun 04 01:53:46 PM PDT 24
Finished Jun 04 01:57:13 PM PDT 24
Peak memory 201880 kb
Host smart-34d8325c-fb33-4dcc-877a-e6e31d08219c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=36092124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fixed
.36092124
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.2496650651
Short name T212
Test name
Test status
Simulation time 197406176534 ps
CPU time 150.84 seconds
Started Jun 04 01:53:47 PM PDT 24
Finished Jun 04 01:56:19 PM PDT 24
Peak memory 201804 kb
Host smart-f521fa6c-828f-4d21-980d-4d5f88200fd2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496650651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.2496650651
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.2388850498
Short name T322
Test name
Test status
Simulation time 608998069013 ps
CPU time 684.21 seconds
Started Jun 04 01:53:48 PM PDT 24
Finished Jun 04 02:05:13 PM PDT 24
Peak memory 201820 kb
Host smart-9886ee2e-dec9-428f-a0ee-bb47ccd0ffa7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388850498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.2388850498
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.2071185773
Short name T722
Test name
Test status
Simulation time 136045591775 ps
CPU time 446.97 seconds
Started Jun 04 01:53:51 PM PDT 24
Finished Jun 04 02:01:19 PM PDT 24
Peak memory 202140 kb
Host smart-495772a3-031c-4caa-8d10-48c0c42ec79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071185773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.2071185773
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.3250684408
Short name T615
Test name
Test status
Simulation time 33942323581 ps
CPU time 74.86 seconds
Started Jun 04 01:53:51 PM PDT 24
Finished Jun 04 01:55:06 PM PDT 24
Peak memory 201572 kb
Host smart-741c8777-bd55-44ab-a383-44b4ae4ed983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250684408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.3250684408
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.535637595
Short name T720
Test name
Test status
Simulation time 5491759058 ps
CPU time 13.87 seconds
Started Jun 04 01:53:52 PM PDT 24
Finished Jun 04 01:54:07 PM PDT 24
Peak memory 201616 kb
Host smart-145a6ad1-2ff8-4b6a-bcaf-fbdc28408d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535637595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.535637595
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.1913663894
Short name T119
Test name
Test status
Simulation time 6138335157 ps
CPU time 12.1 seconds
Started Jun 04 01:53:46 PM PDT 24
Finished Jun 04 01:53:58 PM PDT 24
Peak memory 201636 kb
Host smart-d91b025d-3c49-44cb-bbb4-b184f475fdbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913663894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.1913663894
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.579201450
Short name T308
Test name
Test status
Simulation time 168002831421 ps
CPU time 15.33 seconds
Started Jun 04 01:53:51 PM PDT 24
Finished Jun 04 01:54:07 PM PDT 24
Peak memory 201752 kb
Host smart-14896992-9ba6-47e0-afb5-53c87e2e6149
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579201450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all.
579201450
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.3096040652
Short name T721
Test name
Test status
Simulation time 197301930931 ps
CPU time 216.06 seconds
Started Jun 04 01:53:51 PM PDT 24
Finished Jun 04 01:57:28 PM PDT 24
Peak memory 210484 kb
Host smart-c36518f7-96a5-4752-a7b4-270cdff7b6de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096040652 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.3096040652
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.1480790055
Short name T398
Test name
Test status
Simulation time 305177886 ps
CPU time 0.81 seconds
Started Jun 04 01:52:43 PM PDT 24
Finished Jun 04 01:52:44 PM PDT 24
Peak memory 201456 kb
Host smart-3e468384-843d-4297-9f2d-ce58b9872a3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480790055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.1480790055
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.3053234870
Short name T342
Test name
Test status
Simulation time 215097244748 ps
CPU time 161.36 seconds
Started Jun 04 01:52:40 PM PDT 24
Finished Jun 04 01:55:22 PM PDT 24
Peak memory 201852 kb
Host smart-561989c3-2539-4c37-bd55-801543bba83f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053234870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.3053234870
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.786975217
Short name T784
Test name
Test status
Simulation time 325337991513 ps
CPU time 728.46 seconds
Started Jun 04 01:52:34 PM PDT 24
Finished Jun 04 02:04:44 PM PDT 24
Peak memory 201732 kb
Host smart-34cd600c-2e18-4745-a63a-c2b8dbfe50f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786975217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.786975217
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.4185564025
Short name T146
Test name
Test status
Simulation time 171249096286 ps
CPU time 49.98 seconds
Started Jun 04 01:52:59 PM PDT 24
Finished Jun 04 01:53:51 PM PDT 24
Peak memory 201916 kb
Host smart-466e78a0-fab0-41d2-a88e-390f57fedf05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185564025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.4185564025
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.3775511321
Short name T534
Test name
Test status
Simulation time 159865843226 ps
CPU time 31.36 seconds
Started Jun 04 01:52:35 PM PDT 24
Finished Jun 04 01:53:08 PM PDT 24
Peak memory 201772 kb
Host smart-0cb6d82e-3fb6-4034-a1b9-85c18056e416
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775511321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.3775511321
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.243377842
Short name T158
Test name
Test status
Simulation time 167858463886 ps
CPU time 391.59 seconds
Started Jun 04 01:52:33 PM PDT 24
Finished Jun 04 01:59:07 PM PDT 24
Peak memory 201732 kb
Host smart-34de0ae9-553a-44ad-b2ff-b4c9fec2ccad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243377842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.243377842
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.3558785388
Short name T776
Test name
Test status
Simulation time 159734909563 ps
CPU time 39.51 seconds
Started Jun 04 01:52:28 PM PDT 24
Finished Jun 04 01:53:10 PM PDT 24
Peak memory 201808 kb
Host smart-65b45557-31fa-4960-ac26-3d91e3ddd3aa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558785388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.3558785388
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.3586273660
Short name T288
Test name
Test status
Simulation time 165825508648 ps
CPU time 68.61 seconds
Started Jun 04 01:52:34 PM PDT 24
Finished Jun 04 01:53:44 PM PDT 24
Peak memory 201868 kb
Host smart-f177533a-2784-4f59-8518-5905c4e3cb45
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586273660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.3586273660
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.2372909552
Short name T511
Test name
Test status
Simulation time 204856543469 ps
CPU time 105.97 seconds
Started Jun 04 01:52:36 PM PDT 24
Finished Jun 04 01:54:23 PM PDT 24
Peak memory 201728 kb
Host smart-3959fa9c-474c-4903-a30e-c124edd798e8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372909552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.2372909552
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.829139341
Short name T712
Test name
Test status
Simulation time 110698333187 ps
CPU time 384.02 seconds
Started Jun 04 01:52:43 PM PDT 24
Finished Jun 04 01:59:08 PM PDT 24
Peak memory 202192 kb
Host smart-c8eef704-a7ce-4937-b9b0-dc89ed369c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829139341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.829139341
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.2866724727
Short name T557
Test name
Test status
Simulation time 39722346607 ps
CPU time 24.03 seconds
Started Jun 04 01:52:33 PM PDT 24
Finished Jun 04 01:52:59 PM PDT 24
Peak memory 201560 kb
Host smart-cb0c6863-b808-4259-be45-b0e0b60ce39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866724727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.2866724727
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.3580556222
Short name T106
Test name
Test status
Simulation time 3428331908 ps
CPU time 8.25 seconds
Started Jun 04 01:52:39 PM PDT 24
Finished Jun 04 01:52:48 PM PDT 24
Peak memory 201600 kb
Host smart-2730a24b-e7e1-406d-a6ea-f222741c7aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580556222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.3580556222
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.4238652710
Short name T62
Test name
Test status
Simulation time 4263711353 ps
CPU time 3 seconds
Started Jun 04 01:52:34 PM PDT 24
Finished Jun 04 01:52:39 PM PDT 24
Peak memory 217244 kb
Host smart-cee893d4-bd5d-49fd-a996-50e663dd5dd3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238652710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.4238652710
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.3547781640
Short name T378
Test name
Test status
Simulation time 5632472839 ps
CPU time 15.3 seconds
Started Jun 04 01:52:29 PM PDT 24
Finished Jun 04 01:52:46 PM PDT 24
Peak memory 201604 kb
Host smart-1fe981c7-3e0b-4801-b44e-0e04f5f3e8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547781640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.3547781640
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.238766334
Short name T284
Test name
Test status
Simulation time 350531098842 ps
CPU time 855.1 seconds
Started Jun 04 01:52:35 PM PDT 24
Finished Jun 04 02:06:52 PM PDT 24
Peak memory 201808 kb
Host smart-7c39b0ec-e441-443b-a574-4b6fa0434541
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238766334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.238766334
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.2897549831
Short name T301
Test name
Test status
Simulation time 124984705351 ps
CPU time 204.72 seconds
Started Jun 04 01:52:50 PM PDT 24
Finished Jun 04 01:56:15 PM PDT 24
Peak memory 210480 kb
Host smart-318174a1-5826-451d-98a6-2b819924c03a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897549831 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.2897549831
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.2878660670
Short name T499
Test name
Test status
Simulation time 511174072 ps
CPU time 1.84 seconds
Started Jun 04 01:54:01 PM PDT 24
Finished Jun 04 01:54:03 PM PDT 24
Peak memory 201484 kb
Host smart-992e307c-76c1-4902-8c3c-632660d1f352
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878660670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.2878660670
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.1991941528
Short name T32
Test name
Test status
Simulation time 325885332692 ps
CPU time 718.72 seconds
Started Jun 04 01:53:50 PM PDT 24
Finished Jun 04 02:05:50 PM PDT 24
Peak memory 201812 kb
Host smart-cf538cb1-f6c9-4633-851a-4e0c85b7f0cc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991941528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.1991941528
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.3779941849
Short name T208
Test name
Test status
Simulation time 539441653870 ps
CPU time 306.3 seconds
Started Jun 04 01:53:50 PM PDT 24
Finished Jun 04 01:58:57 PM PDT 24
Peak memory 201816 kb
Host smart-5a4967d7-b2a8-40d6-9f67-a1113c72fdb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779941849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.3779941849
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.4169978742
Short name T337
Test name
Test status
Simulation time 167616788690 ps
CPU time 125.33 seconds
Started Jun 04 01:53:52 PM PDT 24
Finished Jun 04 01:55:57 PM PDT 24
Peak memory 201804 kb
Host smart-08f66127-2d34-4aa1-b2a8-13513bb74152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169978742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.4169978742
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.3215221558
Short name T561
Test name
Test status
Simulation time 481324094513 ps
CPU time 897.85 seconds
Started Jun 04 01:53:51 PM PDT 24
Finished Jun 04 02:08:49 PM PDT 24
Peak memory 201808 kb
Host smart-33264cfb-abfb-4986-9972-53d5cdf0c34a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215221558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.3215221558
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.2026350648
Short name T450
Test name
Test status
Simulation time 493045807777 ps
CPU time 1130.87 seconds
Started Jun 04 01:53:51 PM PDT 24
Finished Jun 04 02:12:43 PM PDT 24
Peak memory 201768 kb
Host smart-3b007247-2a61-4bb6-b444-c8418d4381ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026350648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.2026350648
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.2738231401
Short name T680
Test name
Test status
Simulation time 504244966929 ps
CPU time 1290.05 seconds
Started Jun 04 01:53:51 PM PDT 24
Finished Jun 04 02:15:22 PM PDT 24
Peak memory 201824 kb
Host smart-33e11fc3-314d-492d-b068-7b3234b3c55f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738231401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.2738231401
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.861111007
Short name T752
Test name
Test status
Simulation time 411560626895 ps
CPU time 495.3 seconds
Started Jun 04 01:53:54 PM PDT 24
Finished Jun 04 02:02:10 PM PDT 24
Peak memory 201808 kb
Host smart-8cffb7cf-7eaa-4616-9dfc-17e1172ff9ff
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861111007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
adc_ctrl_filters_wakeup_fixed.861111007
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.3985596399
Short name T605
Test name
Test status
Simulation time 99632175673 ps
CPU time 370.67 seconds
Started Jun 04 01:53:56 PM PDT 24
Finished Jun 04 02:00:08 PM PDT 24
Peak memory 202180 kb
Host smart-f3ce98dd-782d-42dc-bc73-4e60e9c4c128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985596399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.3985596399
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.535606512
Short name T562
Test name
Test status
Simulation time 24098044300 ps
CPU time 57.92 seconds
Started Jun 04 01:53:51 PM PDT 24
Finished Jun 04 01:54:50 PM PDT 24
Peak memory 201608 kb
Host smart-7c9480f2-26d3-4fee-b83f-9f6e7ecfa4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535606512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.535606512
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.2570116250
Short name T392
Test name
Test status
Simulation time 3252190444 ps
CPU time 3.05 seconds
Started Jun 04 01:53:52 PM PDT 24
Finished Jun 04 01:53:56 PM PDT 24
Peak memory 201596 kb
Host smart-8aba221f-e67e-4318-8c62-6f9ef81da917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570116250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.2570116250
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.3819062656
Short name T656
Test name
Test status
Simulation time 5930851190 ps
CPU time 4.86 seconds
Started Jun 04 01:53:51 PM PDT 24
Finished Jun 04 01:53:56 PM PDT 24
Peak memory 201656 kb
Host smart-ea77d3be-6181-4a31-8ddb-561e5a9a0d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819062656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.3819062656
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.3595064013
Short name T423
Test name
Test status
Simulation time 17203293162 ps
CPU time 40.38 seconds
Started Jun 04 01:53:59 PM PDT 24
Finished Jun 04 01:54:40 PM PDT 24
Peak memory 201820 kb
Host smart-48a276c7-9f16-4c1d-877d-24f641389776
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595064013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.3595064013
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.2265179437
Short name T608
Test name
Test status
Simulation time 463162904 ps
CPU time 1.55 seconds
Started Jun 04 01:54:05 PM PDT 24
Finished Jun 04 01:54:07 PM PDT 24
Peak memory 201444 kb
Host smart-31c7f6a9-4ae9-457f-8092-b124d09f3942
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265179437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.2265179437
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.2586387998
Short name T150
Test name
Test status
Simulation time 190052277586 ps
CPU time 456.18 seconds
Started Jun 04 01:54:00 PM PDT 24
Finished Jun 04 02:01:37 PM PDT 24
Peak memory 201780 kb
Host smart-16b95f41-75a7-4aa2-949d-6c660db096bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586387998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.2586387998
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.4226689683
Short name T197
Test name
Test status
Simulation time 493333320014 ps
CPU time 103.69 seconds
Started Jun 04 01:53:57 PM PDT 24
Finished Jun 04 01:55:41 PM PDT 24
Peak memory 201800 kb
Host smart-15032169-68e3-4127-94ae-cd12a3c76bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226689683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.4226689683
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.726053097
Short name T640
Test name
Test status
Simulation time 325217308226 ps
CPU time 727.09 seconds
Started Jun 04 01:53:58 PM PDT 24
Finished Jun 04 02:06:06 PM PDT 24
Peak memory 201804 kb
Host smart-a04c0fc6-108e-4ec8-bb0a-095ffacdb8e7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=726053097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrup
t_fixed.726053097
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.2147553783
Short name T403
Test name
Test status
Simulation time 338893855846 ps
CPU time 851.29 seconds
Started Jun 04 01:54:01 PM PDT 24
Finished Jun 04 02:08:13 PM PDT 24
Peak memory 201768 kb
Host smart-de98a54e-b5a1-4e01-a414-66c5a2363b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147553783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.2147553783
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.4222061250
Short name T498
Test name
Test status
Simulation time 321471135833 ps
CPU time 782.53 seconds
Started Jun 04 01:53:58 PM PDT 24
Finished Jun 04 02:07:02 PM PDT 24
Peak memory 201852 kb
Host smart-6367f92e-e736-4f19-8e0a-5067226bfc74
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222061250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.4222061250
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.2132877726
Short name T487
Test name
Test status
Simulation time 596588937754 ps
CPU time 1375.03 seconds
Started Jun 04 01:53:59 PM PDT 24
Finished Jun 04 02:16:55 PM PDT 24
Peak memory 201800 kb
Host smart-a368239e-dac5-4992-8806-3838bbb42d88
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132877726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.2132877726
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.2491179359
Short name T455
Test name
Test status
Simulation time 136186489363 ps
CPU time 473.67 seconds
Started Jun 04 01:54:06 PM PDT 24
Finished Jun 04 02:02:01 PM PDT 24
Peak memory 202112 kb
Host smart-7d8a6d86-0a71-4d09-9d3d-58a01789877b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491179359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.2491179359
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.4161322653
Short name T789
Test name
Test status
Simulation time 35899814756 ps
CPU time 9.01 seconds
Started Jun 04 01:54:06 PM PDT 24
Finished Jun 04 01:54:15 PM PDT 24
Peak memory 201540 kb
Host smart-9a468c8d-b2a7-4813-b5c6-e98d4df7cfc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161322653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.4161322653
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.188390041
Short name T700
Test name
Test status
Simulation time 2940627231 ps
CPU time 5.14 seconds
Started Jun 04 01:53:58 PM PDT 24
Finished Jun 04 01:54:03 PM PDT 24
Peak memory 201500 kb
Host smart-4670b447-7734-4843-a785-455617934463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188390041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.188390041
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.750922640
Short name T466
Test name
Test status
Simulation time 6091262967 ps
CPU time 4.89 seconds
Started Jun 04 01:53:59 PM PDT 24
Finished Jun 04 01:54:05 PM PDT 24
Peak memory 201656 kb
Host smart-8744a418-50a8-45f8-bfc8-7ebc7a0c5127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750922640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.750922640
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.3300627870
Short name T470
Test name
Test status
Simulation time 142553820199 ps
CPU time 438.53 seconds
Started Jun 04 01:54:06 PM PDT 24
Finished Jun 04 02:01:25 PM PDT 24
Peak memory 202168 kb
Host smart-6edced6d-0d6a-4665-904b-8302d3309a4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300627870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.3300627870
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.2291111011
Short name T276
Test name
Test status
Simulation time 49517093002 ps
CPU time 37.35 seconds
Started Jun 04 01:54:06 PM PDT 24
Finished Jun 04 01:54:44 PM PDT 24
Peak memory 210176 kb
Host smart-cb4b444b-91e3-43c0-a50c-80e961b06764
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291111011 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.2291111011
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.3213149121
Short name T386
Test name
Test status
Simulation time 497854581 ps
CPU time 0.95 seconds
Started Jun 04 01:54:16 PM PDT 24
Finished Jun 04 01:54:18 PM PDT 24
Peak memory 201500 kb
Host smart-6031abfb-1f34-49f0-adf6-7466b2b296c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213149121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.3213149121
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.2929809580
Short name T666
Test name
Test status
Simulation time 361488108984 ps
CPU time 116.68 seconds
Started Jun 04 01:54:06 PM PDT 24
Finished Jun 04 01:56:04 PM PDT 24
Peak memory 201772 kb
Host smart-746e50a4-73aa-4de2-a01b-63305705e5f9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929809580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.2929809580
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.4116854114
Short name T695
Test name
Test status
Simulation time 162627684906 ps
CPU time 402.45 seconds
Started Jun 04 01:54:07 PM PDT 24
Finished Jun 04 02:00:50 PM PDT 24
Peak memory 201764 kb
Host smart-4a1e6ef9-d8ff-4801-a366-99e06d02a3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116854114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.4116854114
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.3144348813
Short name T577
Test name
Test status
Simulation time 162384660627 ps
CPU time 350.8 seconds
Started Jun 04 01:54:07 PM PDT 24
Finished Jun 04 01:59:59 PM PDT 24
Peak memory 201796 kb
Host smart-0f482ddd-e861-4dc1-8934-090e497206e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144348813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.3144348813
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.237496368
Short name T482
Test name
Test status
Simulation time 159729962979 ps
CPU time 200.22 seconds
Started Jun 04 01:54:08 PM PDT 24
Finished Jun 04 01:57:29 PM PDT 24
Peak memory 201764 kb
Host smart-bedafe10-57dd-4e6d-aa24-d12a74941e69
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=237496368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrup
t_fixed.237496368
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.3470848572
Short name T324
Test name
Test status
Simulation time 326790071665 ps
CPU time 190.15 seconds
Started Jun 04 01:54:05 PM PDT 24
Finished Jun 04 01:57:16 PM PDT 24
Peak memory 201860 kb
Host smart-f4728bea-69d9-4e44-9131-4213c20f8b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470848572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.3470848572
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.1622880808
Short name T156
Test name
Test status
Simulation time 328196939788 ps
CPU time 800.26 seconds
Started Jun 04 01:54:08 PM PDT 24
Finished Jun 04 02:07:29 PM PDT 24
Peak memory 201712 kb
Host smart-b2b26a07-cf27-4914-b43c-be51fab7d905
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622880808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.1622880808
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.1417593301
Short name T297
Test name
Test status
Simulation time 626502185769 ps
CPU time 726.57 seconds
Started Jun 04 01:54:06 PM PDT 24
Finished Jun 04 02:06:14 PM PDT 24
Peak memory 201768 kb
Host smart-4d75b5d6-871f-49df-a771-b6996a8799e1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417593301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.1417593301
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.1619526608
Short name T740
Test name
Test status
Simulation time 405630947279 ps
CPU time 229.08 seconds
Started Jun 04 01:54:08 PM PDT 24
Finished Jun 04 01:57:58 PM PDT 24
Peak memory 201872 kb
Host smart-6d80e617-e544-40a8-91b1-0223ba212666
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619526608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.1619526608
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.2117524145
Short name T620
Test name
Test status
Simulation time 34736009756 ps
CPU time 82.17 seconds
Started Jun 04 01:54:16 PM PDT 24
Finished Jun 04 01:55:40 PM PDT 24
Peak memory 201608 kb
Host smart-097dfd79-52da-4b7b-89cb-4c2e7185bb1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117524145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.2117524145
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.97727875
Short name T373
Test name
Test status
Simulation time 3757116581 ps
CPU time 1.47 seconds
Started Jun 04 01:54:14 PM PDT 24
Finished Jun 04 01:54:16 PM PDT 24
Peak memory 201624 kb
Host smart-3bd7e237-9eb7-424e-81d8-507c5a55f0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97727875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.97727875
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.2472872138
Short name T622
Test name
Test status
Simulation time 5938496004 ps
CPU time 4.18 seconds
Started Jun 04 01:54:07 PM PDT 24
Finished Jun 04 01:54:12 PM PDT 24
Peak memory 201604 kb
Host smart-cb08d56b-1a0b-4e28-aa60-3ad18fff7584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472872138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.2472872138
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.3985821681
Short name T725
Test name
Test status
Simulation time 195238274680 ps
CPU time 110.6 seconds
Started Jun 04 01:54:16 PM PDT 24
Finished Jun 04 01:56:08 PM PDT 24
Peak memory 201876 kb
Host smart-f16de3f8-5ec1-44e3-a3e5-776f5495567f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985821681 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.3985821681
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.2318072415
Short name T92
Test name
Test status
Simulation time 522140150 ps
CPU time 1.22 seconds
Started Jun 04 01:54:23 PM PDT 24
Finished Jun 04 01:54:25 PM PDT 24
Peak memory 201500 kb
Host smart-5e94dd9e-049e-4329-b8b2-406196e5549d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318072415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.2318072415
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.2387245598
Short name T235
Test name
Test status
Simulation time 489236365916 ps
CPU time 1129.18 seconds
Started Jun 04 01:54:16 PM PDT 24
Finished Jun 04 02:13:06 PM PDT 24
Peak memory 201784 kb
Host smart-447c871f-ddc4-460d-ac4f-00b4275ab924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387245598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.2387245598
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.3402546179
Short name T364
Test name
Test status
Simulation time 165730067644 ps
CPU time 382.59 seconds
Started Jun 04 01:54:15 PM PDT 24
Finished Jun 04 02:00:38 PM PDT 24
Peak memory 201804 kb
Host smart-fd5f3558-c236-4362-b04a-0e6d9cb209b4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402546179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.3402546179
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.1199561756
Short name T317
Test name
Test status
Simulation time 325399567931 ps
CPU time 356.06 seconds
Started Jun 04 01:54:17 PM PDT 24
Finished Jun 04 02:00:14 PM PDT 24
Peak memory 201792 kb
Host smart-0ac34744-5481-458f-a582-8f3dadd03fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199561756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.1199561756
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.862780654
Short name T500
Test name
Test status
Simulation time 163890162393 ps
CPU time 382.8 seconds
Started Jun 04 01:54:16 PM PDT 24
Finished Jun 04 02:00:40 PM PDT 24
Peak memory 201700 kb
Host smart-7a8ac5ab-2dbf-4025-90ee-c0f707930310
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=862780654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fixe
d.862780654
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.2394184895
Short name T248
Test name
Test status
Simulation time 393750568521 ps
CPU time 868.08 seconds
Started Jun 04 01:54:16 PM PDT 24
Finished Jun 04 02:08:45 PM PDT 24
Peak memory 201804 kb
Host smart-077dadca-f163-4d92-9cfd-2ff67a5cbdfc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394184895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.2394184895
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.2946871090
Short name T367
Test name
Test status
Simulation time 607432666933 ps
CPU time 365.52 seconds
Started Jun 04 01:54:15 PM PDT 24
Finished Jun 04 02:00:21 PM PDT 24
Peak memory 201788 kb
Host smart-9fde9e2c-1219-4dcc-89fa-3f719ea07f79
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946871090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.2946871090
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.2495899869
Short name T353
Test name
Test status
Simulation time 110608601609 ps
CPU time 561.55 seconds
Started Jun 04 01:54:21 PM PDT 24
Finished Jun 04 02:03:43 PM PDT 24
Peak memory 202040 kb
Host smart-973b8fe5-ff64-4f03-ad82-fcc251c71a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495899869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.2495899869
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.2802663211
Short name T469
Test name
Test status
Simulation time 42904029482 ps
CPU time 38.39 seconds
Started Jun 04 01:54:22 PM PDT 24
Finished Jun 04 01:55:01 PM PDT 24
Peak memory 201620 kb
Host smart-f41613a6-ddb5-4edc-bf5d-d18e4243b566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802663211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.2802663211
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.3861592194
Short name T366
Test name
Test status
Simulation time 3017035757 ps
CPU time 4.11 seconds
Started Jun 04 01:54:20 PM PDT 24
Finished Jun 04 01:54:25 PM PDT 24
Peak memory 201624 kb
Host smart-855df14a-9318-48f4-873f-ab6ae0e3a070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861592194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.3861592194
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.34248439
Short name T756
Test name
Test status
Simulation time 5594130147 ps
CPU time 2.11 seconds
Started Jun 04 01:54:17 PM PDT 24
Finished Jun 04 01:54:20 PM PDT 24
Peak memory 201648 kb
Host smart-a8958f8b-be9e-4ab2-a021-321b69cba6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34248439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.34248439
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.3057062027
Short name T152
Test name
Test status
Simulation time 364698360801 ps
CPU time 801.94 seconds
Started Jun 04 01:54:18 PM PDT 24
Finished Jun 04 02:07:41 PM PDT 24
Peak memory 201844 kb
Host smart-f1120b0f-168a-4c5c-aa1d-e91fae27ac43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057062027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.3057062027
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.1443105872
Short name T688
Test name
Test status
Simulation time 26461980044 ps
CPU time 62.52 seconds
Started Jun 04 01:54:21 PM PDT 24
Finished Jun 04 01:55:24 PM PDT 24
Peak memory 210088 kb
Host smart-9c89981e-521f-4a5e-a220-9ca57c6b3458
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443105872 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.1443105872
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.2765023183
Short name T642
Test name
Test status
Simulation time 378997170 ps
CPU time 1.39 seconds
Started Jun 04 01:54:26 PM PDT 24
Finished Jun 04 01:54:28 PM PDT 24
Peak memory 201492 kb
Host smart-3da9664d-b0e0-4d3a-b30a-d548db4b8813
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765023183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.2765023183
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.1223560896
Short name T236
Test name
Test status
Simulation time 375070673088 ps
CPU time 426.72 seconds
Started Jun 04 01:54:30 PM PDT 24
Finished Jun 04 02:01:37 PM PDT 24
Peak memory 201804 kb
Host smart-0bb7fde7-9c4b-41e1-8a92-61cbc9b0a68e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223560896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.1223560896
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.1095389146
Short name T266
Test name
Test status
Simulation time 166021204989 ps
CPU time 428.32 seconds
Started Jun 04 01:54:28 PM PDT 24
Finished Jun 04 02:01:37 PM PDT 24
Peak memory 201852 kb
Host smart-4cdf9ea9-89ea-415e-8a91-446305b9789d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095389146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.1095389146
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.1466932294
Short name T671
Test name
Test status
Simulation time 169606235842 ps
CPU time 406.53 seconds
Started Jun 04 01:54:19 PM PDT 24
Finished Jun 04 02:01:06 PM PDT 24
Peak memory 201808 kb
Host smart-b699e602-161a-4537-8078-4224e4cba352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466932294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.1466932294
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.2836619499
Short name T110
Test name
Test status
Simulation time 493137052777 ps
CPU time 615.47 seconds
Started Jun 04 01:54:29 PM PDT 24
Finished Jun 04 02:04:45 PM PDT 24
Peak memory 201780 kb
Host smart-c7224ed3-6317-4fda-8208-40f3e25f7f70
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836619499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.2836619499
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.1338735953
Short name T8
Test name
Test status
Simulation time 172262076682 ps
CPU time 94.24 seconds
Started Jun 04 01:54:22 PM PDT 24
Finished Jun 04 01:55:57 PM PDT 24
Peak memory 201612 kb
Host smart-734608cc-2563-4dbd-8202-6c89263488a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338735953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.1338735953
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.2279662228
Short name T381
Test name
Test status
Simulation time 331997108833 ps
CPU time 242.3 seconds
Started Jun 04 01:54:22 PM PDT 24
Finished Jun 04 01:58:25 PM PDT 24
Peak memory 201600 kb
Host smart-26e6868a-ad87-4521-a3c5-747df34a5f95
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279662228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.2279662228
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.716118117
Short name T595
Test name
Test status
Simulation time 604824940348 ps
CPU time 1404.7 seconds
Started Jun 04 01:54:27 PM PDT 24
Finished Jun 04 02:17:53 PM PDT 24
Peak memory 201836 kb
Host smart-f26a31f7-b065-41de-92b1-4cb5a542e2ba
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716118117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
adc_ctrl_filters_wakeup_fixed.716118117
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.2795171908
Short name T685
Test name
Test status
Simulation time 80944684575 ps
CPU time 279.88 seconds
Started Jun 04 01:54:30 PM PDT 24
Finished Jun 04 01:59:10 PM PDT 24
Peak memory 202172 kb
Host smart-9aee6692-b751-414c-8dd4-5c08e10f79a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795171908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.2795171908
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.949712015
Short name T432
Test name
Test status
Simulation time 37260254153 ps
CPU time 23.18 seconds
Started Jun 04 01:54:27 PM PDT 24
Finished Jun 04 01:54:51 PM PDT 24
Peak memory 201620 kb
Host smart-a9c00ed5-44b2-4344-98dc-f13f4ca31a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949712015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.949712015
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.2688359477
Short name T446
Test name
Test status
Simulation time 3807308815 ps
CPU time 4.76 seconds
Started Jun 04 01:54:29 PM PDT 24
Finished Jun 04 01:54:35 PM PDT 24
Peak memory 201556 kb
Host smart-3ae3a39b-89c0-4b0f-bcdf-dfb35fcaa0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688359477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.2688359477
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.1194970203
Short name T547
Test name
Test status
Simulation time 5531630392 ps
CPU time 6.91 seconds
Started Jun 04 01:54:24 PM PDT 24
Finished Jun 04 01:54:31 PM PDT 24
Peak memory 201636 kb
Host smart-fe666f3b-4276-44c9-ac90-eada9f0b6000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194970203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.1194970203
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.15640319
Short name T305
Test name
Test status
Simulation time 172703997034 ps
CPU time 96.03 seconds
Started Jun 04 01:54:30 PM PDT 24
Finished Jun 04 01:56:07 PM PDT 24
Peak memory 201724 kb
Host smart-a32a57ed-3c7f-466e-9bd1-57b03e86c017
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15640319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all.15640319
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.2637888162
Short name T240
Test name
Test status
Simulation time 571651654177 ps
CPU time 530.83 seconds
Started Jun 04 01:54:32 PM PDT 24
Finished Jun 04 02:03:23 PM PDT 24
Peak memory 210332 kb
Host smart-10b38f68-74a7-4555-a50d-b73c95301960
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637888162 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.2637888162
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.3112831052
Short name T362
Test name
Test status
Simulation time 462887992 ps
CPU time 1.67 seconds
Started Jun 04 01:54:35 PM PDT 24
Finished Jun 04 01:54:37 PM PDT 24
Peak memory 201496 kb
Host smart-886db81a-c1e5-4cde-ae77-e9562a80c462
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112831052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.3112831052
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.835282317
Short name T738
Test name
Test status
Simulation time 543574228031 ps
CPU time 320.19 seconds
Started Jun 04 01:54:34 PM PDT 24
Finished Jun 04 01:59:55 PM PDT 24
Peak memory 201820 kb
Host smart-ac22d26e-bb43-4072-97e1-0365e312ca94
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835282317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gati
ng.835282317
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.2220426737
Short name T345
Test name
Test status
Simulation time 569420295169 ps
CPU time 1145.08 seconds
Started Jun 04 01:54:34 PM PDT 24
Finished Jun 04 02:13:40 PM PDT 24
Peak memory 201812 kb
Host smart-7d3e33aa-3436-4bd9-8f99-fe08b0de2131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220426737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.2220426737
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.1285210225
Short name T509
Test name
Test status
Simulation time 162885750148 ps
CPU time 361.39 seconds
Started Jun 04 01:54:29 PM PDT 24
Finished Jun 04 02:00:31 PM PDT 24
Peak memory 201776 kb
Host smart-d0982936-3397-4832-b4b7-2ea0f8e60115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285210225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.1285210225
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.2913037419
Short name T670
Test name
Test status
Simulation time 162715422149 ps
CPU time 95.52 seconds
Started Jun 04 01:54:29 PM PDT 24
Finished Jun 04 01:56:06 PM PDT 24
Peak memory 201752 kb
Host smart-3d8e8f28-fe92-4216-8c37-4b5822d4c8e5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913037419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.2913037419
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.1031256657
Short name T326
Test name
Test status
Simulation time 161795765895 ps
CPU time 98.43 seconds
Started Jun 04 01:54:27 PM PDT 24
Finished Jun 04 01:56:06 PM PDT 24
Peak memory 201724 kb
Host smart-b188c270-914c-4323-abcc-7c17cdb426c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031256657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.1031256657
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.453187824
Short name T742
Test name
Test status
Simulation time 495487515310 ps
CPU time 369.38 seconds
Started Jun 04 01:54:29 PM PDT 24
Finished Jun 04 02:00:39 PM PDT 24
Peak memory 201816 kb
Host smart-c362e548-12de-4871-b0ed-ccc7089437ac
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=453187824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fixe
d.453187824
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.3200291816
Short name T247
Test name
Test status
Simulation time 336641075680 ps
CPU time 745.95 seconds
Started Jun 04 01:54:27 PM PDT 24
Finished Jun 04 02:06:54 PM PDT 24
Peak memory 201892 kb
Host smart-3b517992-958a-47aa-85e5-58c176b1d9c1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200291816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.3200291816
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.3246051206
Short name T13
Test name
Test status
Simulation time 201859123379 ps
CPU time 234.14 seconds
Started Jun 04 01:54:30 PM PDT 24
Finished Jun 04 01:58:25 PM PDT 24
Peak memory 201888 kb
Host smart-bf6b69d0-8e35-44e1-9767-d4262c89c1dc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246051206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.3246051206
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.2277193010
Short name T219
Test name
Test status
Simulation time 73352269238 ps
CPU time 275.24 seconds
Started Jun 04 01:54:35 PM PDT 24
Finished Jun 04 01:59:11 PM PDT 24
Peak memory 202088 kb
Host smart-9b265344-d400-4c70-8a73-4c0e5a8553e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277193010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.2277193010
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.324743868
Short name T422
Test name
Test status
Simulation time 29972240835 ps
CPU time 66.45 seconds
Started Jun 04 01:54:34 PM PDT 24
Finished Jun 04 01:55:41 PM PDT 24
Peak memory 201620 kb
Host smart-308c97e1-ac00-45f5-9bc2-447d3daa5ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324743868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.324743868
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.2566553816
Short name T571
Test name
Test status
Simulation time 5512005912 ps
CPU time 14.07 seconds
Started Jun 04 01:54:34 PM PDT 24
Finished Jun 04 01:54:49 PM PDT 24
Peak memory 201628 kb
Host smart-6727646e-b3ff-49bd-9f90-d0b60e59bdc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566553816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.2566553816
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.2975079821
Short name T568
Test name
Test status
Simulation time 6028016767 ps
CPU time 4.18 seconds
Started Jun 04 01:54:32 PM PDT 24
Finished Jun 04 01:54:36 PM PDT 24
Peak memory 201560 kb
Host smart-a0d5678e-e0c3-4cd6-a683-9435b7b27464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975079821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.2975079821
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.4001949170
Short name T145
Test name
Test status
Simulation time 195336864072 ps
CPU time 444.06 seconds
Started Jun 04 01:54:34 PM PDT 24
Finished Jun 04 02:01:59 PM PDT 24
Peak memory 201832 kb
Host smart-8b6c62a1-d0ff-4ae4-8a2b-ce59bec530a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001949170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.4001949170
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.858326396
Short name T243
Test name
Test status
Simulation time 371853383706 ps
CPU time 591.14 seconds
Started Jun 04 01:54:36 PM PDT 24
Finished Jun 04 02:04:28 PM PDT 24
Peak memory 210428 kb
Host smart-4f78a0a4-6a7b-4bc5-8065-581cf081f562
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858326396 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.858326396
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.4279616943
Short name T514
Test name
Test status
Simulation time 357852917 ps
CPU time 0.98 seconds
Started Jun 04 01:54:49 PM PDT 24
Finished Jun 04 01:54:51 PM PDT 24
Peak memory 201440 kb
Host smart-cf234b87-8e57-499c-a210-54a94f1c9db2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279616943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.4279616943
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.3295670752
Short name T278
Test name
Test status
Simulation time 340861993581 ps
CPU time 118.89 seconds
Started Jun 04 01:54:40 PM PDT 24
Finished Jun 04 01:56:40 PM PDT 24
Peak memory 201720 kb
Host smart-2437aa9e-fc84-48d9-bae2-fe52fb595f80
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295670752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.3295670752
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.2460023074
Short name T336
Test name
Test status
Simulation time 329303792446 ps
CPU time 200.89 seconds
Started Jun 04 01:54:40 PM PDT 24
Finished Jun 04 01:58:02 PM PDT 24
Peak memory 201872 kb
Host smart-de680337-9600-4cf6-9723-6cd579927aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460023074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.2460023074
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.3328058018
Short name T338
Test name
Test status
Simulation time 164530821536 ps
CPU time 378.53 seconds
Started Jun 04 01:54:43 PM PDT 24
Finished Jun 04 02:01:02 PM PDT 24
Peak memory 201740 kb
Host smart-203e318c-7a8f-4d95-9187-e303dadd78f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328058018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.3328058018
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.1766586650
Short name T682
Test name
Test status
Simulation time 323735602138 ps
CPU time 699.55 seconds
Started Jun 04 01:54:44 PM PDT 24
Finished Jun 04 02:06:25 PM PDT 24
Peak memory 201776 kb
Host smart-03b55267-0898-4007-b42d-bd2e8bca8782
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766586650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.1766586650
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.2647957721
Short name T318
Test name
Test status
Simulation time 325780258415 ps
CPU time 818.12 seconds
Started Jun 04 01:54:35 PM PDT 24
Finished Jun 04 02:08:14 PM PDT 24
Peak memory 201848 kb
Host smart-196c8281-ce51-4536-a419-60c04405b12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647957721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.2647957721
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.3835773342
Short name T579
Test name
Test status
Simulation time 162695813465 ps
CPU time 90.1 seconds
Started Jun 04 01:54:40 PM PDT 24
Finished Jun 04 01:56:11 PM PDT 24
Peak memory 201660 kb
Host smart-f5a28327-fe46-4e06-94f6-0239c05182c4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835773342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.3835773342
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.3824575643
Short name T162
Test name
Test status
Simulation time 171536983984 ps
CPU time 410.45 seconds
Started Jun 04 01:54:40 PM PDT 24
Finished Jun 04 02:01:31 PM PDT 24
Peak memory 201864 kb
Host smart-591744b5-9b02-4127-83a3-bc8f09723d98
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824575643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.3824575643
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.4207971863
Short name T788
Test name
Test status
Simulation time 200861095413 ps
CPU time 102.74 seconds
Started Jun 04 01:54:44 PM PDT 24
Finished Jun 04 01:56:28 PM PDT 24
Peak memory 201816 kb
Host smart-e48557bd-cbc5-4284-84ab-0f314e833925
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207971863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.4207971863
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.1144512608
Short name T764
Test name
Test status
Simulation time 101089162987 ps
CPU time 496.05 seconds
Started Jun 04 01:54:42 PM PDT 24
Finished Jun 04 02:02:59 PM PDT 24
Peak memory 202080 kb
Host smart-65bd8a15-2df7-45a5-941b-03c58a6fe8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144512608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.1144512608
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.2848852444
Short name T404
Test name
Test status
Simulation time 26071533792 ps
CPU time 29.89 seconds
Started Jun 04 01:54:44 PM PDT 24
Finished Jun 04 01:55:15 PM PDT 24
Peak memory 201592 kb
Host smart-cdf6c20b-7a71-4045-8f32-fa1522a0e9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848852444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.2848852444
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.2778482791
Short name T361
Test name
Test status
Simulation time 3694610192 ps
CPU time 2.86 seconds
Started Jun 04 01:54:42 PM PDT 24
Finished Jun 04 01:54:46 PM PDT 24
Peak memory 201600 kb
Host smart-9d56562d-46c4-4cdb-93c9-44f9ac316d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778482791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.2778482791
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.1825860051
Short name T585
Test name
Test status
Simulation time 5559405356 ps
CPU time 3.95 seconds
Started Jun 04 01:54:33 PM PDT 24
Finished Jun 04 01:54:38 PM PDT 24
Peak memory 201576 kb
Host smart-ca642984-6d6f-48c7-96f1-b477f481737e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825860051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.1825860051
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.738399709
Short name T321
Test name
Test status
Simulation time 858985812560 ps
CPU time 1082.4 seconds
Started Jun 04 01:54:49 PM PDT 24
Finished Jun 04 02:12:52 PM PDT 24
Peak memory 201816 kb
Host smart-9580bd77-bca3-40ab-8872-6a0f54425e6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738399709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all.
738399709
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.2369691302
Short name T99
Test name
Test status
Simulation time 34038995414 ps
CPU time 80.54 seconds
Started Jun 04 01:54:42 PM PDT 24
Finished Jun 04 01:56:03 PM PDT 24
Peak memory 210568 kb
Host smart-f8b4a0e2-6241-4322-b89f-8d590c767d77
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369691302 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.2369691302
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.276225403
Short name T380
Test name
Test status
Simulation time 394746206 ps
CPU time 0.79 seconds
Started Jun 04 01:54:52 PM PDT 24
Finished Jun 04 01:54:54 PM PDT 24
Peak memory 201500 kb
Host smart-6b830a2d-7310-453e-9b9d-6d935c939ecc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276225403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.276225403
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.921463040
Short name T261
Test name
Test status
Simulation time 324109794808 ps
CPU time 360.52 seconds
Started Jun 04 01:54:48 PM PDT 24
Finished Jun 04 02:00:49 PM PDT 24
Peak memory 201780 kb
Host smart-50ec97b5-7505-4581-83bb-f60e397a8950
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921463040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gati
ng.921463040
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.11171139
Short name T341
Test name
Test status
Simulation time 329085679199 ps
CPU time 825.31 seconds
Started Jun 04 01:54:55 PM PDT 24
Finished Jun 04 02:08:41 PM PDT 24
Peak memory 201760 kb
Host smart-a07cc56b-1acd-4c65-92e5-d52cbe763204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11171139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.11171139
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.3431774051
Short name T331
Test name
Test status
Simulation time 491248401080 ps
CPU time 1092.84 seconds
Started Jun 04 01:54:50 PM PDT 24
Finished Jun 04 02:13:04 PM PDT 24
Peak memory 201820 kb
Host smart-05ff7894-ffa0-4de4-8673-8893eecc38ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431774051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.3431774051
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.3913440257
Short name T556
Test name
Test status
Simulation time 165046821364 ps
CPU time 378.75 seconds
Started Jun 04 01:54:49 PM PDT 24
Finished Jun 04 02:01:08 PM PDT 24
Peak memory 201760 kb
Host smart-0ac6d65b-a1cf-4cba-b1bb-9eafa8b5a1c0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913440257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.3913440257
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.3552903250
Short name T198
Test name
Test status
Simulation time 497810675480 ps
CPU time 267.52 seconds
Started Jun 04 01:54:48 PM PDT 24
Finished Jun 04 01:59:17 PM PDT 24
Peak memory 201848 kb
Host smart-6ce4e7d3-eda5-4a9c-8d21-d2037d283dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552903250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.3552903250
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.3958916887
Short name T387
Test name
Test status
Simulation time 497607582053 ps
CPU time 287.75 seconds
Started Jun 04 01:54:48 PM PDT 24
Finished Jun 04 01:59:36 PM PDT 24
Peak memory 201716 kb
Host smart-6ca43ac3-c4d5-4312-83a9-76d758fb306a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958916887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.3958916887
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.3379398195
Short name T269
Test name
Test status
Simulation time 176158274390 ps
CPU time 112.04 seconds
Started Jun 04 01:54:50 PM PDT 24
Finished Jun 04 01:56:43 PM PDT 24
Peak memory 201984 kb
Host smart-5e540365-5231-4964-a2fb-83881c590e2e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379398195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.3379398195
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.1731517243
Short name T421
Test name
Test status
Simulation time 200330084132 ps
CPU time 472.75 seconds
Started Jun 04 01:54:48 PM PDT 24
Finished Jun 04 02:02:42 PM PDT 24
Peak memory 201752 kb
Host smart-f128c52b-a8bc-48b7-9828-67ba76e33357
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731517243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.1731517243
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.1266091513
Short name T759
Test name
Test status
Simulation time 94122606838 ps
CPU time 307.72 seconds
Started Jun 04 01:54:53 PM PDT 24
Finished Jun 04 02:00:01 PM PDT 24
Peak memory 202016 kb
Host smart-c660088b-2587-443f-bf8a-48e8ec3158f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266091513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.1266091513
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.2189619187
Short name T655
Test name
Test status
Simulation time 25546778367 ps
CPU time 15.3 seconds
Started Jun 04 01:54:54 PM PDT 24
Finished Jun 04 01:55:10 PM PDT 24
Peak memory 201532 kb
Host smart-88c14306-fa38-44a3-8b44-b86e4d9d852a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189619187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.2189619187
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.1319941652
Short name T410
Test name
Test status
Simulation time 4796510318 ps
CPU time 12.46 seconds
Started Jun 04 01:54:55 PM PDT 24
Finished Jun 04 01:55:08 PM PDT 24
Peak memory 201632 kb
Host smart-1b74017f-b632-4045-901c-fdeeaa4aa964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319941652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.1319941652
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.2709645666
Short name T26
Test name
Test status
Simulation time 6051496027 ps
CPU time 15.06 seconds
Started Jun 04 01:54:49 PM PDT 24
Finished Jun 04 01:55:05 PM PDT 24
Peak memory 201636 kb
Host smart-fe5c06a6-2ec6-4e4a-ab78-b1fd41193b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709645666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.2709645666
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.1713500387
Short name T664
Test name
Test status
Simulation time 20434037014 ps
CPU time 67.78 seconds
Started Jun 04 01:54:56 PM PDT 24
Finished Jun 04 01:56:04 PM PDT 24
Peak memory 210436 kb
Host smart-941a474f-8b84-4b6d-8500-7e606bc0681c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713500387 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.1713500387
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.163953912
Short name T72
Test name
Test status
Simulation time 329462618 ps
CPU time 0.81 seconds
Started Jun 04 01:55:11 PM PDT 24
Finished Jun 04 01:55:12 PM PDT 24
Peak memory 201496 kb
Host smart-9bb2b3a1-b95f-40bb-8784-bf007eec736b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163953912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.163953912
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.1572391560
Short name T144
Test name
Test status
Simulation time 348508720849 ps
CPU time 464.3 seconds
Started Jun 04 01:55:03 PM PDT 24
Finished Jun 04 02:02:49 PM PDT 24
Peak memory 201868 kb
Host smart-68b36e65-5978-4333-a321-6c28ae4710c2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572391560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.1572391560
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.2092048754
Short name T239
Test name
Test status
Simulation time 184171627269 ps
CPU time 116.67 seconds
Started Jun 04 01:55:03 PM PDT 24
Finished Jun 04 01:57:00 PM PDT 24
Peak memory 201812 kb
Host smart-373de7be-a777-4b68-bbcc-e4264fdc537e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092048754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.2092048754
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.198778097
Short name T234
Test name
Test status
Simulation time 159522850393 ps
CPU time 174.54 seconds
Started Jun 04 01:55:04 PM PDT 24
Finished Jun 04 01:58:00 PM PDT 24
Peak memory 201816 kb
Host smart-ea09fb45-ed3e-4188-a1fa-556a74acfc46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198778097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.198778097
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.3946648701
Short name T31
Test name
Test status
Simulation time 494957745792 ps
CPU time 104.66 seconds
Started Jun 04 01:55:04 PM PDT 24
Finished Jun 04 01:56:49 PM PDT 24
Peak memory 201800 kb
Host smart-449198c3-768a-4a1a-afd4-3588c3fb3814
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946648701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.3946648701
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.1090569780
Short name T257
Test name
Test status
Simulation time 489234879981 ps
CPU time 520.18 seconds
Started Jun 04 01:55:03 PM PDT 24
Finished Jun 04 02:03:44 PM PDT 24
Peak memory 201860 kb
Host smart-68ad15de-b631-43e3-97d0-0a5da40cb7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090569780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.1090569780
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.854610547
Short name T385
Test name
Test status
Simulation time 327321140143 ps
CPU time 188.28 seconds
Started Jun 04 01:55:06 PM PDT 24
Finished Jun 04 01:58:14 PM PDT 24
Peak memory 201764 kb
Host smart-ba205622-9e2d-44d4-89c9-f7dd9bf5886e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=854610547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fixe
d.854610547
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.1415090094
Short name T90
Test name
Test status
Simulation time 203095950341 ps
CPU time 179.25 seconds
Started Jun 04 01:55:03 PM PDT 24
Finished Jun 04 01:58:03 PM PDT 24
Peak memory 201808 kb
Host smart-1abd6e92-d277-4395-9c96-bd6e01d899b9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415090094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.1415090094
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.3673648255
Short name T95
Test name
Test status
Simulation time 82377748524 ps
CPU time 338.16 seconds
Started Jun 04 01:55:05 PM PDT 24
Finished Jun 04 02:00:44 PM PDT 24
Peak memory 202112 kb
Host smart-0066dfbb-db11-4989-9e37-486dc98c3280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673648255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.3673648255
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.1362856977
Short name T430
Test name
Test status
Simulation time 26545466277 ps
CPU time 35.13 seconds
Started Jun 04 01:55:06 PM PDT 24
Finished Jun 04 01:55:41 PM PDT 24
Peak memory 201568 kb
Host smart-f6f22594-65dd-42f1-9d13-e785f3988aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362856977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.1362856977
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.985521568
Short name T785
Test name
Test status
Simulation time 3507468906 ps
CPU time 2.83 seconds
Started Jun 04 01:55:03 PM PDT 24
Finished Jun 04 01:55:07 PM PDT 24
Peak memory 201592 kb
Host smart-c36ccaf9-e033-4b0d-a4cb-5e5346a1e217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985521568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.985521568
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.1950366393
Short name T480
Test name
Test status
Simulation time 5575715851 ps
CPU time 13.86 seconds
Started Jun 04 01:55:04 PM PDT 24
Finished Jun 04 01:55:18 PM PDT 24
Peak memory 201676 kb
Host smart-8c60013c-349d-4921-abc9-73c6fbe2e3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950366393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.1950366393
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.3987998388
Short name T667
Test name
Test status
Simulation time 291186636498 ps
CPU time 1016.57 seconds
Started Jun 04 01:55:08 PM PDT 24
Finished Jun 04 02:12:05 PM PDT 24
Peak memory 202192 kb
Host smart-c48ac2e0-d1b4-45b2-b524-b0e6deeccc2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987998388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.3987998388
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.333964082
Short name T567
Test name
Test status
Simulation time 154770975939 ps
CPU time 167.5 seconds
Started Jun 04 01:55:11 PM PDT 24
Finished Jun 04 01:58:00 PM PDT 24
Peak memory 201912 kb
Host smart-b963d301-b467-4bc7-9cd0-e20e93a76b6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333964082 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.333964082
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.1241849665
Short name T479
Test name
Test status
Simulation time 396793067 ps
CPU time 0.79 seconds
Started Jun 04 01:55:20 PM PDT 24
Finished Jun 04 01:55:22 PM PDT 24
Peak memory 201492 kb
Host smart-d6dc8463-0376-4589-aa58-47a04ec110db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241849665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.1241849665
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.1519470171
Short name T259
Test name
Test status
Simulation time 507103004142 ps
CPU time 375.65 seconds
Started Jun 04 01:55:12 PM PDT 24
Finished Jun 04 02:01:29 PM PDT 24
Peak memory 201864 kb
Host smart-385cccfb-2b29-4913-96df-29b793ef2cd7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519470171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.1519470171
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.1330329587
Short name T165
Test name
Test status
Simulation time 177343389641 ps
CPU time 439.18 seconds
Started Jun 04 01:55:08 PM PDT 24
Finished Jun 04 02:02:27 PM PDT 24
Peak memory 201860 kb
Host smart-791efb55-b585-4b10-b388-c21d7ba7f4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330329587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.1330329587
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.705322370
Short name T773
Test name
Test status
Simulation time 162362938310 ps
CPU time 350.36 seconds
Started Jun 04 01:55:09 PM PDT 24
Finished Jun 04 02:01:00 PM PDT 24
Peak memory 201888 kb
Host smart-a1c69ba7-69ab-4968-aebb-231dd8590d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705322370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.705322370
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.2007738536
Short name T535
Test name
Test status
Simulation time 325985640455 ps
CPU time 748.93 seconds
Started Jun 04 01:55:10 PM PDT 24
Finished Jun 04 02:07:40 PM PDT 24
Peak memory 201800 kb
Host smart-8533a958-bce3-4d20-a7ee-12b0bd9bd730
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007738536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.2007738536
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.2793132113
Short name T87
Test name
Test status
Simulation time 489758543675 ps
CPU time 273.24 seconds
Started Jun 04 01:55:10 PM PDT 24
Finished Jun 04 01:59:44 PM PDT 24
Peak memory 201828 kb
Host smart-93238856-954d-41a4-a141-81d4b50bb8d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793132113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.2793132113
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.2265510580
Short name T627
Test name
Test status
Simulation time 155355429281 ps
CPU time 40.29 seconds
Started Jun 04 01:55:09 PM PDT 24
Finished Jun 04 01:55:50 PM PDT 24
Peak memory 201772 kb
Host smart-a67267a7-9ca9-48a4-b5e2-fbd786edc558
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265510580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.2265510580
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.3755521319
Short name T256
Test name
Test status
Simulation time 180052747309 ps
CPU time 305.45 seconds
Started Jun 04 01:55:09 PM PDT 24
Finished Jun 04 02:00:15 PM PDT 24
Peak memory 201804 kb
Host smart-23c73f8e-1574-4f5b-9bdb-1b5c962807eb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755521319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.3755521319
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.2311968014
Short name T587
Test name
Test status
Simulation time 597273661658 ps
CPU time 680.83 seconds
Started Jun 04 01:55:09 PM PDT 24
Finished Jun 04 02:06:30 PM PDT 24
Peak memory 201680 kb
Host smart-c34a1e61-75ad-4ef6-a15a-5e7c25edb97b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311968014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.2311968014
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.2649627751
Short name T451
Test name
Test status
Simulation time 120784937003 ps
CPU time 525.19 seconds
Started Jun 04 01:55:15 PM PDT 24
Finished Jun 04 02:04:01 PM PDT 24
Peak memory 202092 kb
Host smart-f887e2bf-76b8-4be7-9249-38d9d26aac1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649627751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.2649627751
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.3807851828
Short name T488
Test name
Test status
Simulation time 42869330446 ps
CPU time 23.8 seconds
Started Jun 04 01:55:16 PM PDT 24
Finished Jun 04 01:55:41 PM PDT 24
Peak memory 201576 kb
Host smart-99dbad41-3962-4555-b857-44bffb44beb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807851828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.3807851828
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.1090033760
Short name T390
Test name
Test status
Simulation time 3328074403 ps
CPU time 2.74 seconds
Started Jun 04 01:55:15 PM PDT 24
Finished Jun 04 01:55:19 PM PDT 24
Peak memory 201556 kb
Host smart-f9ae79ac-5627-421b-8c11-fb7768b26754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090033760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.1090033760
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.1539237694
Short name T83
Test name
Test status
Simulation time 5632329595 ps
CPU time 7.52 seconds
Started Jun 04 01:55:09 PM PDT 24
Finished Jun 04 01:55:17 PM PDT 24
Peak memory 201608 kb
Host smart-3b89b788-5925-4165-a747-07b2422749a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539237694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.1539237694
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.687144777
Short name T739
Test name
Test status
Simulation time 517632085812 ps
CPU time 1052.45 seconds
Started Jun 04 01:55:17 PM PDT 24
Finished Jun 04 02:12:50 PM PDT 24
Peak memory 201724 kb
Host smart-69c6877b-498c-4591-b923-b3a6c6bc0c75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687144777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all.
687144777
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.2404083075
Short name T260
Test name
Test status
Simulation time 152265046849 ps
CPU time 242.49 seconds
Started Jun 04 01:55:20 PM PDT 24
Finished Jun 04 01:59:24 PM PDT 24
Peak memory 217924 kb
Host smart-2f027457-5e67-4e4d-8e85-4440582969fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404083075 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.2404083075
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.3018752305
Short name T426
Test name
Test status
Simulation time 391745214 ps
CPU time 1.19 seconds
Started Jun 04 01:52:35 PM PDT 24
Finished Jun 04 01:52:38 PM PDT 24
Peak memory 201444 kb
Host smart-20b295f1-e5f8-4f81-9c33-a0c6634cd005
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018752305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.3018752305
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.2343531814
Short name T672
Test name
Test status
Simulation time 320872730564 ps
CPU time 377.37 seconds
Started Jun 04 01:52:39 PM PDT 24
Finished Jun 04 01:58:57 PM PDT 24
Peak memory 201804 kb
Host smart-55ae239f-62e3-486b-9091-480ed26abf53
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343531814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.2343531814
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.1278202962
Short name T736
Test name
Test status
Simulation time 163440543539 ps
CPU time 205.56 seconds
Started Jun 04 01:52:52 PM PDT 24
Finished Jun 04 01:56:19 PM PDT 24
Peak memory 201808 kb
Host smart-3818ec97-1e58-4d42-83ab-4034a0933807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278202962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.1278202962
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.1708902825
Short name T379
Test name
Test status
Simulation time 327390438589 ps
CPU time 746.24 seconds
Started Jun 04 01:52:38 PM PDT 24
Finished Jun 04 02:05:10 PM PDT 24
Peak memory 201728 kb
Host smart-7ec670dd-d8c8-46b4-828c-a4da01ecdae8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708902825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.1708902825
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.3396531889
Short name T283
Test name
Test status
Simulation time 323083310738 ps
CPU time 772.94 seconds
Started Jun 04 01:53:04 PM PDT 24
Finished Jun 04 02:05:58 PM PDT 24
Peak memory 201912 kb
Host smart-e99e9681-39ec-49cd-982b-5ca09fc8582b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396531889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.3396531889
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.1948995922
Short name T599
Test name
Test status
Simulation time 328613900241 ps
CPU time 100.85 seconds
Started Jun 04 01:52:43 PM PDT 24
Finished Jun 04 01:54:24 PM PDT 24
Peak memory 201300 kb
Host smart-2475e898-7e1b-4968-a1f4-d664ecfd3f0f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948995922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.1948995922
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.276548001
Short name T745
Test name
Test status
Simulation time 194172808159 ps
CPU time 482.64 seconds
Started Jun 04 01:52:41 PM PDT 24
Finished Jun 04 02:00:44 PM PDT 24
Peak memory 201820 kb
Host smart-b2e27c99-8368-4f54-acce-5937583590db
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276548001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.a
dc_ctrl_filters_wakeup_fixed.276548001
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.3700730760
Short name T576
Test name
Test status
Simulation time 90933457665 ps
CPU time 337.91 seconds
Started Jun 04 01:52:40 PM PDT 24
Finished Jun 04 01:58:19 PM PDT 24
Peak memory 202088 kb
Host smart-427f6f6c-2d1d-4df8-a82d-af0a88b237e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700730760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.3700730760
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.2942378384
Short name T612
Test name
Test status
Simulation time 41730150640 ps
CPU time 24.95 seconds
Started Jun 04 01:52:38 PM PDT 24
Finished Jun 04 01:53:03 PM PDT 24
Peak memory 201636 kb
Host smart-e37d71b0-52ac-44bc-9dfe-215ebc70e6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942378384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.2942378384
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.1844567707
Short name T111
Test name
Test status
Simulation time 4298393487 ps
CPU time 6.05 seconds
Started Jun 04 01:52:46 PM PDT 24
Finished Jun 04 01:52:53 PM PDT 24
Peak memory 201596 kb
Host smart-5e840905-c7c5-4112-a720-59bfcffe658f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844567707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.1844567707
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.1935007483
Short name T79
Test name
Test status
Simulation time 7696972057 ps
CPU time 9.21 seconds
Started Jun 04 01:52:50 PM PDT 24
Finished Jun 04 01:53:01 PM PDT 24
Peak memory 218416 kb
Host smart-24348441-80ac-442f-969a-68af57200abc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935007483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.1935007483
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.2061858501
Short name T772
Test name
Test status
Simulation time 5649826157 ps
CPU time 4.54 seconds
Started Jun 04 01:52:43 PM PDT 24
Finished Jun 04 01:52:49 PM PDT 24
Peak memory 201636 kb
Host smart-f16c8e87-107e-42f7-a9d2-abdedf6fb756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061858501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.2061858501
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.2721464229
Short name T510
Test name
Test status
Simulation time 365936728427 ps
CPU time 804.74 seconds
Started Jun 04 01:52:41 PM PDT 24
Finished Jun 04 02:06:07 PM PDT 24
Peak memory 201868 kb
Host smart-c6f8d98e-807d-45b6-aadb-ac4875b2a296
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721464229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
2721464229
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.4245090951
Short name T300
Test name
Test status
Simulation time 85132254689 ps
CPU time 264.68 seconds
Started Jun 04 01:52:41 PM PDT 24
Finished Jun 04 01:57:07 PM PDT 24
Peak memory 210404 kb
Host smart-51417505-5034-496f-a8db-7acefa86789b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245090951 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.4245090951
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.153130674
Short name T704
Test name
Test status
Simulation time 326580150 ps
CPU time 1.41 seconds
Started Jun 04 01:55:29 PM PDT 24
Finished Jun 04 01:55:31 PM PDT 24
Peak memory 201516 kb
Host smart-5cca944a-a1b4-4f8c-a2b2-47b02fa01b5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153130674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.153130674
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.492480076
Short name T765
Test name
Test status
Simulation time 368997966705 ps
CPU time 216.39 seconds
Started Jun 04 01:55:23 PM PDT 24
Finished Jun 04 01:59:00 PM PDT 24
Peak memory 201804 kb
Host smart-f773e057-c760-47a8-ab7f-27384bb96b11
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492480076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gati
ng.492480076
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.3421902487
Short name T692
Test name
Test status
Simulation time 188033477740 ps
CPU time 105.9 seconds
Started Jun 04 01:55:22 PM PDT 24
Finished Jun 04 01:57:09 PM PDT 24
Peak memory 201780 kb
Host smart-493dd40a-3af9-428b-9d8c-4a71c379a46b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421902487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.3421902487
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.1611510724
Short name T717
Test name
Test status
Simulation time 485128756527 ps
CPU time 878.69 seconds
Started Jun 04 01:55:22 PM PDT 24
Finished Jun 04 02:10:02 PM PDT 24
Peak memory 201764 kb
Host smart-507f2d08-cb0b-46ad-88cf-f93986340d89
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611510724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.1611510724
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.1334869195
Short name T737
Test name
Test status
Simulation time 325662108245 ps
CPU time 695.14 seconds
Started Jun 04 01:55:15 PM PDT 24
Finished Jun 04 02:06:50 PM PDT 24
Peak memory 201764 kb
Host smart-8b867f6d-506c-4621-aa27-9bd8152ca3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334869195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.1334869195
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.4025673575
Short name T465
Test name
Test status
Simulation time 492932059444 ps
CPU time 1123.96 seconds
Started Jun 04 01:55:17 PM PDT 24
Finished Jun 04 02:14:02 PM PDT 24
Peak memory 201784 kb
Host smart-3263a82c-79c7-43d8-b272-0cfc4a67c614
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025673575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.4025673575
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.2100510501
Short name T319
Test name
Test status
Simulation time 366124687426 ps
CPU time 112.3 seconds
Started Jun 04 01:55:24 PM PDT 24
Finished Jun 04 01:57:17 PM PDT 24
Peak memory 201840 kb
Host smart-0a790571-81ac-4ca7-98c6-58c466a56601
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100510501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.2100510501
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.1670492281
Short name T395
Test name
Test status
Simulation time 201769875046 ps
CPU time 80.06 seconds
Started Jun 04 01:55:23 PM PDT 24
Finished Jun 04 01:56:44 PM PDT 24
Peak memory 201772 kb
Host smart-248861d5-1727-4191-9ffc-fba274d45a01
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670492281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.1670492281
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.3334479786
Short name T85
Test name
Test status
Simulation time 154049426162 ps
CPU time 789.17 seconds
Started Jun 04 01:55:31 PM PDT 24
Finished Jun 04 02:08:41 PM PDT 24
Peak memory 202176 kb
Host smart-bf13d599-dd53-4aab-aaa7-a5a8c531f7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334479786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.3334479786
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.2054510721
Short name T359
Test name
Test status
Simulation time 44026692584 ps
CPU time 25.63 seconds
Started Jun 04 01:55:31 PM PDT 24
Finished Jun 04 01:55:57 PM PDT 24
Peak memory 201536 kb
Host smart-a7506bd1-5c09-4c38-8b71-79ceef8ab282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054510721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.2054510721
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.116694946
Short name T473
Test name
Test status
Simulation time 3229559417 ps
CPU time 4.17 seconds
Started Jun 04 01:55:24 PM PDT 24
Finished Jun 04 01:55:29 PM PDT 24
Peak memory 201584 kb
Host smart-685c8492-8ca1-4bc3-913f-b40a6d7c98bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116694946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.116694946
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.3163087387
Short name T769
Test name
Test status
Simulation time 5787109822 ps
CPU time 4.37 seconds
Started Jun 04 01:55:16 PM PDT 24
Finished Jun 04 01:55:21 PM PDT 24
Peak memory 201632 kb
Host smart-d3d9a2f6-a9f8-4f27-9fe3-39721022b8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163087387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.3163087387
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.2212239478
Short name T344
Test name
Test status
Simulation time 588009777748 ps
CPU time 571.64 seconds
Started Jun 04 01:55:30 PM PDT 24
Finished Jun 04 02:05:02 PM PDT 24
Peak memory 210376 kb
Host smart-0dcf7c2d-fc5f-4be4-9553-977645d6167f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212239478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.2212239478
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.4164785061
Short name T18
Test name
Test status
Simulation time 49201548267 ps
CPU time 121.36 seconds
Started Jun 04 01:55:29 PM PDT 24
Finished Jun 04 01:57:31 PM PDT 24
Peak memory 210472 kb
Host smart-98307d8c-1f76-423b-8e27-1166be59a857
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164785061 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.4164785061
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.3591863495
Short name T677
Test name
Test status
Simulation time 521420964 ps
CPU time 1.8 seconds
Started Jun 04 01:55:37 PM PDT 24
Finished Jun 04 01:55:40 PM PDT 24
Peak memory 201492 kb
Host smart-b3fb6b38-7a0b-4ea2-bc61-7b822fb15704
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591863495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.3591863495
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.3330693664
Short name T491
Test name
Test status
Simulation time 185153322898 ps
CPU time 445.46 seconds
Started Jun 04 01:55:30 PM PDT 24
Finished Jun 04 02:02:57 PM PDT 24
Peak memory 201804 kb
Host smart-e12251df-38a0-4e26-9e8d-6c090ef2202c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330693664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.3330693664
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.3757017727
Short name T258
Test name
Test status
Simulation time 161747514631 ps
CPU time 49.49 seconds
Started Jun 04 01:55:37 PM PDT 24
Finished Jun 04 01:56:27 PM PDT 24
Peak memory 201796 kb
Host smart-00f27d44-d421-40c7-ade6-2f724e8797c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757017727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.3757017727
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.940281681
Short name T194
Test name
Test status
Simulation time 165821036160 ps
CPU time 112.85 seconds
Started Jun 04 01:55:30 PM PDT 24
Finished Jun 04 01:57:24 PM PDT 24
Peak memory 201816 kb
Host smart-430bd95d-9594-46b9-8a16-d78cddd52aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940281681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.940281681
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.3803281482
Short name T195
Test name
Test status
Simulation time 491369396478 ps
CPU time 273.34 seconds
Started Jun 04 01:55:30 PM PDT 24
Finished Jun 04 02:00:04 PM PDT 24
Peak memory 201768 kb
Host smart-e84b3d49-73dc-484b-b91f-59e4f5b758b4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803281482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.3803281482
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.3774821458
Short name T30
Test name
Test status
Simulation time 331458551073 ps
CPU time 163.76 seconds
Started Jun 04 01:55:30 PM PDT 24
Finished Jun 04 01:58:15 PM PDT 24
Peak memory 201744 kb
Host smart-4442d786-51b9-42ef-af15-e8bad66c0738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774821458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.3774821458
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.1881912658
Short name T529
Test name
Test status
Simulation time 481479321565 ps
CPU time 1040.51 seconds
Started Jun 04 01:55:30 PM PDT 24
Finished Jun 04 02:12:52 PM PDT 24
Peak memory 201780 kb
Host smart-ea474ee6-7ca6-41b9-86f2-92f3e29a43ef
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881912658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.1881912658
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.1241804339
Short name T793
Test name
Test status
Simulation time 392718595948 ps
CPU time 229.35 seconds
Started Jun 04 01:55:32 PM PDT 24
Finished Jun 04 01:59:22 PM PDT 24
Peak memory 201788 kb
Host smart-e74d3271-3e5c-4de8-9b56-d9c71a14a019
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241804339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.1241804339
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.1833070716
Short name T225
Test name
Test status
Simulation time 132346994365 ps
CPU time 556.6 seconds
Started Jun 04 01:55:37 PM PDT 24
Finished Jun 04 02:04:54 PM PDT 24
Peak memory 202140 kb
Host smart-774e2f6f-d5ca-4e92-9da2-42c067a747e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833070716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.1833070716
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.2927013174
Short name T493
Test name
Test status
Simulation time 37272202234 ps
CPU time 90.64 seconds
Started Jun 04 01:55:37 PM PDT 24
Finished Jun 04 01:57:08 PM PDT 24
Peak memory 201572 kb
Host smart-0415f2e9-f764-472e-b9b8-ea1eab000cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927013174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.2927013174
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.377528864
Short name T602
Test name
Test status
Simulation time 5246544347 ps
CPU time 3.56 seconds
Started Jun 04 01:55:37 PM PDT 24
Finished Jun 04 01:55:41 PM PDT 24
Peak memory 201572 kb
Host smart-fb20a934-444a-442f-ba1c-433467db4c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377528864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.377528864
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.3939290054
Short name T631
Test name
Test status
Simulation time 5989373644 ps
CPU time 4.21 seconds
Started Jun 04 01:55:30 PM PDT 24
Finished Jun 04 01:55:35 PM PDT 24
Peak memory 201636 kb
Host smart-219eb99e-ee28-4d53-b64f-a351b2b978e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939290054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.3939290054
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.1895527379
Short name T275
Test name
Test status
Simulation time 255782057951 ps
CPU time 170.76 seconds
Started Jun 04 01:55:38 PM PDT 24
Finished Jun 04 01:58:30 PM PDT 24
Peak memory 210188 kb
Host smart-82f77ff9-6e7a-4521-9c9c-f87c1c48b9bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895527379 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.1895527379
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.2346013552
Short name T394
Test name
Test status
Simulation time 389375855 ps
CPU time 0.79 seconds
Started Jun 04 01:55:43 PM PDT 24
Finished Jun 04 01:55:44 PM PDT 24
Peak memory 201472 kb
Host smart-460e28db-bc05-4063-91a5-f0139b4ab194
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346013552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.2346013552
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.3258809728
Short name T346
Test name
Test status
Simulation time 164030284238 ps
CPU time 97.03 seconds
Started Jun 04 01:55:44 PM PDT 24
Finished Jun 04 01:57:21 PM PDT 24
Peak memory 201848 kb
Host smart-fb8f9411-44dd-4ac5-981c-9b780384b34f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258809728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.3258809728
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.2497117739
Short name T213
Test name
Test status
Simulation time 531591823559 ps
CPU time 204.46 seconds
Started Jun 04 01:55:45 PM PDT 24
Finished Jun 04 01:59:10 PM PDT 24
Peak memory 201812 kb
Host smart-5b8b0ac2-9daa-451f-bd5b-4088e2ef6593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497117739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.2497117739
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.2738764078
Short name T614
Test name
Test status
Simulation time 165069722538 ps
CPU time 305.9 seconds
Started Jun 04 01:55:38 PM PDT 24
Finished Jun 04 02:00:44 PM PDT 24
Peak memory 201816 kb
Host smart-3b65609c-dd8d-4be2-a9a6-0c3965e9d2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738764078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.2738764078
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.2378999497
Short name T623
Test name
Test status
Simulation time 167254122146 ps
CPU time 91.5 seconds
Started Jun 04 01:55:43 PM PDT 24
Finished Jun 04 01:57:15 PM PDT 24
Peak memory 201692 kb
Host smart-bfd907f3-bf6a-4a65-9f3d-bcaa29327ea9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378999497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.2378999497
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.3595637468
Short name T335
Test name
Test status
Simulation time 330577964356 ps
CPU time 831.29 seconds
Started Jun 04 01:55:37 PM PDT 24
Finished Jun 04 02:09:29 PM PDT 24
Peak memory 201884 kb
Host smart-a5f143d2-45a6-42e0-b1d5-f1a3cd31a86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595637468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.3595637468
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.949330435
Short name T512
Test name
Test status
Simulation time 167505865735 ps
CPU time 120.08 seconds
Started Jun 04 01:55:39 PM PDT 24
Finished Jun 04 01:57:39 PM PDT 24
Peak memory 201772 kb
Host smart-2219634d-4470-4b8c-90ea-02b867444502
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=949330435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fixe
d.949330435
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.301185742
Short name T210
Test name
Test status
Simulation time 165711076856 ps
CPU time 99.08 seconds
Started Jun 04 01:55:44 PM PDT 24
Finished Jun 04 01:57:24 PM PDT 24
Peak memory 201904 kb
Host smart-828e4b5e-a49a-4166-ac2c-89dd6daa9e6f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301185742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_
wakeup.301185742
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.4036771478
Short name T558
Test name
Test status
Simulation time 399283194413 ps
CPU time 993.72 seconds
Started Jun 04 01:55:45 PM PDT 24
Finished Jun 04 02:12:19 PM PDT 24
Peak memory 201744 kb
Host smart-338f25aa-245f-4038-8b34-ec8c1afbef7c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036771478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.4036771478
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.2364345247
Short name T437
Test name
Test status
Simulation time 123637428290 ps
CPU time 497.55 seconds
Started Jun 04 01:55:43 PM PDT 24
Finished Jun 04 02:04:01 PM PDT 24
Peak memory 202108 kb
Host smart-0468ca18-b229-4239-87fd-997624b7d0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364345247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.2364345247
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.2626535766
Short name T694
Test name
Test status
Simulation time 23918276259 ps
CPU time 53.43 seconds
Started Jun 04 01:55:43 PM PDT 24
Finished Jun 04 01:56:37 PM PDT 24
Peak memory 201544 kb
Host smart-b4dea6a4-2469-4179-acaf-a6220fb5ea3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626535766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.2626535766
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.3650222316
Short name T651
Test name
Test status
Simulation time 3733479169 ps
CPU time 2.37 seconds
Started Jun 04 01:55:43 PM PDT 24
Finished Jun 04 01:55:46 PM PDT 24
Peak memory 201580 kb
Host smart-4ff91e09-a35f-4e00-9bfe-9b117195a01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650222316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.3650222316
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.2337610676
Short name T490
Test name
Test status
Simulation time 5861048192 ps
CPU time 3.92 seconds
Started Jun 04 01:55:37 PM PDT 24
Finished Jun 04 01:55:41 PM PDT 24
Peak memory 201636 kb
Host smart-2b9e33bc-1bcd-450a-a0f7-85fcd2bd6ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337610676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.2337610676
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.4284372575
Short name T508
Test name
Test status
Simulation time 384695746312 ps
CPU time 730.93 seconds
Started Jun 04 01:55:45 PM PDT 24
Finished Jun 04 02:07:56 PM PDT 24
Peak memory 201760 kb
Host smart-4e34c19c-5652-4838-8d6f-9b2b1718eaec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284372575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.4284372575
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.2516628143
Short name T696
Test name
Test status
Simulation time 14344444888 ps
CPU time 38.17 seconds
Started Jun 04 01:55:43 PM PDT 24
Finished Jun 04 01:56:22 PM PDT 24
Peak memory 216068 kb
Host smart-d2faf46e-67e5-487a-bc43-70feb2ba8b98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516628143 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.2516628143
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.53077344
Short name T100
Test name
Test status
Simulation time 493076925 ps
CPU time 0.95 seconds
Started Jun 04 01:56:00 PM PDT 24
Finished Jun 04 01:56:02 PM PDT 24
Peak memory 201468 kb
Host smart-15b8f59c-5e97-4f2e-9c90-e10db034c654
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53077344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.53077344
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.1483072111
Short name T294
Test name
Test status
Simulation time 326921527299 ps
CPU time 786.79 seconds
Started Jun 04 01:55:51 PM PDT 24
Finished Jun 04 02:08:58 PM PDT 24
Peak memory 201812 kb
Host smart-d8e916a4-97d3-4da4-a511-cf55d1fefb17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483072111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.1483072111
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.490308738
Short name T646
Test name
Test status
Simulation time 333243803848 ps
CPU time 428.19 seconds
Started Jun 04 01:55:53 PM PDT 24
Finished Jun 04 02:03:02 PM PDT 24
Peak memory 201764 kb
Host smart-6ccf393e-99a0-44ec-877c-62f75fdf4613
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=490308738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrup
t_fixed.490308738
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.3961376709
Short name T449
Test name
Test status
Simulation time 159839212559 ps
CPU time 95.78 seconds
Started Jun 04 01:55:50 PM PDT 24
Finished Jun 04 01:57:26 PM PDT 24
Peak memory 201780 kb
Host smart-a14c6e81-8d0e-4c8a-97ab-ebc21162a137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961376709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.3961376709
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.972976960
Short name T697
Test name
Test status
Simulation time 166698325797 ps
CPU time 375.82 seconds
Started Jun 04 01:55:51 PM PDT 24
Finished Jun 04 02:02:08 PM PDT 24
Peak memory 201796 kb
Host smart-cca1e0f9-4f2a-4fbd-8a1b-bada5521ae73
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=972976960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fixe
d.972976960
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.2806890404
Short name T289
Test name
Test status
Simulation time 550130643797 ps
CPU time 280.11 seconds
Started Jun 04 01:55:52 PM PDT 24
Finished Jun 04 02:00:32 PM PDT 24
Peak memory 201816 kb
Host smart-9e54d750-88bf-4c62-bd51-a5f9b56dc2ee
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806890404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.2806890404
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.224931271
Short name T542
Test name
Test status
Simulation time 394056102106 ps
CPU time 188.82 seconds
Started Jun 04 01:55:51 PM PDT 24
Finished Jun 04 01:59:00 PM PDT 24
Peak memory 201828 kb
Host smart-798b2aa4-d241-4e5d-8db1-c348f8f06136
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224931271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
adc_ctrl_filters_wakeup_fixed.224931271
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.266841821
Short name T452
Test name
Test status
Simulation time 90533090456 ps
CPU time 325.66 seconds
Started Jun 04 01:56:00 PM PDT 24
Finished Jun 04 02:01:26 PM PDT 24
Peak memory 202052 kb
Host smart-cf8d6a63-18f6-420e-b5c7-2758c457fcd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266841821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.266841821
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.166522315
Short name T673
Test name
Test status
Simulation time 22487241007 ps
CPU time 13.47 seconds
Started Jun 04 01:56:01 PM PDT 24
Finished Jun 04 01:56:15 PM PDT 24
Peak memory 201572 kb
Host smart-fcf46138-feff-4acd-bd13-cf5df5f21895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166522315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.166522315
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.2495972576
Short name T444
Test name
Test status
Simulation time 4934591047 ps
CPU time 6.6 seconds
Started Jun 04 01:56:00 PM PDT 24
Finished Jun 04 01:56:07 PM PDT 24
Peak memory 201608 kb
Host smart-d7d0be1d-1181-4454-aef1-53b3da27e337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495972576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.2495972576
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.1523117881
Short name T116
Test name
Test status
Simulation time 5888992151 ps
CPU time 3.18 seconds
Started Jun 04 01:55:43 PM PDT 24
Finished Jun 04 01:55:46 PM PDT 24
Peak memory 201644 kb
Host smart-5e70a018-cf9c-4e30-aa5f-19db6587683b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523117881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.1523117881
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.531729126
Short name T411
Test name
Test status
Simulation time 9554674706 ps
CPU time 22.48 seconds
Started Jun 04 01:55:59 PM PDT 24
Finished Jun 04 01:56:22 PM PDT 24
Peak memory 201624 kb
Host smart-420e2c74-a699-4675-a5de-c52d093510b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531729126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all.
531729126
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.962904902
Short name T424
Test name
Test status
Simulation time 456682245 ps
CPU time 1.59 seconds
Started Jun 04 01:56:18 PM PDT 24
Finished Jun 04 01:56:20 PM PDT 24
Peak memory 201472 kb
Host smart-b485a3b2-a4a8-43a0-8ff8-8608e9f479a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962904902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.962904902
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.1087682107
Short name T707
Test name
Test status
Simulation time 503623822774 ps
CPU time 627.29 seconds
Started Jun 04 01:56:10 PM PDT 24
Finished Jun 04 02:06:38 PM PDT 24
Peak memory 201768 kb
Host smart-5935c8ce-e9f3-42c3-90f2-18fccdc04009
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087682107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.1087682107
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.3688472899
Short name T710
Test name
Test status
Simulation time 329681320233 ps
CPU time 212.07 seconds
Started Jun 04 01:55:59 PM PDT 24
Finished Jun 04 01:59:31 PM PDT 24
Peak memory 201816 kb
Host smart-725df164-91c7-4350-8092-f3acedf32ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688472899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.3688472899
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.3357807644
Short name T538
Test name
Test status
Simulation time 329090948334 ps
CPU time 193.32 seconds
Started Jun 04 01:56:10 PM PDT 24
Finished Jun 04 01:59:24 PM PDT 24
Peak memory 201804 kb
Host smart-2a9ee695-d193-4029-a702-9e8087593653
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357807644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.3357807644
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.3307104031
Short name T714
Test name
Test status
Simulation time 167391334251 ps
CPU time 52.99 seconds
Started Jun 04 01:55:58 PM PDT 24
Finished Jun 04 01:56:52 PM PDT 24
Peak memory 201912 kb
Host smart-7a2dc6cd-5759-4393-b3d5-92e0a1535a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307104031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.3307104031
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.2554936035
Short name T768
Test name
Test status
Simulation time 164173479797 ps
CPU time 370.4 seconds
Started Jun 04 01:55:59 PM PDT 24
Finished Jun 04 02:02:10 PM PDT 24
Peak memory 201772 kb
Host smart-6b4c2e99-30d5-489d-96f8-c897e4443012
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554936035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.2554936035
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.1080030957
Short name T291
Test name
Test status
Simulation time 527345687221 ps
CPU time 1332.28 seconds
Started Jun 04 01:56:08 PM PDT 24
Finished Jun 04 02:18:21 PM PDT 24
Peak memory 201812 kb
Host smart-3bfa720a-ad0a-4f14-935e-d0ac8fdcf170
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080030957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.1080030957
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.3308907832
Short name T457
Test name
Test status
Simulation time 400340085198 ps
CPU time 94.95 seconds
Started Jun 04 01:56:08 PM PDT 24
Finished Jun 04 01:57:43 PM PDT 24
Peak memory 201816 kb
Host smart-99f4a8ee-d2ec-4ec7-be23-52bfcf4bd771
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308907832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.3308907832
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.2716323308
Short name T48
Test name
Test status
Simulation time 99740785265 ps
CPU time 413.46 seconds
Started Jun 04 01:56:18 PM PDT 24
Finished Jun 04 02:03:12 PM PDT 24
Peak memory 202080 kb
Host smart-6896cb73-e12c-46f7-8c71-6967887e8876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716323308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.2716323308
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.3573863257
Short name T414
Test name
Test status
Simulation time 24158044463 ps
CPU time 53.47 seconds
Started Jun 04 01:56:21 PM PDT 24
Finished Jun 04 01:57:15 PM PDT 24
Peak memory 201612 kb
Host smart-e170fc93-523d-4352-b03c-171594d91cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573863257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.3573863257
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.177441088
Short name T524
Test name
Test status
Simulation time 5134804393 ps
CPU time 12.29 seconds
Started Jun 04 01:56:08 PM PDT 24
Finished Jun 04 01:56:21 PM PDT 24
Peak memory 201676 kb
Host smart-764b8b14-f2ad-4c0c-aeb1-898adae2c6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177441088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.177441088
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.2555269253
Short name T560
Test name
Test status
Simulation time 5595055140 ps
CPU time 15.28 seconds
Started Jun 04 01:55:59 PM PDT 24
Finished Jun 04 01:56:15 PM PDT 24
Peak memory 201668 kb
Host smart-ef903e3b-595b-43f9-a57a-80809ac5e727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555269253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.2555269253
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.2628677491
Short name T594
Test name
Test status
Simulation time 328932309058 ps
CPU time 1004.52 seconds
Started Jun 04 01:56:17 PM PDT 24
Finished Jun 04 02:13:02 PM PDT 24
Peak memory 212808 kb
Host smart-19d422e2-a179-4e40-8a4e-f04e0e907e59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628677491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.2628677491
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.862854332
Short name T295
Test name
Test status
Simulation time 208821145412 ps
CPU time 325.97 seconds
Started Jun 04 01:56:19 PM PDT 24
Finished Jun 04 02:01:46 PM PDT 24
Peak memory 210156 kb
Host smart-c0204233-5f72-4999-aff3-19838cfa3ad4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862854332 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.862854332
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.3275325355
Short name T735
Test name
Test status
Simulation time 523832226 ps
CPU time 0.7 seconds
Started Jun 04 01:56:26 PM PDT 24
Finished Jun 04 01:56:27 PM PDT 24
Peak memory 201496 kb
Host smart-f638508a-bb10-42ec-9a8f-1fc271d6bb50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275325355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.3275325355
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.1553110513
Short name T588
Test name
Test status
Simulation time 295894798079 ps
CPU time 304.9 seconds
Started Jun 04 01:56:27 PM PDT 24
Finished Jun 04 02:01:33 PM PDT 24
Peak memory 201764 kb
Host smart-ce5bb6eb-03e0-443e-93bf-7faa48239e0f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553110513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.1553110513
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.2580528336
Short name T526
Test name
Test status
Simulation time 195030160794 ps
CPU time 316.33 seconds
Started Jun 04 01:56:23 PM PDT 24
Finished Jun 04 02:01:40 PM PDT 24
Peak memory 201804 kb
Host smart-c5520ff5-2e74-466e-a642-66d4f96c4c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580528336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.2580528336
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.3077269586
Short name T525
Test name
Test status
Simulation time 165046777132 ps
CPU time 385.97 seconds
Started Jun 04 01:56:21 PM PDT 24
Finished Jun 04 02:02:47 PM PDT 24
Peak memory 201776 kb
Host smart-5ebe024d-3833-4b9f-ad17-c365975cb38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077269586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.3077269586
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.4214703443
Short name T406
Test name
Test status
Simulation time 488981387663 ps
CPU time 566.18 seconds
Started Jun 04 01:56:20 PM PDT 24
Finished Jun 04 02:05:46 PM PDT 24
Peak memory 201772 kb
Host smart-5adc81d2-0a8d-408a-9e2e-e5f1e78f961f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214703443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.4214703443
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.3848172928
Short name T15
Test name
Test status
Simulation time 165654516769 ps
CPU time 95.26 seconds
Started Jun 04 01:56:18 PM PDT 24
Finished Jun 04 01:57:54 PM PDT 24
Peak memory 201868 kb
Host smart-e6eaa8eb-f647-4a8d-a2a7-0f403a052430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848172928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.3848172928
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.2335133103
Short name T407
Test name
Test status
Simulation time 320528002936 ps
CPU time 788.4 seconds
Started Jun 04 01:56:22 PM PDT 24
Finished Jun 04 02:09:30 PM PDT 24
Peak memory 201764 kb
Host smart-94d4a921-fdb2-4e35-bddf-9fbfc2091516
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335133103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.2335133103
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.3773276402
Short name T339
Test name
Test status
Simulation time 569761586089 ps
CPU time 1249.86 seconds
Started Jun 04 01:56:19 PM PDT 24
Finished Jun 04 02:17:10 PM PDT 24
Peak memory 201880 kb
Host smart-99c3f0a4-a7c3-4ca0-bef1-2614853edac5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773276402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.3773276402
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.3575463447
Short name T691
Test name
Test status
Simulation time 406235416057 ps
CPU time 938.64 seconds
Started Jun 04 01:56:18 PM PDT 24
Finished Jun 04 02:11:58 PM PDT 24
Peak memory 201872 kb
Host smart-f2a2f504-1859-49ae-b270-3499606ab8fe
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575463447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.3575463447
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.2779613279
Short name T603
Test name
Test status
Simulation time 66050082767 ps
CPU time 237.79 seconds
Started Jun 04 01:56:25 PM PDT 24
Finished Jun 04 02:00:24 PM PDT 24
Peak memory 202120 kb
Host smart-2de83732-068f-479a-bbc8-4aba9e6a68da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779613279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.2779613279
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.431207904
Short name T727
Test name
Test status
Simulation time 31894983238 ps
CPU time 18.63 seconds
Started Jun 04 01:56:25 PM PDT 24
Finished Jun 04 01:56:44 PM PDT 24
Peak memory 201536 kb
Host smart-5e6813f9-3473-47bd-8936-8d794d56b05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431207904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.431207904
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.1563960915
Short name T497
Test name
Test status
Simulation time 4686918162 ps
CPU time 1.6 seconds
Started Jun 04 01:56:26 PM PDT 24
Finished Jun 04 01:56:28 PM PDT 24
Peak memory 201612 kb
Host smart-79407389-4c90-45ed-a12c-b7814a8753cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563960915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.1563960915
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.714068509
Short name T142
Test name
Test status
Simulation time 5926193690 ps
CPU time 8.5 seconds
Started Jun 04 01:56:20 PM PDT 24
Finished Jun 04 01:56:29 PM PDT 24
Peak memory 201632 kb
Host smart-ce00d18f-fed7-4078-b3ee-0570511ab9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714068509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.714068509
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.1865732633
Short name T244
Test name
Test status
Simulation time 683059366349 ps
CPU time 256.5 seconds
Started Jun 04 01:56:25 PM PDT 24
Finished Jun 04 02:00:42 PM PDT 24
Peak memory 201868 kb
Host smart-3ddec6fe-f13c-4ee1-8d5d-ecfc2a63c506
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865732633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.1865732633
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.3258218328
Short name T591
Test name
Test status
Simulation time 32004093431 ps
CPU time 72.25 seconds
Started Jun 04 01:56:26 PM PDT 24
Finished Jun 04 01:57:39 PM PDT 24
Peak memory 210452 kb
Host smart-d550a11f-645d-44af-95cf-7b14afdfd5ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258218328 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.3258218328
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.2454399739
Short name T73
Test name
Test status
Simulation time 404811740 ps
CPU time 0.82 seconds
Started Jun 04 01:56:39 PM PDT 24
Finished Jun 04 01:56:41 PM PDT 24
Peak memory 201472 kb
Host smart-a2dbac51-8514-4696-83bb-90977c0ed7a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454399739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.2454399739
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.1356190315
Short name T302
Test name
Test status
Simulation time 354653748144 ps
CPU time 422.68 seconds
Started Jun 04 01:56:22 PM PDT 24
Finished Jun 04 02:03:26 PM PDT 24
Peak memory 201756 kb
Host smart-e0fc15c3-71e2-4a58-b8d5-18d682e354ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356190315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.1356190315
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.2862523957
Short name T679
Test name
Test status
Simulation time 332899647548 ps
CPU time 750.83 seconds
Started Jun 04 01:56:23 PM PDT 24
Finished Jun 04 02:08:54 PM PDT 24
Peak memory 201756 kb
Host smart-2473f811-eb1f-410d-aef9-203cc234d38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862523957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.2862523957
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.3285274133
Short name T564
Test name
Test status
Simulation time 331250540492 ps
CPU time 742.85 seconds
Started Jun 04 01:56:26 PM PDT 24
Finished Jun 04 02:08:49 PM PDT 24
Peak memory 201716 kb
Host smart-450ba535-2016-43ed-85e8-902b6f23f9c5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285274133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.3285274133
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.287599143
Short name T565
Test name
Test status
Simulation time 334406746361 ps
CPU time 76.58 seconds
Started Jun 04 01:56:27 PM PDT 24
Finished Jun 04 01:57:44 PM PDT 24
Peak memory 201848 kb
Host smart-b4c4be65-2dbb-4dd5-a16b-6c3b50356176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287599143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.287599143
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.4071784852
Short name T544
Test name
Test status
Simulation time 486783445638 ps
CPU time 277.18 seconds
Started Jun 04 01:56:25 PM PDT 24
Finished Jun 04 02:01:03 PM PDT 24
Peak memory 201848 kb
Host smart-73618d79-7684-4286-8c67-0d0972e0576c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071784852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.4071784852
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.1720849040
Short name T549
Test name
Test status
Simulation time 360488228812 ps
CPU time 504.43 seconds
Started Jun 04 01:56:24 PM PDT 24
Finished Jun 04 02:04:49 PM PDT 24
Peak memory 201860 kb
Host smart-777a4c0e-0518-45a3-b7aa-eced9d36dbcc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720849040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.1720849040
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.36528146
Short name T731
Test name
Test status
Simulation time 595196652346 ps
CPU time 82.08 seconds
Started Jun 04 01:56:26 PM PDT 24
Finished Jun 04 01:57:48 PM PDT 24
Peak memory 201760 kb
Host smart-54dd2df7-b9c9-49fb-81e9-335a9f28aab8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36528146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.a
dc_ctrl_filters_wakeup_fixed.36528146
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.1783558301
Short name T355
Test name
Test status
Simulation time 138322524574 ps
CPU time 469.56 seconds
Started Jun 04 01:56:35 PM PDT 24
Finished Jun 04 02:04:25 PM PDT 24
Peak memory 202144 kb
Host smart-cde92624-2c4b-416a-9735-0f6846c39308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783558301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.1783558301
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.1865125193
Short name T149
Test name
Test status
Simulation time 33333228045 ps
CPU time 7.83 seconds
Started Jun 04 01:56:32 PM PDT 24
Finished Jun 04 01:56:40 PM PDT 24
Peak memory 201596 kb
Host smart-c724b776-cf45-4291-b9e3-b2ba011f26c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865125193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.1865125193
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.872831563
Short name T7
Test name
Test status
Simulation time 4362496880 ps
CPU time 5.12 seconds
Started Jun 04 01:56:27 PM PDT 24
Finished Jun 04 01:56:33 PM PDT 24
Peak memory 201620 kb
Host smart-b5a2db5f-b2e2-4597-8795-ff9227f7a89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872831563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.872831563
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.3978346808
Short name T548
Test name
Test status
Simulation time 5711032760 ps
CPU time 14.73 seconds
Started Jun 04 01:56:27 PM PDT 24
Finished Jun 04 01:56:42 PM PDT 24
Peak memory 201608 kb
Host smart-30dbf311-1dbb-4b73-a528-959bf4ce163a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978346808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.3978346808
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.404266166
Short name T766
Test name
Test status
Simulation time 253852288238 ps
CPU time 637.81 seconds
Started Jun 04 01:56:32 PM PDT 24
Finished Jun 04 02:07:11 PM PDT 24
Peak memory 202164 kb
Host smart-b4af0e8b-059b-4d8d-aeba-8d23338da1fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404266166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all.
404266166
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.2036678502
Short name T668
Test name
Test status
Simulation time 490682938 ps
CPU time 0.9 seconds
Started Jun 04 01:56:46 PM PDT 24
Finished Jun 04 01:56:47 PM PDT 24
Peak memory 201468 kb
Host smart-e0a53ab4-a942-47f2-942d-a1acde1f69fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036678502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.2036678502
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.1660643334
Short name T172
Test name
Test status
Simulation time 339581846084 ps
CPU time 214.72 seconds
Started Jun 04 01:56:39 PM PDT 24
Finished Jun 04 02:00:15 PM PDT 24
Peak memory 201704 kb
Host smart-f31e5db0-f8e1-4db7-bfc9-a6162559838b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660643334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.1660643334
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.3259144607
Short name T268
Test name
Test status
Simulation time 160157372588 ps
CPU time 90.83 seconds
Started Jun 04 01:56:41 PM PDT 24
Finished Jun 04 01:58:12 PM PDT 24
Peak memory 201852 kb
Host smart-9291027f-7482-4378-a28f-3d2ef43edcf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259144607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.3259144607
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.1460956439
Short name T596
Test name
Test status
Simulation time 492743993752 ps
CPU time 1186.52 seconds
Started Jun 04 01:56:40 PM PDT 24
Finished Jun 04 02:16:27 PM PDT 24
Peak memory 201768 kb
Host smart-16c82d43-2eee-4c56-91b8-dea470ab71ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460956439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.1460956439
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.144782866
Short name T699
Test name
Test status
Simulation time 159756719772 ps
CPU time 89.53 seconds
Started Jun 04 01:56:39 PM PDT 24
Finished Jun 04 01:58:10 PM PDT 24
Peak memory 201800 kb
Host smart-91263adc-257e-4f53-936c-4c48138b59bb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=144782866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrup
t_fixed.144782866
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.3998222983
Short name T202
Test name
Test status
Simulation time 497636952463 ps
CPU time 280.25 seconds
Started Jun 04 01:56:37 PM PDT 24
Finished Jun 04 02:01:18 PM PDT 24
Peak memory 201836 kb
Host smart-9c761a68-b662-4011-b3ee-42ddf4289b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998222983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.3998222983
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.1674052556
Short name T408
Test name
Test status
Simulation time 169958658231 ps
CPU time 108.52 seconds
Started Jun 04 01:56:39 PM PDT 24
Finished Jun 04 01:58:29 PM PDT 24
Peak memory 201816 kb
Host smart-db318c7e-72a2-4de5-a855-0050c4431559
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674052556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.1674052556
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.2620951844
Short name T281
Test name
Test status
Simulation time 378766153643 ps
CPU time 152.34 seconds
Started Jun 04 01:56:39 PM PDT 24
Finished Jun 04 01:59:12 PM PDT 24
Peak memory 201880 kb
Host smart-fee23aeb-ac3b-4afe-b6b9-9cccd938e9ae
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620951844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.2620951844
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.3856533629
Short name T795
Test name
Test status
Simulation time 608808280761 ps
CPU time 1366.91 seconds
Started Jun 04 01:56:41 PM PDT 24
Finished Jun 04 02:19:29 PM PDT 24
Peak memory 201800 kb
Host smart-97341309-09ef-4761-a6a0-e670e000a39a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856533629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.3856533629
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.3859586564
Short name T356
Test name
Test status
Simulation time 123534917831 ps
CPU time 436.59 seconds
Started Jun 04 01:56:47 PM PDT 24
Finished Jun 04 02:04:04 PM PDT 24
Peak memory 202092 kb
Host smart-79fefdf1-1317-4d68-af12-70cc1538b4b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859586564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.3859586564
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.3589699589
Short name T647
Test name
Test status
Simulation time 44452915346 ps
CPU time 43.46 seconds
Started Jun 04 01:56:47 PM PDT 24
Finished Jun 04 01:57:31 PM PDT 24
Peak memory 201624 kb
Host smart-e8ec955d-5306-49f2-b50d-535dcbef19b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589699589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.3589699589
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.3984977117
Short name T10
Test name
Test status
Simulation time 3476409520 ps
CPU time 9.41 seconds
Started Jun 04 01:56:47 PM PDT 24
Finished Jun 04 01:56:57 PM PDT 24
Peak memory 201608 kb
Host smart-79a151ff-aa45-479b-a823-59c7282dd4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984977117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.3984977117
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.2207945024
Short name T590
Test name
Test status
Simulation time 5897078341 ps
CPU time 3.79 seconds
Started Jun 04 01:56:42 PM PDT 24
Finished Jun 04 01:56:46 PM PDT 24
Peak memory 201636 kb
Host smart-5fff215e-aed6-4654-94a2-2154383ae381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207945024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.2207945024
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.838886223
Short name T607
Test name
Test status
Simulation time 74752864347 ps
CPU time 186.45 seconds
Started Jun 04 01:56:47 PM PDT 24
Finished Jun 04 01:59:54 PM PDT 24
Peak memory 201540 kb
Host smart-7faf9160-b760-4b07-8073-1bb3586b1edc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838886223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all.
838886223
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.2627199289
Short name T516
Test name
Test status
Simulation time 350410962 ps
CPU time 0.82 seconds
Started Jun 04 01:56:53 PM PDT 24
Finished Jun 04 01:56:55 PM PDT 24
Peak memory 201544 kb
Host smart-c8bb7a24-d16b-4358-aa22-585ffecf400f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627199289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.2627199289
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.578722538
Short name T617
Test name
Test status
Simulation time 498769812475 ps
CPU time 328.5 seconds
Started Jun 04 01:56:46 PM PDT 24
Finished Jun 04 02:02:15 PM PDT 24
Peak memory 201840 kb
Host smart-28022e94-39c4-43a3-87e3-27f45628d4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578722538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.578722538
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.4222478674
Short name T734
Test name
Test status
Simulation time 163521610501 ps
CPU time 96.94 seconds
Started Jun 04 01:56:45 PM PDT 24
Finished Jun 04 01:58:23 PM PDT 24
Peak memory 201720 kb
Host smart-35e09909-2c10-4a8a-9702-e8c6d33200d5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222478674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.4222478674
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.2330621601
Short name T91
Test name
Test status
Simulation time 324714361272 ps
CPU time 214.57 seconds
Started Jun 04 01:56:47 PM PDT 24
Finished Jun 04 02:00:22 PM PDT 24
Peak memory 201788 kb
Host smart-25978ec6-ca28-4363-9598-953d437a4c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330621601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.2330621601
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.3399339121
Short name T405
Test name
Test status
Simulation time 326523941391 ps
CPU time 197.36 seconds
Started Jun 04 01:56:46 PM PDT 24
Finished Jun 04 02:00:04 PM PDT 24
Peak memory 201716 kb
Host smart-e61ea5a8-b96e-4b24-8892-6852146c1196
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399339121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.3399339121
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.4170552939
Short name T298
Test name
Test status
Simulation time 179139472376 ps
CPU time 92.22 seconds
Started Jun 04 01:56:45 PM PDT 24
Finished Jun 04 01:58:18 PM PDT 24
Peak memory 201784 kb
Host smart-ea4823c7-81c4-43cc-9a25-a186e4a5447f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170552939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.4170552939
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.1764989418
Short name T669
Test name
Test status
Simulation time 192546411211 ps
CPU time 470.79 seconds
Started Jun 04 01:56:46 PM PDT 24
Finished Jun 04 02:04:37 PM PDT 24
Peak memory 201788 kb
Host smart-431975ca-b747-44b8-8136-552575731340
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764989418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.1764989418
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.2262292846
Short name T354
Test name
Test status
Simulation time 136963238977 ps
CPU time 683.05 seconds
Started Jun 04 01:56:52 PM PDT 24
Finished Jun 04 02:08:16 PM PDT 24
Peak memory 202112 kb
Host smart-c4e8cd4f-b545-47af-8b8f-717a3cdb9524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262292846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.2262292846
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.3126629574
Short name T375
Test name
Test status
Simulation time 26942962200 ps
CPU time 18 seconds
Started Jun 04 01:56:46 PM PDT 24
Finished Jun 04 01:57:05 PM PDT 24
Peak memory 201536 kb
Host smart-4f24bbb9-703a-47f1-9ac9-abe877f642b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126629574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.3126629574
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.886718535
Short name T467
Test name
Test status
Simulation time 5484103337 ps
CPU time 6.84 seconds
Started Jun 04 01:56:46 PM PDT 24
Finished Jun 04 01:56:54 PM PDT 24
Peak memory 201568 kb
Host smart-ca626664-23c3-41c3-9f7e-8ae7d5fb352c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886718535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.886718535
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.753160907
Short name T690
Test name
Test status
Simulation time 6133410558 ps
CPU time 16.03 seconds
Started Jun 04 01:56:46 PM PDT 24
Finished Jun 04 01:57:03 PM PDT 24
Peak memory 201636 kb
Host smart-a19d3087-6af8-4d46-8c93-666af7e6d86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753160907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.753160907
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.3629472114
Short name T597
Test name
Test status
Simulation time 369327747556 ps
CPU time 183.97 seconds
Started Jun 04 01:56:53 PM PDT 24
Finished Jun 04 01:59:57 PM PDT 24
Peak memory 209984 kb
Host smart-015687ad-f40f-46da-a3da-65ded6e1cce3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629472114 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.3629472114
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.1560066050
Short name T507
Test name
Test status
Simulation time 499361949 ps
CPU time 1.69 seconds
Started Jun 04 01:56:59 PM PDT 24
Finished Jun 04 01:57:02 PM PDT 24
Peak memory 201468 kb
Host smart-78a7aedc-4771-4b0d-8844-759be3347302
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560066050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.1560066050
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.4255990403
Short name T176
Test name
Test status
Simulation time 380764631493 ps
CPU time 196.78 seconds
Started Jun 04 01:56:52 PM PDT 24
Finished Jun 04 02:00:10 PM PDT 24
Peak memory 201808 kb
Host smart-aed9fc13-6537-40be-88f3-d108f0b2a557
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255990403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.4255990403
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.2799870715
Short name T214
Test name
Test status
Simulation time 205901051833 ps
CPU time 113.2 seconds
Started Jun 04 01:56:55 PM PDT 24
Finished Jun 04 01:58:48 PM PDT 24
Peak memory 201864 kb
Host smart-73396b81-3042-4569-ad1c-55310020de4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799870715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.2799870715
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.1484767111
Short name T781
Test name
Test status
Simulation time 163009088137 ps
CPU time 64.81 seconds
Started Jun 04 01:56:55 PM PDT 24
Finished Jun 04 01:58:01 PM PDT 24
Peak memory 201768 kb
Host smart-7d43582d-8e63-4d76-8bb1-21eada764e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484767111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.1484767111
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.3899911142
Short name T555
Test name
Test status
Simulation time 333813826526 ps
CPU time 717.21 seconds
Started Jun 04 01:56:53 PM PDT 24
Finished Jun 04 02:08:51 PM PDT 24
Peak memory 201780 kb
Host smart-4240dbac-bf6f-443d-9224-adbb668cc67c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899911142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.3899911142
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.3375896678
Short name T416
Test name
Test status
Simulation time 170656289264 ps
CPU time 411.2 seconds
Started Jun 04 01:56:54 PM PDT 24
Finished Jun 04 02:03:46 PM PDT 24
Peak memory 201696 kb
Host smart-6b8dad6f-8e19-4f28-a1f6-81039ec8ce0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375896678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.3375896678
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.1444374318
Short name T187
Test name
Test status
Simulation time 162177529980 ps
CPU time 89.2 seconds
Started Jun 04 01:56:54 PM PDT 24
Finished Jun 04 01:58:24 PM PDT 24
Peak memory 201780 kb
Host smart-ac450bd4-166a-4322-8f61-88d25d31dfb5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444374318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.1444374318
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.4219936654
Short name T267
Test name
Test status
Simulation time 351347779264 ps
CPU time 397.77 seconds
Started Jun 04 01:56:54 PM PDT 24
Finished Jun 04 02:03:32 PM PDT 24
Peak memory 201856 kb
Host smart-d48319c1-c9e6-4454-9b61-c567139b3f07
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219936654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.4219936654
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.3510578162
Short name T464
Test name
Test status
Simulation time 612122655658 ps
CPU time 360.89 seconds
Started Jun 04 01:56:53 PM PDT 24
Finished Jun 04 02:02:55 PM PDT 24
Peak memory 201756 kb
Host smart-663beebb-ce7f-4f5a-b884-ef810838f71c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510578162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.3510578162
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.4069061453
Short name T746
Test name
Test status
Simulation time 38867558205 ps
CPU time 92.86 seconds
Started Jun 04 01:57:00 PM PDT 24
Finished Jun 04 01:58:34 PM PDT 24
Peak memory 201624 kb
Host smart-7cd743f7-e483-4ef6-8a96-5ad2842839f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069061453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.4069061453
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.4261482580
Short name T540
Test name
Test status
Simulation time 3863167008 ps
CPU time 2.9 seconds
Started Jun 04 01:57:03 PM PDT 24
Finished Jun 04 01:57:06 PM PDT 24
Peak memory 201560 kb
Host smart-ecaaf4a7-05b4-417b-94f5-1c4f84312cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261482580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.4261482580
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.3760740764
Short name T554
Test name
Test status
Simulation time 5900452220 ps
CPU time 4.35 seconds
Started Jun 04 01:56:54 PM PDT 24
Finished Jun 04 01:56:59 PM PDT 24
Peak memory 201636 kb
Host smart-e6ea759b-0ea6-4e90-ad0a-c5cb055243d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760740764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.3760740764
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.421102108
Short name T49
Test name
Test status
Simulation time 1648990872582 ps
CPU time 4215.57 seconds
Started Jun 04 01:57:02 PM PDT 24
Finished Jun 04 03:07:19 PM PDT 24
Peak memory 210284 kb
Host smart-cac83fb1-301d-4ea9-857c-fa7674a17743
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421102108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all.
421102108
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.3985473575
Short name T19
Test name
Test status
Simulation time 305739858979 ps
CPU time 290.13 seconds
Started Jun 04 01:57:00 PM PDT 24
Finished Jun 04 02:01:51 PM PDT 24
Peak memory 210428 kb
Host smart-ed92d29e-c7d9-4d90-af56-0b18e70def41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985473575 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.3985473575
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.2318944763
Short name T709
Test name
Test status
Simulation time 524909680 ps
CPU time 1.11 seconds
Started Jun 04 01:52:47 PM PDT 24
Finished Jun 04 01:52:49 PM PDT 24
Peak memory 201472 kb
Host smart-c57a7dce-c5f7-479d-86ca-952554423f44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318944763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.2318944763
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.2480380963
Short name T274
Test name
Test status
Simulation time 165456401241 ps
CPU time 99.69 seconds
Started Jun 04 01:52:34 PM PDT 24
Finished Jun 04 01:54:16 PM PDT 24
Peak memory 201808 kb
Host smart-e8e17cb2-e079-4331-ac31-ddf105e855e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480380963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.2480380963
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.3839714501
Short name T583
Test name
Test status
Simulation time 168814052560 ps
CPU time 103.03 seconds
Started Jun 04 01:53:06 PM PDT 24
Finished Jun 04 01:54:50 PM PDT 24
Peak memory 201900 kb
Host smart-a0a719cb-ec66-47cd-b31b-7e7026a8ad16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839714501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.3839714501
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.2401582323
Short name T530
Test name
Test status
Simulation time 157114022383 ps
CPU time 95.67 seconds
Started Jun 04 01:52:51 PM PDT 24
Finished Jun 04 01:54:29 PM PDT 24
Peak memory 201864 kb
Host smart-fd80c1ac-02b2-482d-ba31-6ce57b133381
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401582323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.2401582323
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.18775394
Short name T674
Test name
Test status
Simulation time 336474843376 ps
CPU time 754.58 seconds
Started Jun 04 01:52:50 PM PDT 24
Finished Jun 04 02:05:25 PM PDT 24
Peak memory 201836 kb
Host smart-62bb4583-f6f5-4bae-a282-1eb5a804f911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18775394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.18775394
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.1275782248
Short name T713
Test name
Test status
Simulation time 334866927472 ps
CPU time 775.48 seconds
Started Jun 04 01:52:39 PM PDT 24
Finished Jun 04 02:05:36 PM PDT 24
Peak memory 201760 kb
Host smart-854f5b81-b2d2-4cdb-9cc4-e5f93b596fbc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275782248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.1275782248
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.4202591804
Short name T191
Test name
Test status
Simulation time 352564021332 ps
CPU time 761.77 seconds
Started Jun 04 01:53:04 PM PDT 24
Finished Jun 04 02:05:47 PM PDT 24
Peak memory 201872 kb
Host smart-7e7e2d31-80af-4222-8b14-f88968d9d557
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202591804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.4202591804
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.2249634227
Short name T486
Test name
Test status
Simulation time 417710015040 ps
CPU time 247.7 seconds
Started Jun 04 01:52:46 PM PDT 24
Finished Jun 04 01:56:54 PM PDT 24
Peak memory 201780 kb
Host smart-1bf989eb-1567-4455-89ec-80a2df611f35
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249634227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.2249634227
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.311889908
Short name T351
Test name
Test status
Simulation time 63844541223 ps
CPU time 282.24 seconds
Started Jun 04 01:52:51 PM PDT 24
Finished Jun 04 01:57:35 PM PDT 24
Peak memory 202120 kb
Host smart-f10a4629-d42e-4fa3-bb17-39390b3b946a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311889908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.311889908
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.1421918285
Short name T401
Test name
Test status
Simulation time 29256003297 ps
CPU time 18.51 seconds
Started Jun 04 01:52:45 PM PDT 24
Finished Jun 04 01:53:05 PM PDT 24
Peak memory 201616 kb
Host smart-1ff466a6-279d-4d7b-b4ae-9371239a4fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421918285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.1421918285
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.3136170977
Short name T468
Test name
Test status
Simulation time 3422182082 ps
CPU time 8.79 seconds
Started Jun 04 01:52:47 PM PDT 24
Finished Jun 04 01:52:56 PM PDT 24
Peak memory 201608 kb
Host smart-68077df7-3dfe-4f64-8065-b437811c492b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136170977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.3136170977
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.1695834155
Short name T489
Test name
Test status
Simulation time 6106737347 ps
CPU time 7.39 seconds
Started Jun 04 01:52:51 PM PDT 24
Finished Jun 04 01:53:01 PM PDT 24
Peak memory 201632 kb
Host smart-81125a76-c73d-458e-9366-34e0f4f43a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695834155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.1695834155
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.1506404363
Short name T286
Test name
Test status
Simulation time 475733483154 ps
CPU time 866.72 seconds
Started Jun 04 01:52:59 PM PDT 24
Finished Jun 04 02:07:27 PM PDT 24
Peak memory 202120 kb
Host smart-35f6ec8b-aef8-46f2-82c8-dbb47e218460
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506404363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
1506404363
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.2418694229
Short name T659
Test name
Test status
Simulation time 149356878685 ps
CPU time 64.59 seconds
Started Jun 04 01:52:57 PM PDT 24
Finished Jun 04 01:54:03 PM PDT 24
Peak memory 210192 kb
Host smart-32c713be-b7cf-40c2-824e-fcb58cf4dcad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418694229 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.2418694229
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.3144656350
Short name T443
Test name
Test status
Simulation time 517371696 ps
CPU time 0.96 seconds
Started Jun 04 01:52:57 PM PDT 24
Finished Jun 04 01:52:59 PM PDT 24
Peak memory 201488 kb
Host smart-7ddd3905-d036-4973-b612-63dac52820d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144656350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.3144656350
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.2866652472
Short name T115
Test name
Test status
Simulation time 349773045689 ps
CPU time 329.38 seconds
Started Jun 04 01:52:50 PM PDT 24
Finished Jun 04 01:58:21 PM PDT 24
Peak memory 201804 kb
Host smart-2b6da7fb-2e8f-4023-bcee-a2d2d2accdfd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866652472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.2866652472
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.1168800313
Short name T573
Test name
Test status
Simulation time 323843740997 ps
CPU time 204.2 seconds
Started Jun 04 01:52:45 PM PDT 24
Finished Jun 04 01:56:10 PM PDT 24
Peak memory 201812 kb
Host smart-329ab612-14bd-47e9-b274-1f28b62d3ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168800313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.1168800313
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.2808859265
Short name T270
Test name
Test status
Simulation time 491838481038 ps
CPU time 271.86 seconds
Started Jun 04 01:52:44 PM PDT 24
Finished Jun 04 01:57:17 PM PDT 24
Peak memory 201816 kb
Host smart-a79d0d94-1f0a-4707-9b15-ad8548bb00ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808859265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.2808859265
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.649385421
Short name T193
Test name
Test status
Simulation time 489686051588 ps
CPU time 297.49 seconds
Started Jun 04 01:52:44 PM PDT 24
Finished Jun 04 01:57:43 PM PDT 24
Peak memory 201796 kb
Host smart-64d773aa-bdbd-4293-9e07-da26361e5376
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=649385421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt
_fixed.649385421
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.1257062962
Short name T163
Test name
Test status
Simulation time 159158527208 ps
CPU time 100.8 seconds
Started Jun 04 01:52:39 PM PDT 24
Finished Jun 04 01:54:21 PM PDT 24
Peak memory 201800 kb
Host smart-bb54c832-4d55-439a-97ab-a2f2a0790907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257062962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.1257062962
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.1748172523
Short name T448
Test name
Test status
Simulation time 334788216031 ps
CPU time 376.12 seconds
Started Jun 04 01:52:52 PM PDT 24
Finished Jun 04 01:59:10 PM PDT 24
Peak memory 201784 kb
Host smart-8563884d-1741-40c0-8294-c13df27b1369
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748172523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.1748172523
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.167075593
Short name T702
Test name
Test status
Simulation time 203390195641 ps
CPU time 117.1 seconds
Started Jun 04 01:52:51 PM PDT 24
Finished Jun 04 01:54:49 PM PDT 24
Peak memory 201768 kb
Host smart-b62adbf9-3ab4-4432-adf1-0a0e1f5852de
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167075593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.a
dc_ctrl_filters_wakeup_fixed.167075593
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.800218718
Short name T552
Test name
Test status
Simulation time 130170813150 ps
CPU time 444.88 seconds
Started Jun 04 01:52:38 PM PDT 24
Finished Jun 04 02:00:04 PM PDT 24
Peak memory 202156 kb
Host smart-627d2dad-6763-4049-aebd-2d18a04ad7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800218718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.800218718
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.2186889378
Short name T372
Test name
Test status
Simulation time 28972928130 ps
CPU time 70.74 seconds
Started Jun 04 01:52:45 PM PDT 24
Finished Jun 04 01:53:57 PM PDT 24
Peak memory 201636 kb
Host smart-c48d7e3b-cab9-48e1-828f-1d0e16bda148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186889378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.2186889378
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.2031776836
Short name T360
Test name
Test status
Simulation time 3016089261 ps
CPU time 4.08 seconds
Started Jun 04 01:52:41 PM PDT 24
Finished Jun 04 01:52:46 PM PDT 24
Peak memory 201620 kb
Host smart-3140111b-4f68-4194-b459-c0dda7d9539a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031776836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.2031776836
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.2210641789
Short name T384
Test name
Test status
Simulation time 5945844241 ps
CPU time 15.52 seconds
Started Jun 04 01:52:51 PM PDT 24
Finished Jun 04 01:53:08 PM PDT 24
Peak memory 201636 kb
Host smart-9d084ff2-547f-4839-8fdd-39fd56122f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210641789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.2210641789
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.705736173
Short name T760
Test name
Test status
Simulation time 151121553772 ps
CPU time 165.88 seconds
Started Jun 04 01:52:45 PM PDT 24
Finished Jun 04 01:55:32 PM PDT 24
Peak memory 201896 kb
Host smart-03b9c962-08b9-491c-9a91-180e2168f31a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705736173 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.705736173
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.4191456217
Short name T686
Test name
Test status
Simulation time 535364666 ps
CPU time 0.92 seconds
Started Jun 04 01:52:44 PM PDT 24
Finished Jun 04 01:52:46 PM PDT 24
Peak memory 201492 kb
Host smart-a9c4fda1-d5e6-4473-a5af-a5aee0952190
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191456217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.4191456217
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.1544871825
Short name T611
Test name
Test status
Simulation time 176690414420 ps
CPU time 402.95 seconds
Started Jun 04 01:52:45 PM PDT 24
Finished Jun 04 01:59:29 PM PDT 24
Peak memory 201732 kb
Host smart-41d8b3e6-e6c7-4f80-a396-99570d7b3415
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544871825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.1544871825
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.4225406489
Short name T299
Test name
Test status
Simulation time 474503263434 ps
CPU time 538.37 seconds
Started Jun 04 01:52:50 PM PDT 24
Finished Jun 04 02:01:50 PM PDT 24
Peak memory 201796 kb
Host smart-779bded2-2190-44e3-b78f-02f2c9444d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225406489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.4225406489
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.3978655621
Short name T186
Test name
Test status
Simulation time 498176974965 ps
CPU time 288.4 seconds
Started Jun 04 01:52:46 PM PDT 24
Finished Jun 04 01:57:35 PM PDT 24
Peak memory 201808 kb
Host smart-cd6ac432-385b-4835-b948-74f316394391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978655621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.3978655621
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.353175845
Short name T14
Test name
Test status
Simulation time 164310010569 ps
CPU time 99.23 seconds
Started Jun 04 01:52:43 PM PDT 24
Finished Jun 04 01:54:23 PM PDT 24
Peak memory 201824 kb
Host smart-6d33c6c3-71fe-4b97-ade5-6c25a7e1e3e1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=353175845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt
_fixed.353175845
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.1190984293
Short name T675
Test name
Test status
Simulation time 486426738117 ps
CPU time 318.7 seconds
Started Jun 04 01:52:43 PM PDT 24
Finished Jun 04 01:58:02 PM PDT 24
Peak memory 201792 kb
Host smart-6c33fdac-27e1-4111-a271-f829bb5637d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190984293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.1190984293
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.1335713256
Short name T716
Test name
Test status
Simulation time 499912021335 ps
CPU time 1290.64 seconds
Started Jun 04 01:53:01 PM PDT 24
Finished Jun 04 02:14:32 PM PDT 24
Peak memory 201744 kb
Host smart-d05d38ea-fa09-4ec1-9102-fd01733b115e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335713256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.1335713256
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.4293687693
Short name T105
Test name
Test status
Simulation time 504185680559 ps
CPU time 563.62 seconds
Started Jun 04 01:52:45 PM PDT 24
Finished Jun 04 02:02:09 PM PDT 24
Peak memory 201912 kb
Host smart-d0241f98-e77f-45a9-a83c-16a9e6a59d5d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293687693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.4293687693
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.3030591827
Short name T570
Test name
Test status
Simulation time 201285549169 ps
CPU time 453.38 seconds
Started Jun 04 01:52:43 PM PDT 24
Finished Jun 04 02:00:17 PM PDT 24
Peak memory 201804 kb
Host smart-62fb5fd8-e970-415c-bcb0-a5a7b3dc1c50
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030591827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.3030591827
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.2728240022
Short name T747
Test name
Test status
Simulation time 36095435601 ps
CPU time 23.61 seconds
Started Jun 04 01:52:43 PM PDT 24
Finished Jun 04 01:53:08 PM PDT 24
Peak memory 201536 kb
Host smart-b5e2bb03-7ec6-451a-b8b4-ba97957f8ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728240022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.2728240022
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.2460156217
Short name T391
Test name
Test status
Simulation time 5024265077 ps
CPU time 3.1 seconds
Started Jun 04 01:52:53 PM PDT 24
Finished Jun 04 01:52:58 PM PDT 24
Peak memory 201592 kb
Host smart-27a3b0c1-5998-4cdc-8941-c0e5ecf274a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460156217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.2460156217
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.8739947
Short name T762
Test name
Test status
Simulation time 5960163616 ps
CPU time 8.89 seconds
Started Jun 04 01:52:54 PM PDT 24
Finished Jun 04 01:53:05 PM PDT 24
Peak memory 201608 kb
Host smart-1df51063-690b-41ab-87ea-da56156c9cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8739947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.8739947
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.2129600482
Short name T224
Test name
Test status
Simulation time 310997354408 ps
CPU time 699.91 seconds
Started Jun 04 01:52:49 PM PDT 24
Finished Jun 04 02:04:29 PM PDT 24
Peak memory 210324 kb
Host smart-fd17bd85-b537-4cb4-a522-f40f775b402c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129600482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
2129600482
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.1965239386
Short name T780
Test name
Test status
Simulation time 245948828881 ps
CPU time 54.77 seconds
Started Jun 04 01:52:53 PM PDT 24
Finished Jun 04 01:53:49 PM PDT 24
Peak memory 210080 kb
Host smart-4b9f270f-5ff5-4f7a-bbce-77c86943b1b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965239386 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.1965239386
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.2881879283
Short name T553
Test name
Test status
Simulation time 403755302 ps
CPU time 0.75 seconds
Started Jun 04 01:52:45 PM PDT 24
Finished Jun 04 01:52:47 PM PDT 24
Peak memory 201480 kb
Host smart-e429a1be-8eca-4f6c-bfa7-050d938d55f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881879283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.2881879283
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.515595416
Short name T93
Test name
Test status
Simulation time 191740516662 ps
CPU time 258.77 seconds
Started Jun 04 01:52:46 PM PDT 24
Finished Jun 04 01:57:06 PM PDT 24
Peak memory 201884 kb
Host smart-6703206f-6d13-49a2-8401-3fed0b61d5c3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515595416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gatin
g.515595416
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.1156236652
Short name T575
Test name
Test status
Simulation time 330876889220 ps
CPU time 209.65 seconds
Started Jun 04 01:53:02 PM PDT 24
Finished Jun 04 01:56:32 PM PDT 24
Peak memory 201868 kb
Host smart-3af0ca9c-567d-4d5e-b8ae-3c07e6524d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156236652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.1156236652
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.1871255961
Short name T463
Test name
Test status
Simulation time 489516127403 ps
CPU time 1196.62 seconds
Started Jun 04 01:52:51 PM PDT 24
Finished Jun 04 02:12:50 PM PDT 24
Peak memory 201796 kb
Host smart-e2433e39-2d90-4ee7-b050-fa6d7ddf9ab6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871255961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.1871255961
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.1180159281
Short name T767
Test name
Test status
Simulation time 491916615754 ps
CPU time 1181.15 seconds
Started Jun 04 01:52:50 PM PDT 24
Finished Jun 04 02:12:32 PM PDT 24
Peak memory 201836 kb
Host smart-0edfa912-bc3d-4cc7-8c4f-fd0c80fb1ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180159281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.1180159281
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.674104103
Short name T148
Test name
Test status
Simulation time 325311815638 ps
CPU time 185.72 seconds
Started Jun 04 01:52:40 PM PDT 24
Finished Jun 04 01:55:46 PM PDT 24
Peak memory 201820 kb
Host smart-788fe5cc-7cf6-405b-b2e0-036c2891472b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=674104103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixed
.674104103
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.3282294035
Short name T701
Test name
Test status
Simulation time 592238313182 ps
CPU time 1517.06 seconds
Started Jun 04 01:52:52 PM PDT 24
Finished Jun 04 02:18:11 PM PDT 24
Peak memory 201780 kb
Host smart-07544c39-295e-4d6b-ac75-881f8d0075e1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282294035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.3282294035
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.549889695
Short name T382
Test name
Test status
Simulation time 85694087907 ps
CPU time 284.13 seconds
Started Jun 04 01:52:47 PM PDT 24
Finished Jun 04 01:57:32 PM PDT 24
Peak memory 202016 kb
Host smart-8d9fca69-6bf2-483f-b0e2-65529b02324f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549889695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.549889695
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.2424084623
Short name T757
Test name
Test status
Simulation time 42959918377 ps
CPU time 42.39 seconds
Started Jun 04 01:52:51 PM PDT 24
Finished Jun 04 01:53:35 PM PDT 24
Peak memory 201596 kb
Host smart-58e3fd04-3515-49b2-93ba-0bdf03d0adba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424084623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.2424084623
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.752230044
Short name T462
Test name
Test status
Simulation time 5033635665 ps
CPU time 6.66 seconds
Started Jun 04 01:52:43 PM PDT 24
Finished Jun 04 01:52:50 PM PDT 24
Peak memory 201156 kb
Host smart-7f295225-6bd1-4093-90ab-b40667104f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752230044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.752230044
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.2919426795
Short name T417
Test name
Test status
Simulation time 5844094326 ps
CPU time 14.23 seconds
Started Jun 04 01:52:50 PM PDT 24
Finished Jun 04 01:53:06 PM PDT 24
Peak memory 201632 kb
Host smart-dbf52ccf-5b1a-4a09-8ad6-cc78c7413612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919426795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.2919426795
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.3188918856
Short name T166
Test name
Test status
Simulation time 438331293464 ps
CPU time 892.85 seconds
Started Jun 04 01:52:53 PM PDT 24
Finished Jun 04 02:07:47 PM PDT 24
Peak memory 210344 kb
Host smart-3e5f29f1-5d72-4a9e-a017-ecc5dd9a2d46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188918856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
3188918856
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.2705355665
Short name T215
Test name
Test status
Simulation time 39999027701 ps
CPU time 167.66 seconds
Started Jun 04 01:52:52 PM PDT 24
Finished Jun 04 01:55:41 PM PDT 24
Peak memory 218152 kb
Host smart-37519b7a-cf2a-46ad-b8d8-aea791a86fcf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705355665 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.2705355665
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.3234437905
Short name T475
Test name
Test status
Simulation time 532581100 ps
CPU time 1.72 seconds
Started Jun 04 01:53:01 PM PDT 24
Finished Jun 04 01:53:04 PM PDT 24
Peak memory 201504 kb
Host smart-df903e25-4a3b-41c7-836e-fb0be9473080
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234437905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.3234437905
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.3746081866
Short name T290
Test name
Test status
Simulation time 165854506075 ps
CPU time 323.86 seconds
Started Jun 04 01:52:54 PM PDT 24
Finished Jun 04 01:58:19 PM PDT 24
Peak memory 201756 kb
Host smart-9c1cc430-0d0c-4026-971b-032b6bec1209
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746081866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.3746081866
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.833877043
Short name T792
Test name
Test status
Simulation time 326865739770 ps
CPU time 702.14 seconds
Started Jun 04 01:53:01 PM PDT 24
Finished Jun 04 02:04:44 PM PDT 24
Peak memory 201800 kb
Host smart-fd66f3e9-32be-44ff-aecb-4c444bf22f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833877043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.833877043
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.1405214250
Short name T604
Test name
Test status
Simulation time 325725730531 ps
CPU time 142.67 seconds
Started Jun 04 01:53:01 PM PDT 24
Finished Jun 04 01:55:25 PM PDT 24
Peak memory 201872 kb
Host smart-d6568d56-c0e2-430c-9a9f-15c497d5b18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405214250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.1405214250
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.1968847808
Short name T420
Test name
Test status
Simulation time 491021219233 ps
CPU time 270.87 seconds
Started Jun 04 01:53:02 PM PDT 24
Finished Jun 04 01:57:34 PM PDT 24
Peak memory 201756 kb
Host smart-b4c1d9ac-4c2d-4b8e-a957-79eba0172da7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968847808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.1968847808
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.3694676856
Short name T519
Test name
Test status
Simulation time 167767500958 ps
CPU time 411.2 seconds
Started Jun 04 01:52:44 PM PDT 24
Finished Jun 04 01:59:36 PM PDT 24
Peak memory 201812 kb
Host smart-02746695-e977-477f-98c7-4fb9990ed2c1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694676856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.3694676856
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.14862317
Short name T633
Test name
Test status
Simulation time 558596242707 ps
CPU time 681.63 seconds
Started Jun 04 01:52:59 PM PDT 24
Finished Jun 04 02:04:21 PM PDT 24
Peak memory 201872 kb
Host smart-4c1d8ed1-1061-4984-8ad6-3df7f3eb4e20
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14862317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_wa
keup.14862317
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.146975071
Short name T377
Test name
Test status
Simulation time 606581579306 ps
CPU time 328.5 seconds
Started Jun 04 01:52:57 PM PDT 24
Finished Jun 04 01:58:27 PM PDT 24
Peak memory 201764 kb
Host smart-61ca4d56-53e2-4533-adea-eebed9b0c77b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146975071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.a
dc_ctrl_filters_wakeup_fixed.146975071
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.3410959660
Short name T625
Test name
Test status
Simulation time 109225956414 ps
CPU time 573.31 seconds
Started Jun 04 01:53:06 PM PDT 24
Finished Jun 04 02:02:40 PM PDT 24
Peak memory 202112 kb
Host smart-215cb2c7-2827-4761-a28d-86613af870f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410959660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.3410959660
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.3829321117
Short name T638
Test name
Test status
Simulation time 43379073759 ps
CPU time 26.73 seconds
Started Jun 04 01:52:54 PM PDT 24
Finished Jun 04 01:53:22 PM PDT 24
Peak memory 201564 kb
Host smart-5dbc3c07-1952-49ff-a156-c8e194e16aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829321117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.3829321117
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.938956928
Short name T431
Test name
Test status
Simulation time 3162570374 ps
CPU time 2.26 seconds
Started Jun 04 01:52:52 PM PDT 24
Finished Jun 04 01:52:56 PM PDT 24
Peak memory 201624 kb
Host smart-db67b433-735f-4f7f-8e27-c604e18fb905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938956928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.938956928
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.2038192301
Short name T459
Test name
Test status
Simulation time 5921441735 ps
CPU time 4.68 seconds
Started Jun 04 01:52:50 PM PDT 24
Finished Jun 04 01:52:57 PM PDT 24
Peak memory 201636 kb
Host smart-20e135e0-a24a-4f81-b9e7-6ecb86f87524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038192301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.2038192301
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.2473898366
Short name T23
Test name
Test status
Simulation time 109956325455 ps
CPU time 262.88 seconds
Started Jun 04 01:52:53 PM PDT 24
Finished Jun 04 01:57:17 PM PDT 24
Peak memory 210404 kb
Host smart-c38ddb2f-dcaf-4f21-90f2-93055f5b8c3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473898366 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.2473898366
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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