Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6961	1			T2	11		T4	20		T5	20
testmodes[AdcCtrlTestmodeNormal]	5316	1			T2	9		T6	57		T7	2
testmodes[AdcCtrlTestmodeLowpower]	5842	1			T1	3		T3	2		T6	44
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3813	1			T2	5		T4	19		T5	19
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1689	1			T2	5		T6	19		T56	5
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1345	1			T6	20		T42	13		T51	16
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1680	1			T2	5		T6	21		T56	5
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1917	1			T2	4		T6	22		T7	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1377	1			T6	13		T42	12		T51	10
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1347	1			T6	18		T42	16		T51	11
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1372	1			T6	15		T42	9		T15	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2881	1			T1	2		T3	1		T6	11