Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26511

1

T1

37

T2

20

T3

39

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22705

1

T2

20

T3

22

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3806

1

T1

37

T3

17

T6

26

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20260

1

T1

27

T2

20

T3

39

auto[1]

6251

1

T1

10

T6

26

T7

40

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22444

1

T1

37

T2

20

T3

39

auto[1]

4067

1

T6

15

T7

15

T11

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	17	1			T162	17		-	-		-	-
values[0]	58	1			T30	25		T178	14		T157	9
values[1]	855	1			T48	24		T30	21		T33	1
values[2]	3064	1			T7	24		T8	3		T11	11
values[3]	636	1			T1	24		T3	22		T154	1
values[4]	578	1			T227	1		T28	7		T228	16
values[5]	646	1			T156	11		T157	1		T229	45
values[6]	738	1			T3	17		T6	26		T13	1
values[7]	700	1			T161	1		T154	1		T48	27
values[8]	637	1			T7	16		T13	1		T28	1
values[9]	1372	1			T1	13		T15	28		T166	3
minimum	17210	1			T2	20		T4	20		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1059	1			T48	24		T30	26		T34	29
values[1]	3193	1			T1	14		T7	24		T8	3
values[2]	509	1			T1	10		T3	22		T12	12
values[3]	624	1			T228	16		T156	11		T157	1
values[4]	599	1			T154	1		T229	45		T165	5
values[5]	769	1			T3	17		T6	26		T13	1
values[6]	716	1			T154	1		T48	27		T61	14
values[7]	662	1			T7	16		T13	1		T28	1
values[8]	872	1			T1	13		T15	10		T166	3
values[9]	288	1			T15	18		T158	22		T44	2
minimum	17220	1			T2	20		T4	20		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22186

1

T1

3

T2

20

T3

2

auto[1]

4325

1

T1

34

T3

37

T6

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T48	14		T34	17		T204	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T30	15		T178	8		T186	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1522	1			T8	3		T11	1		T14	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	390	1			T1	14		T7	12		T161	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T3	22		T151	16		T45	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T1	10		T12	12		T227	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T228	8		T156	11		T172	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T157	1		T164	17		T230	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T229	25		T165	1		T107	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T154	1		T173	15		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T13	1		T204	23		T171	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T3	17		T6	12		T161	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T48	23		T17	3		T36	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T154	1		T61	9		T231	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T28	1		T170	1		T163	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T7	13		T13	1		T162	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T16	1		T155	17		T232	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T1	13		T15	6		T166	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T188	10		T189	2		T233	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T15	10		T158	11		T44	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17083	1			T2	20		T4	20		T5	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T48	10		T34	12		T234	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T30	11		T178	6		T186	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	956	1			T11	10		T14	8		T152	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T7	12		T16	1		T30	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T151	10		T45	1		T175	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T156	5		T40	3		T223	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T228	8		T43	5		T44	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T164	6		T230	1		T235	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T229	20		T165	4		T181	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T173	13		T89	2		T93	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T173	15		T168	14		T236	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T6	14		T151	16		T117	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T48	4		T36	16		T188	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T61	5		T237	1		T124	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T238	10		T239	12		T184	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T7	3		T162	7		T158	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T155	30		T229	2		T206	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T15	4		T166	2		T61	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T188	10		T194	16		T197	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T15	8		T158	11		T44	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T6	1		T16	1		T28	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T162	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T30	14		T178	8		T157	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T48	14		T33	1		T34	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T30	16		T186	10		T220	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1514	1			T8	3		T11	1		T14	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T7	12		T12	12		T161	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T3	22		T154	1		T89	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T1	24		T156	6		T40	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T228	8		T151	16		T172	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T227	1		T28	7		T164	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T156	11		T229	25		T165	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T157	1		T173	15		T215	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T13	1		T171	1		T168	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T3	17		T6	12		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T48	23		T204	23		T100	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T161	1		T154	1		T61	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T28	1		T170	1		T36	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T7	13		T13	1		T162	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	397	1			T16	1		T155	17		T232	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T1	13		T15	16		T166	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17081	1			T2	20		T4	20		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T162	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T30	11		T178	6		T157	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T48	10		T34	12		T171	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T30	5		T186	10		T223	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	951	1			T11	10		T14	8		T152	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T7	12		T16	1		T151	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T192	8		T235	9		T240	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T156	5		T40	3		T223	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T228	8		T151	10		T43	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T164	6		T241	12		T242	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T229	20		T165	4		T181	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T173	13		T243	1		T230	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T168	14		T236	8		T182	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T6	14		T151	16		T124	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T48	4		T173	15		T188	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T61	5		T47	1		T169	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T36	16		T238	10		T239	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T7	3		T162	7		T237	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	341	1			T155	30		T229	2		T206	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T15	12		T166	2		T61	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T6	1		T16	1		T28	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T48	11		T34	13		T204	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T30	13		T178	7		T186	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1294	1			T8	3		T11	11		T14	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	380	1			T1	1		T7	13		T161	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T3	1		T151	11		T45	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T1	1		T12	1		T227	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T228	9		T156	1		T172	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T157	1		T164	7		T230	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T229	22		T165	5		T107	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T154	1		T173	14		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T13	1		T204	1		T171	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T3	1		T6	15		T161	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T48	5		T17	3		T36	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T154	1		T61	6		T231	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T28	1		T170	1		T163	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T7	4		T13	1		T162	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T16	1		T155	32		T232	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T1	1		T15	5		T166	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T188	11		T189	1		T233	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T15	9		T158	12		T44	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17220	1			T2	20		T4	20		T5	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T48	13		T34	16		T204	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T30	13		T178	7		T186	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1184	1			T32	17		T34	4		T164	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T1	13		T7	11		T30	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T3	21		T151	15		T45	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T1	9		T12	11		T28	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T228	7		T156	10		T43	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T164	16		T242	12		T244	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T229	23		T107	16		T181	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T173	14		T215	8		T93	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T204	22		T173	14		T168	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T3	16		T6	11		T151	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T48	22		T188	5		T169	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T61	8		T231	6		T237	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T183	11		T238	7		T239	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T7	12		T162	8		T158	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T155	15		T232	9		T229	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T1	12		T15	5		T61	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T188	9		T189	1		T194	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T15	9		T158	10		T46	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T162	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T30	12		T178	7		T157	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T48	11		T33	1		T34	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T30	7		T186	11		T220	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1292	1			T8	3		T11	11		T14	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	338	1			T7	13		T12	1		T161	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T3	1		T154	1		T89	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T1	2		T156	6		T40	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T228	9		T151	11		T172	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T227	1		T28	1		T164	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T156	1		T229	22		T165	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T157	1		T173	14		T215	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T13	1		T171	1		T168	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T3	1		T6	15		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T48	5		T204	1		T100	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T161	1		T154	1		T61	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T28	1		T170	1		T36	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T7	4		T13	1		T162	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	417	1			T16	1		T155	32		T232	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	367	1			T1	1		T15	14		T166	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17210	1			T2	20		T4	20		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T162	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T30	13		T178	7		T157	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T48	13		T34	16		T164	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T30	14		T186	9		T245	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1173	1			T32	17		T34	4		T204	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T7	11		T12	11		T151	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T3	21		T192	8		T240	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T1	22		T156	5		T40	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T228	7		T151	15		T43	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T28	6		T164	16		T88	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T156	10		T229	23		T107	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T173	14		T215	8		T243	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T168	11		T108	5		T191	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T3	16		T6	11		T151	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T48	22		T204	22		T173	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T61	8		T231	6		T47	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T169	7		T246	13		T183	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T7	12		T162	8		T237	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	321	1			T155	15		T232	9		T229	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T1	12		T15	14		T61	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22186

1

T1

3

T2

20

T3

2

auto[1]

auto[0]

4325

1

T1

34

T3

37

T6

11

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26511

1

T1

37

T2

20

T3

39

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22851

1

T1

10

T2

20

T3

17

auto[ADC_CTRL_FILTER_COND_OUT]

3660

1

T1

27

T3

22

T7

40

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20128

1

T1

10

T2

20

T3

39

auto[1]

6383

1

T1

27

T6

3

T7

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22444

1

T1

37

T2

20

T3

39

auto[1]

4067

1

T6

15

T7

15

T11

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	473	1			T6	3		T42	1		T51	2
values[0]	21	1			T247	1		T248	20		-	-
values[1]	696	1			T231	7		T186	20		T155	8
values[2]	2916	1			T1	13		T7	24		T8	3
values[3]	725	1			T1	14		T15	18		T227	1
values[4]	760	1			T6	26		T166	3		T28	8
values[5]	601	1			T3	22		T16	1		T237	14
values[6]	901	1			T3	17		T154	2		T30	25
values[7]	717	1			T1	10		T12	12		T48	27
values[8]	578	1			T161	1		T186	2		T155	13
values[9]	1370	1			T7	16		T13	2		T161	1
minimum	16753	1			T2	20		T4	20		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	855	1			T7	24		T178	14		T231	7
values[1]	3000	1			T1	27		T8	3		T11	11
values[2]	730	1			T6	26		T15	18		T48	24
values[3]	749	1			T166	3		T16	1		T28	7
values[4]	713	1			T3	22		T30	25		T157	9
values[5]	804	1			T1	10		T3	17		T12	12
values[6]	615	1			T48	27		T16	4		T61	40
values[7]	763	1			T7	16		T161	2		T170	1
values[8]	911	1			T13	2		T162	17		T151	26
values[9]	161	1			T154	1		T228	16		T160	1
minimum	17210	1			T2	20		T4	20		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22186

1

T1

3

T2

20

T3

2

auto[1]

4325

1

T1

34

T3

37

T6

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T178	8		T231	7		T171	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T7	12		T186	10		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1504	1			T8	3		T11	1		T14	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T1	27		T15	6		T227	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T6	12		T15	10		T48	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T186	3		T45	5		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T166	1		T16	1		T28	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T117	12		T167	7		T188	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T30	14		T157	3		T100	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T3	22		T172	16		T206	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	343	1			T1	10		T3	17		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T12	12		T154	1		T164	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T48	23		T16	3		T61	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T61	11		T186	1		T158	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T161	1		T162	9		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T7	13		T161	1		T170	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T13	1		T162	10		T43	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T13	1		T151	16		T40	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T154	1		T228	8		T160	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T249	16		T194	14		T250	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17081	1			T2	20		T4	20		T5	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T178	6		T171	8		T165	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T7	12		T186	10		T155	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	993	1			T11	10		T14	8		T152	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T15	4		T17	3		T18	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T6	14		T15	8		T48	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T186	12		T45	1		T251	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T166	2		T237	1		T245	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T117	12		T167	6		T188	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T30	11		T157	6		T102	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T206	18		T223	4		T93	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T151	12		T43	5		T252	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T164	6		T102	8		T242	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T48	4		T16	1		T61	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T61	15		T186	1		T158	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T162	7		T155	12		T156	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T7	3		T164	14		T124	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T162	7		T43	4		T181	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T151	10		T40	3		T173	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T228	8		T253	11		T254	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T194	9		T250	9		T20	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T6	1		T16	1		T28	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	458	1			T6	3		T42	1		T51	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T255	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T247	1		T248	10		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T231	7		T171	1		T165	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T186	10		T155	1		T157	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1559	1			T8	3		T11	1		T14	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T1	13		T7	12		T15	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T15	10		T33	1		T34	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T1	14		T227	1		T204	23
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T6	12		T166	1		T28	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T186	3		T45	5		T117	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T16	1		T237	13		T100	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T3	22		T167	7		T188	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	351	1			T3	17		T154	1		T30	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T154	1		T61	11		T164	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T1	10		T48	23		T16	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T12	12		T158	11		T164	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T155	1		T158	17		T171	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T161	1		T186	1		T100	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	315	1			T13	1		T161	1		T154	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	449	1			T7	13		T13	1		T170	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16624	1			T2	20		T4	20		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T255	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T248	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T171	8		T165	4		T40	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T186	10		T155	7		T229	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	983	1			T11	10		T14	8		T152	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T7	12		T15	4		T223	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T15	8		T34	12		T151	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T17	3		T18	9		T182	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T6	14		T166	2		T157	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T186	12		T45	1		T117	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T237	1		T102	13		T44	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T167	6		T188	12		T223	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T30	11		T43	5		T252	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T61	15		T164	6		T206	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T48	4		T16	1		T61	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T158	11		T164	5		T102	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T155	12		T158	16		T256	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T186	1		T234	4		T169	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T228	8		T162	14		T156	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	353	1			T7	3		T151	10		T164	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T6	1		T16	1		T28	3