Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26511

1

T1

37

T2

20

T3

39

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22664

1

T1

37

T2

20

T3

17

auto[ADC_CTRL_FILTER_COND_OUT]

3847

1

T3

22

T6

26

T7

24

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20042

1

T1

37

T2

20

T3

17

auto[1]

6469

1

T3

22

T7

24

T8

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22444

1

T1

37

T2

20

T3

39

auto[1]

4067

1

T6

15

T7

15

T11

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	272	1			T1	24		T33	1		T17	9
values[0]	26	1			T156	11		T218	15		-	-
values[1]	979	1			T3	22		T12	12		T61	26
values[2]	652	1			T7	16		T15	10		T154	1
values[3]	792	1			T7	24		T48	27		T34	8
values[4]	659	1			T161	1		T48	24		T28	8
values[5]	764	1			T6	26		T15	18		T30	1
values[6]	626	1			T161	1		T154	1		T16	4
values[7]	543	1			T1	13		T227	1		T16	1
values[8]	615	1			T166	3		T186	20		T157	1
values[9]	3373	1			T3	17		T8	3		T11	11
minimum	17210	1			T2	20		T4	20		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	936	1			T3	22		T12	12		T154	1
values[1]	598	1			T7	16		T15	10		T34	8
values[2]	732	1			T161	1		T48	27		T156	11
values[3]	727	1			T7	24		T48	24		T28	8
values[4]	693	1			T6	26		T15	18		T154	1
values[5]	547	1			T161	1		T16	4		T30	25
values[6]	2864	1			T1	13		T8	3		T11	11
values[7]	587	1			T166	3		T30	20		T157	1
values[8]	1019	1			T1	10		T3	17		T13	1
values[9]	282	1			T1	14		T13	1		T34	29
minimum	17526	1			T2	20		T4	20		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22186

1

T1

3

T2

20

T3

2

auto[1]

4325

1

T1

34

T3

37

T6

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T12	12		T154	1		T151	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T3	22		T61	11		T151	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T7	13		T34	5		T228	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T15	6		T158	12		T271	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T161	1		T164	8		T100	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T48	23		T156	6		T43	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T186	1		T204	23		T171	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T7	12		T48	14		T28	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T154	1		T61	9		T162	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T6	12		T15	10		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T16	3		T155	1		T163	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T161	1		T30	14		T40	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1552	1			T1	13		T8	3		T11	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T16	1		T204	9		T158	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T166	1		T229	18		T164	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T30	15		T157	1		T229	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T1	10		T3	17		T178	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	391	1			T13	1		T154	1		T33	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T1	14		T13	1		T18	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T34	17		T234	5		T315	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17183	1			T2	20		T4	20		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T156	11		T174	10		T293	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T151	12		T173	13		T188	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T61	15		T151	10		T155	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T7	3		T34	3		T228	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T15	4		T158	11		T223	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T164	5		T44	1		T182	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T48	4		T156	5		T43	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T186	1		T238	11		T191	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T7	12		T48	10		T155	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T61	5		T162	7		T167	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T6	14		T15	8		T102	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T16	1		T155	7		T40	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T30	11		T43	5		T266	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1005	1			T11	10		T14	8		T152	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T158	16		T260	14		T240	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T166	2		T229	16		T164	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T30	5		T229	6		T44	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T178	6		T169	6		T236	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T162	7		T151	16		T173	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T18	9		T262	13		T316	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T34	12		T234	4		T317	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T6	1		T16	1		T28	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T174	9		T293	8		T318	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T1	24		T18	13		T262	16
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T33	1		T17	6		T159	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T218	15		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T156	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T12	12		T151	3		T231	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T3	22		T61	11		T155	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T7	13		T154	1		T170	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T15	6		T151	16		T158	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T34	5		T228	8		T157	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T7	12		T48	23		T156	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T161	1		T204	23		T171	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T48	14		T28	8		T155	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T61	9		T186	1		T172	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T6	12		T15	10		T30	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T154	1		T16	3		T162	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T161	1		T30	14		T40	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T1	13		T227	1		T165	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T16	1		T204	9		T158	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T166	1		T186	10		T229	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T157	1		T44	1		T47	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1561	1			T3	17		T8	3		T11	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	455	1			T13	1		T154	1		T30	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17081	1			T2	20		T4	20		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T18	9		T262	13		T316	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T17	3		T268	5		T319	26
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T151	12		T186	12		T188	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T61	15		T155	18		T164	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T7	3		T156	10		T102	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T15	4		T151	10		T158	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T34	3		T228	8		T157	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T7	12		T48	4		T156	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T238	11		T191	4		T265	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T48	10		T155	12		T237	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T61	5		T186	1		T167	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T6	14		T15	8		T102	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T16	1		T162	7		T155	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T30	11		T43	5		T266	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T165	4		T40	9		T168	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T158	16		T260	14		T240	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T166	2		T186	10		T229	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T44	1		T47	1		T89	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1018	1			T11	10		T14	8		T152	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T30	5		T34	12		T162	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T6	1		T16	1		T28	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T12	1		T154	1		T151	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T3	1		T61	16		T151	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T7	4		T34	4		T228	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T15	5		T158	12		T271	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T161	1		T164	6		T100	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T48	5		T156	6		T43	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T186	2		T204	1		T171	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T7	13		T48	11		T28	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T154	1		T61	6		T162	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T6	15		T15	9		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T16	4		T155	8		T163	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T161	1		T30	12		T40	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1340	1			T1	1		T8	3		T11	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T16	1		T204	1		T158	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T166	3		T229	18		T164	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T30	6		T157	1		T229	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T1	1		T3	1		T178	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	342	1			T13	1		T154	1		T33	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T1	1		T13	1		T18	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T34	13		T234	5		T315	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17291	1			T2	20		T4	20		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T156	1		T174	10		T293	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T12	11		T151	2		T231	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T3	21		T61	10		T151	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T7	12		T34	4		T228	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T15	5		T158	11		T176	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T164	7		T107	16		T288	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T48	22		T156	5		T43	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T204	22		T215	8		T95	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T7	11		T48	13		T28	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T61	8		T162	8		T172	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T6	11		T15	9		T102	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T40	2		T90	10		T240	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T30	13		T43	5		T215	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1217	1			T1	12		T32	17		T186	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T204	8		T158	14		T215	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T229	16		T164	15		T167	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T30	14		T229	9		T47	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T1	9		T3	16		T178	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T162	9		T151	14		T173	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T1	13		T18	8		T262	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T34	16		T234	4		T277	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T186	2		T189	1		T320	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T156	10		T174	9		T293	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T1	2		T18	14		T262	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T33	1		T17	6		T159	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T218	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T156	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T12	1		T151	13		T231	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T3	1		T61	16		T155	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T7	4		T154	1		T170	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T15	5		T151	11		T158	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T34	4		T228	9		T157	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T7	13		T48	5		T156	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T161	1		T204	1		T171	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T48	11		T28	2		T155	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T61	6		T186	2		T172	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T6	15		T15	9		T30	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T154	1		T16	4		T162	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T161	1		T30	12		T40	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	1		T227	1		T165	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T16	1		T204	1		T158	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T166	3		T186	11		T229	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T157	1		T44	2		T47	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1355	1			T3	1		T8	3		T11	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	407	1			T13	1		T154	1		T30	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17210	1			T2	20		T4	20		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T1	22		T18	8		T262	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T17	3		T189	1		T268	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T218	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T156	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T12	11		T151	2		T231	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T3	21		T61	10		T155	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T7	12		T156	13		T232	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T15	5		T151	15		T158	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T34	4		T228	7		T157	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T7	11		T48	22		T156	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T204	22		T215	8		T95	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T48	13		T28	6		T237	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T61	8		T172	14		T175	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T6	11		T15	9		T102	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T162	8		T225	8		T90	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T30	13		T43	5		T215	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T1	12		T40	7		T168	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T204	8		T158	14		T169	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T186	9		T229	16		T167	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T47	2		T215	5		T184	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1224	1			T3	16		T32	17		T178	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	387	1			T30	14		T34	16		T162	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22186

1

T1

3

T2

20

T3

2

auto[1]

auto[0]

4325

1

T1

34

T3

37

T6

11