Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26511

1

T1

37

T2

20

T3

39

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22590

1

T1

23

T2

20

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3921

1

T1

14

T3

39

T6

26

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20689

1

T1

24

T2

20

T3

22

auto[1]

5822

1

T1

13

T3

17

T6

26

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22444

1

T1

37

T2

20

T3

39

auto[1]

4067

1

T6

15

T7

15

T11

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	75	1			T40	1		T262	29		T321	20
values[0]	86	1			T231	7		T322	25		T323	14
values[1]	559	1			T15	10		T154	1		T16	5
values[2]	823	1			T1	10		T3	22		T15	18
values[3]	768	1			T166	3		T228	16		T186	15
values[4]	2892	1			T8	3		T11	11		T14	9
values[5]	619	1			T1	13		T12	12		T161	1
values[6]	738	1			T7	16		T161	1		T154	1
values[7]	709	1			T6	26		T7	24		T48	24
values[8]	698	1			T154	1		T34	29		T186	2
values[9]	1334	1			T1	14		T3	17		T13	2
minimum	17210	1			T2	20		T4	20		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	731	1			T15	10		T154	1		T16	5
values[1]	835	1			T1	10		T3	22		T15	18
values[2]	822	1			T30	25		T228	16		T155	34
values[3]	2793	1			T8	3		T11	11		T14	9
values[4]	726	1			T7	16		T12	12		T161	2
values[5]	787	1			T1	13		T7	24		T154	1
values[6]	561	1			T48	24		T162	16		T157	9
values[7]	659	1			T6	26		T154	1		T186	22
values[8]	1011	1			T13	2		T28	1		T34	37
values[9]	352	1			T1	14		T3	17		T155	8
minimum	17234	1			T2	20		T4	20		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22186

1

T1

3

T2

20

T3

2

auto[1]

4325

1

T1

34

T3

37

T6

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T16	3		T178	8		T204	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T15	6		T154	1		T16	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T1	10		T28	7		T61	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T3	22		T15	10		T166	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T155	16		T164	16		T43	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T30	14		T228	8		T232	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1585	1			T8	3		T11	1		T14	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T48	23		T236	1		T190	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T7	13		T161	1		T170	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T12	12		T161	1		T30	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T1	13		T7	12		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T151	16		T156	6		T234	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T48	14		T157	3		T181	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T162	9		T172	1		T40	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T154	1		T186	11		T165	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T6	12		T181	15		T45	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T13	2		T34	22		T151	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T28	1		T61	9		T160	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T155	1		T88	13		T92	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T1	14		T3	17		T158	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17094	1			T2	20		T4	20		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T324	1		T325	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T16	1		T178	6		T174	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T15	4		T173	15		T117	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T61	15		T186	12		T229	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T15	8		T166	2		T155	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T155	18		T164	14		T43	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T30	11		T228	8		T229	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1006	1			T11	10		T14	8		T152	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T48	4		T236	8		T266	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T7	3		T171	8		T40	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T30	5		T162	7		T38	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T7	12		T18	9		T169	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T151	10		T156	5		T234	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T48	10		T157	6		T181	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T162	7		T40	3		T102	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T186	11		T165	4		T44	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T6	14		T181	19		T45	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T34	15		T151	28		T237	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T61	5		T47	1		T236	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T155	7		T184	18		T326	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T158	11		T164	5		T251	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T6	1		T16	1		T28	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T325	9		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T40	1		T262	16		T321	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T185	3		T299	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T327	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T231	7		T322	15		T323	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T16	3		T178	8		T204	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T15	6		T154	1		T16	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T1	10		T28	7		T61	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T3	22		T15	10		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T186	3		T163	1		T158	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T166	1		T228	8		T232	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1603	1			T8	3		T11	1		T14	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T48	23		T30	14		T43	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T1	13		T30	1		T40	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T12	12		T161	1		T215	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T7	13		T161	1		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T30	15		T162	10		T156	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T7	12		T48	14		T33	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T6	12		T162	9		T151	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T154	1		T34	17		T186	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T40	10		T43	6		T181	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T13	2		T34	5		T151	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	419	1			T1	14		T3	17		T28	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17081	1			T2	20		T4	20		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T262	13		T321	11		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T185	1		T299	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T322	10		T323	13		T328	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T16	1		T178	6		T168	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T15	4		T173	15		T117	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T61	15		T229	2		T164	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T15	8		T155	12		T156	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T186	12		T158	5		T164	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T166	2		T228	8		T229	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1027	1			T11	10		T14	8		T152	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T48	4		T30	11		T266	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T40	6		T44	1		T188	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T236	8		T230	1		T312	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T7	3		T171	8		T169	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T30	5		T162	7		T175	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T7	12		T48	10		T18	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T6	14		T162	7		T151	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T34	12		T186	1		T157	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T40	3		T43	5		T181	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T34	3		T151	28		T186	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	334	1			T61	5		T158	11		T164	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T6	1		T16	1		T28	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T16	4		T178	7		T204	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T15	5		T154	1		T16	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T1	1		T28	1		T61	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T3	1		T15	9		T166	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T155	19		T164	15		T43	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T30	12		T228	9		T232	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1352	1			T8	3		T11	11		T14	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T48	5		T236	9		T190	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T7	4		T161	1		T170	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T12	1		T161	1		T30	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T1	1		T7	13		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T151	11		T156	6		T234	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T48	11		T157	7		T181	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T162	8		T172	1		T40	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T154	1		T186	13		T165	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T6	15		T181	20		T45	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T13	2		T34	17		T151	30
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T28	1		T61	6		T160	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T155	8		T88	1		T92	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T1	1		T3	1		T158	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17213	1			T2	20		T4	20		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T324	1		T325	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T178	7		T204	8		T174	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T15	5		T231	6		T107	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T1	9		T28	6		T61	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T3	21		T15	9		T156	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T155	15		T164	15		T43	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T30	13		T228	7		T232	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1239	1			T32	17		T172	15		T102	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T48	22		T95	6		T261	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T7	12		T40	2		T249	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T12	11		T30	14		T162	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T1	12		T7	11		T18	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T151	15		T156	5		T234	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T48	13		T157	2		T181	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T162	8		T40	5		T102	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T186	9		T215	8		T230	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T6	11		T181	14		T45	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T34	20		T151	16		T237	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T61	8		T189	1		T47	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T88	12		T184	13		T326	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T1	13		T3	16		T158	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T327	10		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T40	1		T262	14		T321	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T185	3		T299	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T327	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T231	1		T322	11		T323	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T16	4		T178	7		T204	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T15	5		T154	1		T16	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T1	1		T28	1		T61	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T3	1		T15	9		T155	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T186	13		T163	1		T158	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T166	3		T228	9		T232	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1369	1			T8	3		T11	11		T14	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T48	5		T30	12		T43	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T1	1		T30	1		T40	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T12	1		T161	1		T215	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T7	4		T161	1		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T30	6		T162	8		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T7	13		T48	11		T33	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T6	15		T162	8		T151	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T154	1		T34	13		T186	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T40	8		T43	6		T181	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	321	1			T13	2		T34	4		T151	30
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	414	1			T1	1		T3	1		T28	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17210	1			T2	20		T4	20		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T262	15		T321	8		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T185	1		T299	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T327	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T231	6		T322	14		T328	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T178	7		T204	8		T168	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T15	5		T107	16		T173	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T1	9		T28	6		T61	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T3	21		T15	9		T156	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T186	2		T158	4		T164	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T228	7		T232	9		T229	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1261	1			T32	17		T155	15		T172	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T48	22		T30	13		T249	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	12		T40	2		T188	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T12	11		T215	8		T329	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T7	12		T169	11		T249	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T30	14		T162	9		T156	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T7	11		T48	13		T18	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T6	11		T162	8		T151	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T34	16		T157	2		T181	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T40	5		T43	5		T181	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T34	4		T151	16		T186	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T1	13		T3	16		T61	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22186

1

T1

3

T2

20

T3

2

auto[1]

auto[0]

4325

1

T1

34

T3

37

T6

11