Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26511

1

T1

37

T2

20

T3

39

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22770

1

T1

10

T2

20

T3

22

auto[ADC_CTRL_FILTER_COND_OUT]

3741

1

T1

27

T3

17

T7

40

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19747

1

T1

10

T2

20

T3

22

auto[1]

6764

1

T1

27

T3

17

T6

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22444

1

T1

37

T2

20

T3

39

auto[1]

4067

1

T6

15

T7

15

T11

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	666	1			T6	3		T42	1		T51	2
values[0]	29	1			T247	1		T184	23		T313	5
values[1]	625	1			T231	7		T186	20		T157	1
values[2]	2968	1			T1	27		T7	24		T8	3
values[3]	713	1			T15	18		T227	1		T48	24
values[4]	784	1			T6	26		T166	3		T28	8
values[5]	722	1			T3	22		T16	1		T30	25
values[6]	777	1			T1	10		T3	17		T154	2
values[7]	746	1			T12	12		T48	27		T16	4
values[8]	566	1			T161	1		T186	2		T155	13
values[9]	1162	1			T7	16		T13	2		T161	1
minimum	16753	1			T2	20		T4	20		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	627	1			T7	24		T34	8		T178	14
values[1]	2968	1			T1	27		T8	3		T11	11
values[2]	648	1			T6	26		T15	18		T48	24
values[3]	815	1			T166	3		T16	1		T28	7
values[4]	667	1			T3	22		T30	25		T172	16
values[5]	824	1			T1	10		T3	17		T12	12
values[6]	703	1			T48	27		T16	4		T61	40
values[7]	702	1			T161	2		T170	1		T186	2
values[8]	908	1			T7	16		T13	2		T154	1
values[9]	176	1			T228	16		T160	1		T249	16
minimum	17473	1			T2	20		T4	20		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22186

1

T1

3

T2

20

T3

2

auto[1]

4325

1

T1

34

T3

37

T6

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T34	5		T178	8		T157	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T7	12		T231	7		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1549	1			T8	3		T11	1		T14	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T1	27		T227	1		T204	23
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T6	12		T15	10		T28	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T48	14		T186	3		T163	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T166	1		T33	1		T229	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T16	1		T28	7		T157	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T3	22		T100	1		T44	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T30	14		T172	16		T102	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T1	10		T12	12		T154	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T3	17		T164	17		T172	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T156	11		T164	8		T159	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T48	23		T16	3		T61	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T186	1		T155	1		T156	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T161	2		T170	1		T164	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T13	1		T154	1		T162	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T7	13		T13	1		T151	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T160	1		T249	16		T315	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T228	8		T330	1		T20	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17140	1			T2	20		T4	20		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T186	10		T204	9		T225	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T34	3		T178	6		T165	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T7	12		T155	7		T229	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1007	1			T11	10		T14	8		T15	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T36	16		T223	13		T192	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T6	14		T15	8		T34	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T48	10		T186	12		T229	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T166	2		T229	14		T182	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T157	6		T237	1		T45	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T44	1		T223	4		T243	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T30	11		T102	13		T206	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T151	12		T43	5		T262	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T164	6		T102	8		T252	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T164	5		T280	10		T288	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T48	4		T16	1		T61	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T186	1		T155	12		T156	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T164	14		T124	13		T169	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T162	14		T43	4		T181	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T7	3		T151	10		T40	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T253	11		T194	9		T250	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T228	8		T20	1		T109	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T6	1		T16	1		T28	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T186	10		T236	10		T309	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	494	1			T6	3		T42	1		T51	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T190	1		T269	1		T277	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T247	1		T184	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T313	5		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T157	1		T171	1		T165	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T231	7		T186	10		T204	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1584	1			T8	3		T11	1		T14	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T1	27		T7	12		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T15	10		T30	15		T34	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T227	1		T48	14		T204	23
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T6	12		T166	1		T28	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T28	7		T186	3		T157	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T3	22		T100	1		T128	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T16	1		T30	14		T237	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T1	10		T154	2		T157	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T3	17		T164	17		T172	31
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T12	12		T151	3		T156	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T48	23		T16	3		T61	20
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T186	1		T155	1		T158	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T161	1		T100	1		T43	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	351	1			T13	1		T154	1		T162	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T7	13		T13	1		T161	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16624	1			T2	20		T4	20		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T193	12		T258	13		T331	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T332	13		T20	1		T333	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T184	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T171	8		T165	4		T40	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T186	10		T229	6		T174	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1001	1			T11	10		T14	8		T15	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T7	12		T155	7		T223	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T15	8		T30	5		T34	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T48	10		T229	2		T17	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T6	14		T166	2		T229	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T186	12		T157	6		T45	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T44	1		T223	4		T182	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T30	11		T237	1		T102	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T43	5		T262	13		T243	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T164	6		T252	3		T294	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T151	12		T164	5		T192	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T48	4		T16	1		T61	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T186	1		T155	12		T158	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T234	4		T169	6		T238	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T162	14		T156	10		T43	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T7	3		T228	8		T151	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T6	1		T16	1		T28	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T34	4		T178	7		T157	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T7	13		T231	1		T155	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1345	1			T8	3		T11	11		T14	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T1	2		T227	1		T204	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T6	15		T15	9		T28	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T48	11		T186	13		T163	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T166	3		T33	1		T229	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T16	1		T28	1		T157	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T3	1		T100	1		T44	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T30	12		T172	1		T102	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T1	1		T12	1		T154	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T3	1		T164	7		T172	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T156	1		T164	6		T159	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T48	5		T16	4		T61	22
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T186	2		T155	13		T156	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T161	2		T170	1		T164	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T13	1		T154	1		T162	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T7	4		T13	1		T151	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T160	1		T249	1		T315	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T228	9		T330	1		T20	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17264	1			T2	20		T4	20		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T186	11		T204	1		T225	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T34	4		T178	7		T107	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T7	11		T231	6		T229	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1211	1			T15	5		T30	14		T32	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T1	25		T204	22		T95	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T6	11		T15	9		T34	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T48	13		T186	2		T229	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T229	14		T225	16		T249	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T28	6		T157	2		T237	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T3	21		T169	7		T88	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T30	13		T172	15		T102	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T1	9		T12	11		T151	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T3	16		T164	16		T172	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T156	10		T164	7		T288	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T48	22		T61	18		T155	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T156	13		T158	4		T249	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T164	15		T124	9		T169	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T162	17		T43	4		T181	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T7	12		T151	15		T40	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T249	15		T194	13		T250	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T228	7		T20	1		T109	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T40	2		T215	8		T184	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T186	9		T204	8		T225	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	531	1			T6	3		T42	1		T51	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T190	1		T269	1		T277	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T247	1		T184	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T313	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T157	1		T171	9		T165	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T231	1		T186	11		T204	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1336	1			T8	3		T11	11		T14	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T1	2		T7	13		T155	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T15	9		T30	6		T34	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T227	1		T48	11		T204	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T6	15		T166	3		T28	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T28	1		T186	13		T157	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T3	1		T100	1		T128	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T16	1		T30	12		T237	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T1	1		T154	2		T157	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T3	1		T164	7		T172	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T12	1		T151	13		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T48	5		T16	4		T61	22
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T186	2		T155	13		T158	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T161	1		T100	1		T43	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T13	1		T154	1		T162	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	347	1			T7	4		T13	1		T161	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16753	1			T2	20		T4	20		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T299	10		T334	15		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T277	15		T332	13		T20	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T184	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T313	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T40	2		T107	16		T215	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T231	6		T186	9		T204	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1249	1			T15	5		T32	17		T34	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T1	25		T7	11		T95	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T15	9		T30	14		T34	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T48	13		T204	22		T229	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T6	11		T229	14		T225	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T28	6		T186	2		T157	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T3	21		T169	7		T88	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T30	13		T237	12		T102	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T1	9		T43	5		T246	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T3	16		T164	16		T172	29
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T12	11		T151	2		T156	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T48	22		T61	18		T155	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T158	4		T249	16		T256	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T234	4		T215	5		T169	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T162	17		T156	13		T43	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T7	12		T228	7		T151	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22186

1

T1

3

T2

20

T3

2

auto[1]

auto[0]

4325

1

T1

34

T3

37

T6

11