Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26511

1

T1

37

T2

20

T3

39

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22738

1

T2

20

T4

20

T5

20

auto[ADC_CTRL_FILTER_COND_OUT]

3773

1

T1

37

T3

39

T6

26

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20284

1

T1

13

T2

20

T4

20

auto[1]

6227

1

T1

24

T3

39

T6

26

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22444

1

T1

37

T2

20

T3

39

auto[1]

4067

1

T6

15

T7

15

T11

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	268	1			T1	13		T156	11		T172	1
values[0]	29	1			T89	1		T218	15		T335	1
values[1]	590	1			T13	1		T154	1		T16	1
values[2]	878	1			T1	14		T3	17		T6	26
values[3]	649	1			T15	18		T16	4		T186	20
values[4]	865	1			T151	31		T155	34		T41	3
values[5]	712	1			T154	1		T48	27		T33	1
values[6]	825	1			T1	10		T3	22		T7	24
values[7]	671	1			T7	16		T154	1		T34	8
values[8]	2968	1			T8	3		T11	11		T13	1
values[9]	846	1			T12	12		T161	2		T166	3
minimum	17210	1			T2	20		T4	20		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	825	1			T1	14		T13	1		T154	1
values[1]	627	1			T3	17		T6	26		T227	1
values[2]	765	1			T15	18		T16	4		T186	20
values[3]	812	1			T48	27		T151	31		T41	3
values[4]	786	1			T15	10		T154	1		T28	1
values[5]	651	1			T1	10		T3	22		T7	24
values[6]	2999	1			T7	16		T8	3		T11	11
values[7]	731	1			T13	1		T161	1		T30	20
values[8]	784	1			T12	12		T161	1		T166	3
values[9]	171	1			T1	13		T172	15		T181	7
minimum	17360	1			T2	20		T4	20		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22186

1

T1

3

T2

20

T3

2

auto[1]

4325

1

T1

34

T3

37

T6

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T154	1		T48	14		T162	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T1	14		T13	1		T61	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T162	10		T229	25		T164	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T3	17		T6	12		T227	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T15	10		T16	3		T155	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T186	10		T43	6		T46	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T41	3		T47	5		T169	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T48	23		T151	15		T102	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T15	6		T33	1		T231	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T154	1		T28	1		T171	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T28	7		T232	10		T157	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T1	10		T3	22		T7	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1580	1			T8	3		T11	1		T14	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T7	13		T228	8		T186	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T30	15		T61	11		T229	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T13	1		T161	1		T157	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T166	1		T186	1		T156	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T12	12		T161	1		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T172	15		T181	4		T238	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T1	13		T325	1		T336	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17107	1			T2	20		T4	20		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T16	1		T188	1		T266	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T48	10		T162	7		T151	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T61	5		T164	14		T182	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T162	7		T229	20		T164	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T6	14		T173	15		T206	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T15	8		T16	1		T155	30
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T186	10		T43	4		T46	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T47	1		T251	12		T192	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T48	4		T151	16		T102	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T15	4		T155	7		T171	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T223	13		T108	2		T93	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T40	3		T36	16		T169	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T7	12		T151	12		T40	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	998	1			T11	10		T14	8		T152	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T7	3		T228	8		T186	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T30	5		T61	15		T229	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T157	6		T44	1		T175	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T166	2		T186	1		T207	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T34	12		T173	13		T188	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T181	3		T238	10		T217	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T325	9		T337	6		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T6	1		T16	1		T28	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T266	8		T242	11		T244	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T156	11		T225	9		T89	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T1	13		T172	1		T271	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T89	1		T218	15		T335	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T301	3		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T154	1		T30	14		T151	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T13	1		T16	1		T61	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T48	14		T162	19		T229	25
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T1	14		T3	17		T6	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T15	10		T16	3		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T186	10		T204	9		T173	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T155	16		T41	3		T47	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T151	15		T102	6		T43	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T33	1		T155	1		T102	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T154	1		T48	23		T171	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T15	6		T28	7		T231	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T1	10		T3	22		T7	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T154	1		T34	5		T178	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T7	13		T228	8		T151	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1568	1			T8	3		T11	1		T14	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T13	1		T157	3		T172	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T166	1		T186	1		T163	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T12	12		T161	2		T30	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17081	1			T2	20		T4	20		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T238	10		T290	3		T209	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T168	2		T325	9		T338	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T301	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T30	11		T151	10		T156	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T61	5		T182	6		T266	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T48	10		T162	14		T229	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T6	14		T164	14		T230	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T15	8		T16	1		T155	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T186	10		T173	15		T206	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T155	18		T47	1		T251	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T151	16		T102	13		T43	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T155	7		T102	8		T44	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T48	4		T17	3		T234	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T15	4		T171	8		T40	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T7	12		T40	6		T188	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T34	3		T178	6		T158	22
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T7	3		T228	8		T151	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1031	1			T11	10		T14	8		T152	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T157	6		T44	1		T175	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T166	2		T186	1		T181	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T34	12		T173	13		T188	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T6	1		T16	1		T28	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T154	1		T48	11		T162	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T1	1		T13	1		T61	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T162	8		T229	22		T164	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T3	1		T6	15		T227	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T15	9		T16	4		T155	32
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T186	11		T43	6		T46	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T41	3		T47	4		T169	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T48	5		T151	17		T102	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T15	5		T33	1		T231	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T154	1		T28	1		T171	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T28	1		T232	1		T157	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T1	1		T3	1		T7	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1338	1			T8	3		T11	11		T14	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T7	4		T228	9		T186	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T30	6		T61	16		T229	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T13	1		T161	1		T157	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T166	3		T186	2		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T12	1		T161	1		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T172	1		T181	4		T238	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T1	1		T325	10		T336	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17257	1			T2	20		T4	20		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T16	1		T188	1		T266	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T48	13		T162	8		T151	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T1	13		T61	8		T164	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T162	9		T229	23		T164	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T3	16		T6	11		T204	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T15	9		T155	15		T156	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T186	9		T43	4		T46	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T47	2		T169	7		T249	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T48	22		T151	14		T102	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T15	5		T231	6		T102	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T108	5		T93	13		T238	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T28	6		T232	9		T40	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T1	9		T3	21		T7	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1240	1			T32	17		T34	4		T178	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T7	12		T228	7		T186	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T30	14		T61	10		T229	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T157	2		T172	15		T175	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T156	10		T215	8		T225	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T12	11		T34	16		T204	22
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T172	14		T181	3		T238	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T1	12		T336	14		T337	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T30	13		T252	3		T35	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T242	12		T244	2		T287	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T156	1		T225	1		T89	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T1	1		T172	1		T271	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T89	1		T218	1		T335	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T301	9		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T154	1		T30	12		T151	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T13	1		T16	1		T61	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T48	11		T162	16		T229	22
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T1	1		T3	1		T6	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T15	9		T16	4		T155	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T186	11		T204	1		T173	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T155	19		T41	3		T47	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T151	17		T102	14		T43	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T33	1		T155	8		T102	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T154	1		T48	5		T171	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T15	5		T28	1		T231	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T1	1		T3	1		T7	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T154	1		T34	4		T178	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T7	4		T228	9		T151	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1373	1			T8	3		T11	11		T14	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T13	1		T157	7		T172	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T166	3		T186	2		T163	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T12	1		T161	2		T30	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17210	1			T2	20		T4	20		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T156	10		T225	8		T238	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T1	12		T168	11		T338	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T218	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T301	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T30	13		T151	15		T156	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T61	8		T339	9		T242	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T48	13		T162	17		T229	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T1	13		T3	16		T6	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T15	9		T156	5		T124	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T186	9		T204	8		T173	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T155	15		T47	2		T169	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T151	14		T102	5		T43	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T102	8		T117	11		T18	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T48	22		T17	3		T234	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T15	5		T28	6		T231	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T1	9		T3	21		T7	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T34	4		T178	7		T158	21
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T7	12		T228	7		T151	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1226	1			T30	14		T32	17		T61	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T157	2		T172	15		T189	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T172	14		T181	3		T215	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T12	11		T34	16		T204	22

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22186

1

T1

3

T2

20

T3

2

auto[1]

auto[0]

4325

1

T1

34

T3

37

T6

11