Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26511

1

T1

37

T2

20

T3

39

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22752

1

T2

20

T4

20

T5

20

auto[ADC_CTRL_FILTER_COND_OUT]

3759

1

T1

37

T3

39

T6

26

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20204

1

T1

13

T2

20

T4

20

auto[1]

6307

1

T1

24

T3

39

T6

26

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22444

1

T1

37

T2

20

T3

39

auto[1]

4067

1

T6

15

T7

15

T11

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	28	1			T89	1		T284	10		T198	8
values[0]	45	1			T252	7		T287	14		T296	1
values[1]	597	1			T1	14		T13	1		T154	1
values[2]	887	1			T3	17		T6	26		T227	1
values[3]	630	1			T15	18		T16	4		T186	20
values[4]	854	1			T151	31		T155	34		T41	3
values[5]	726	1			T48	27		T33	1		T231	7
values[6]	899	1			T1	10		T3	22		T7	24
values[7]	536	1			T7	16		T13	1		T178	14
values[8]	3006	1			T8	3		T11	11		T14	9
values[9]	1093	1			T1	13		T12	12		T161	2
minimum	17210	1			T2	20		T4	20		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	983	1			T1	14		T13	1		T154	1
values[1]	616	1			T3	17		T6	26		T227	1
values[2]	644	1			T15	18		T16	4		T186	20
values[3]	946	1			T48	27		T151	31		T41	3
values[4]	762	1			T15	10		T154	1		T28	1
values[5]	621	1			T1	10		T3	22		T7	24
values[6]	3044	1			T7	16		T8	3		T11	11
values[7]	667	1			T13	1		T161	1		T30	20
values[8]	700	1			T12	12		T161	1		T166	3
values[9]	284	1			T1	13		T186	2		T172	15
minimum	17244	1			T2	20		T4	20		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22186

1

T1

3

T2

20

T3

2

auto[1]

4325

1

T1

34

T3

37

T6

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T154	1		T48	14		T30	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T1	14		T13	1		T16	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T162	10		T229	15		T164	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T3	17		T6	12		T227	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T15	10		T16	3		T155	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T186	10		T46	3		T182	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T41	3		T124	10		T47	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T48	23		T151	15		T102	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T15	6		T33	1		T231	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T154	1		T28	1		T171	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T28	7		T158	12		T171	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T1	10		T3	22		T7	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1584	1			T8	3		T11	1		T14	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T7	13		T178	8		T228	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T30	15		T61	11		T229	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T13	1		T161	1		T157	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T166	1		T156	11		T204	23
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T12	12		T161	1		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T186	1		T172	15		T181	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T1	13		T173	15		T325	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17084	1			T2	20		T4	20		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T266	1		T208	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T48	10		T30	11		T162	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T61	5		T156	10		T164	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T162	7		T229	14		T164	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T6	14		T229	6		T173	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T15	8		T16	1		T155	30
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T186	10		T46	1		T182	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T124	13		T47	1		T251	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T48	4		T151	16		T102	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T15	4		T155	7		T102	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T223	13		T108	2		T93	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T158	11		T171	8		T40	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T7	12		T40	6		T238	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1009	1			T11	10		T14	8		T152	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T7	3		T178	6		T228	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T30	5		T61	15		T229	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T157	6		T44	1		T175	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T166	2		T256	3		T207	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T34	12		T188	10		T168	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T186	1		T181	3		T238	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T173	13		T325	9		T309	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T6	1		T16	1		T28	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T266	8		T208	11		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T89	1		T284	10		T198	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T337	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T252	4		T218	15		T335	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T287	8		T296	1		T340	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T154	1		T30	14		T151	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T1	14		T13	1		T16	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T48	14		T162	19		T229	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T3	17		T6	12		T227	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T15	10		T16	3		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T186	10		T204	9		T102	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T155	16		T41	3		T47	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T151	15		T43	12		T46	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T33	1		T231	7		T155	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T48	23		T171	1		T17	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T15	6		T28	7		T34	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T1	10		T3	22		T7	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T158	11		T44	1		T220	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T7	13		T13	1		T178	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1576	1			T8	3		T11	1		T14	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T157	3		T172	16		T40	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T166	1		T186	1		T156	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T1	13		T12	12		T161	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17081	1			T2	20		T4	20		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T337	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T252	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T287	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T30	11		T151	10		T158	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T61	5		T156	10		T182	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T48	10		T162	14		T229	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T6	14		T229	6		T164	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T15	8		T16	1		T155	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T186	10		T102	13		T173	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T155	18		T47	1		T18	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T151	16		T43	9		T46	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T155	7		T171	8		T102	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T48	4		T17	3		T234	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T15	4		T34	3		T158	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T7	12		T237	1		T40	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T158	11		T44	1		T233	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T7	3		T178	6		T228	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1035	1			T11	10		T14	8		T152	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T157	6		T181	19		T44	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T166	2		T186	1		T181	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T34	12		T173	13		T188	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T6	1		T16	1		T28	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T154	1		T48	11		T30	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T1	1		T13	1		T16	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T162	8		T229	15		T164	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T3	1		T6	15		T227	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T15	9		T16	4		T155	32
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T186	11		T46	3		T182	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T41	3		T124	14		T47	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T48	5		T151	17		T102	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T15	5		T33	1		T231	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T154	1		T28	1		T171	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T28	1		T158	12		T171	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T1	1		T3	1		T7	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1353	1			T8	3		T11	11		T14	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T7	4		T178	7		T228	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T30	6		T61	16		T229	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T13	1		T161	1		T157	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T166	3		T156	1		T204	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T12	1		T161	1		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T186	2		T172	1		T181	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T1	1		T173	14		T325	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17213	1			T2	20		T4	20		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T266	9		T208	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T48	13		T30	13		T162	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T1	13		T61	8		T156	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T162	9		T229	14		T164	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T3	16		T6	11		T204	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T15	9		T155	15		T156	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T186	9		T46	1		T90	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T124	9		T47	2		T169	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T48	22		T151	14		T102	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T15	5		T231	6		T102	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T108	5		T93	13		T184	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T28	6		T158	11		T40	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T1	9		T3	21		T7	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1240	1			T32	17		T34	4		T158	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T7	12		T178	7		T228	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T30	14		T61	10		T229	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T157	2		T172	15		T175	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T156	10		T204	22		T225	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T12	11		T34	16		T188	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T172	14		T181	3		T215	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T1	12		T173	14		T336	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T35	1		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T208	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T89	1		T284	1		T198	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T337	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T252	4		T218	1		T335	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T287	7		T296	1		T340	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T154	1		T30	12		T151	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T1	1		T13	1		T16	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T48	11		T162	16		T229	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T3	1		T6	15		T227	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T15	9		T16	4		T155	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T186	11		T204	1		T102	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T155	19		T41	3		T47	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T151	17		T43	12		T46	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T33	1		T231	1		T155	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T48	5		T171	1		T17	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T15	5		T28	1		T34	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T1	1		T3	1		T7	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T158	12		T44	2		T220	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T7	4		T13	1		T178	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1377	1			T8	3		T11	11		T14	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T157	7		T172	1		T40	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T166	3		T186	2		T156	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	367	1			T1	1		T12	1		T161	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17210	1			T2	20		T4	20		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T284	9		T198	7		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T337	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T252	3		T218	14		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T287	7		T340	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T30	13		T151	15		T158	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T1	13		T61	8		T156	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T48	13		T162	17		T229	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T3	16		T6	11		T229	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T15	9		T156	5		T124	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T186	9		T204	8		T102	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T155	15		T47	2		T18	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T151	14		T43	9		T46	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T231	6		T102	8		T117	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T48	22		T17	3		T234	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T15	5		T28	6		T34	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T1	9		T3	21		T7	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T158	10		T249	15		T241	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T7	12		T178	7		T228	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1234	1			T30	14		T32	17		T61	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T157	2		T172	15		T181	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T156	10		T204	22		T172	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T1	12		T12	11		T34	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22186

1

T1

3

T2

20

T3

2

auto[1]

auto[0]

4325

1

T1

34

T3

37

T6

11