Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26511

1

T1

37

T2

20

T3

39

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22890

1

T1

24

T2

20

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3621

1

T1

13

T3

39

T6

26

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20591

1

T1

24

T2

20

T4

20

auto[1]

5920

1

T1

13

T3

39

T6

26

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22444

1

T1

37

T2

20

T3

39

auto[1]

4067

1

T6

15

T7

15

T11

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	290	1			T124	23		T220	1		T236	9
values[0]	85	1			T13	1		T161	1		T174	19
values[1]	776	1			T7	16		T15	18		T154	1
values[2]	642	1			T178	14		T186	2		T237	14
values[3]	806	1			T3	17		T228	16		T204	9
values[4]	517	1			T161	1		T154	1		T16	1
values[5]	3040	1			T1	10		T3	22		T6	26
values[6]	748	1			T1	13		T28	7		T33	1
values[7]	627	1			T34	8		T151	26		T41	3
values[8]	618	1			T1	14		T12	12		T13	1
values[9]	1152	1			T15	10		T166	3		T48	24
minimum	17210	1			T2	20		T4	20		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	723	1			T161	1		T154	1		T16	4
values[1]	772	1			T61	14		T178	14		T186	2
values[2]	637	1			T3	17		T228	16		T204	9
values[3]	2840	1			T8	3		T11	11		T14	9
values[4]	833	1			T1	10		T3	22		T6	26
values[5]	649	1			T1	13		T28	7		T33	1
values[6]	629	1			T12	12		T30	20		T34	8
values[7]	747	1			T1	14		T13	1		T48	51
values[8]	1106	1			T15	10		T166	3		T30	1
values[9]	109	1			T157	1		T163	1		T181	7
minimum	17466	1			T2	20		T4	20		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22186

1

T1

3

T2

20

T3

2

auto[1]

4325

1

T1

34

T3

37

T6

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T16	3		T28	1		T232	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T161	1		T154	1		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T186	1		T172	16		T40	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T61	9		T178	8		T164	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T228	8		T171	1		T181	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T3	17		T204	9		T117	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1501	1			T8	3		T11	1		T14	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T170	1		T157	1		T43	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T1	10		T7	12		T227	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T3	22		T6	12		T30	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T33	1		T162	10		T151	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T1	13		T28	7		T164	33
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T12	12		T30	15		T229	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T34	5		T102	9		T107	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T1	14		T13	1		T48	23
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T48	14		T162	9		T158	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T186	10		T156	20		T206	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T15	6		T166	1		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T157	1		T163	1		T181	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T184	14		T198	11		T274	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17177	1			T2	20		T4	20		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T7	13		T13	1		T18	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T16	1		T237	1		T171	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T155	12		T40	6		T43	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T186	1		T173	15		T167	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T61	5		T178	6		T164	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T228	8		T181	19		T47	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T117	12		T290	3		T293	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	987	1			T11	10		T14	8		T152	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T43	4		T44	2		T167	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T7	12		T229	6		T158	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T6	14		T30	11		T151	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T162	7		T151	10		T44	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T164	20		T245	11		T233	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T30	5		T229	2		T238	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T34	3		T102	8		T168	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T48	4		T61	15		T186	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T48	10		T162	7		T158	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T186	10		T156	15		T206	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T15	4		T166	2		T34	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T181	3		T341	15		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T184	18		T274	3		T342	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T6	1		T15	8		T16	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T7	3		T18	9		T254	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T287	8		T343	5		T218	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T124	10		T220	1		T236	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T174	10		T183	1		T298	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T13	1		T161	1		T300	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T15	10		T16	3		T28	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T7	13		T154	1		T61	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T186	1		T237	13		T172	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T178	8		T252	4		T182	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T228	8		T171	1		T181	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T3	17		T204	9		T164	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T161	1		T154	1		T16	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T157	1		T43	6		T44	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1629	1			T1	10		T7	12		T8	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T3	22		T6	12		T30	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T33	1		T162	10		T231	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T1	13		T28	7		T164	33
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T151	16		T41	3		T215	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T34	5		T107	17		T271	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T1	14		T12	12		T13	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T162	9		T172	15		T102	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T186	10		T156	20		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T15	6		T166	1		T48	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17081	1			T2	20		T4	20		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T287	6		T341	15		T289	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T124	13		T236	8		T184	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T174	9		T298	12		T344	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T300	18		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T15	8		T16	1		T151	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T7	3		T61	5		T155	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T186	1		T237	1		T173	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T178	6		T252	3		T182	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T228	8		T181	19		T238	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T164	5		T165	4		T102	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T158	11		T47	1		T38	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T43	4		T44	2		T167	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1029	1			T7	12		T11	10		T14	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T6	14		T30	11		T151	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T162	7		T44	1		T45	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T164	20		T40	3		T245	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T151	10		T238	11		T286	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T34	3		T168	14		T182	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T48	4		T30	5		T61	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T162	7		T102	8		T46	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T186	10		T156	15		T181	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T15	4		T166	2		T48	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T6	1		T16	1		T28	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T16	4		T28	1		T232	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T161	1		T154	1		T155	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T186	2		T172	1		T40	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T61	6		T178	7		T164	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T228	9		T171	1		T181	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T3	1		T204	1		T117	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1317	1			T8	3		T11	11		T14	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T170	1		T157	1		T43	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T1	1		T7	13		T227	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T3	1		T6	15		T30	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T33	1		T162	8		T151	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T1	1		T28	1		T164	22
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T12	1		T30	6		T229	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T34	4		T102	9		T107	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T1	1		T13	1		T48	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T48	11		T162	8		T158	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T186	11		T156	17		T206	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	359	1			T15	5		T166	3		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T157	1		T163	1		T181	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T184	19		T198	1		T274	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17307	1			T2	20		T4	20		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T7	4		T13	1		T18	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T232	9		T237	12		T174	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T40	2		T43	5		T234	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T172	15		T173	14		T167	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T61	8		T178	7		T164	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T228	7		T181	14		T47	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T3	16		T204	8		T117	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1171	1			T32	17		T158	10		T126	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T43	4		T249	13		T256	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T1	9		T7	11		T229	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T3	21		T6	11		T30	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T162	9		T151	15		T231	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T1	12		T28	6		T164	31
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T12	11		T30	14		T229	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T34	4		T102	8		T107	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T1	13		T48	22		T61	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T48	13		T162	8		T158	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T186	9		T156	18		T206	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T15	5		T34	16		T155	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T181	3		T341	14		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T184	13		T198	10		T301	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T15	9		T151	14		T229	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T7	12		T18	8		T254	3

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T287	7		T343	1		T218	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T124	14		T220	1		T236	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T174	10		T183	1		T298	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T13	1		T161	1		T300	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T15	9		T16	4		T28	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T7	4		T154	1		T61	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T186	2		T237	2		T172	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T178	7		T252	4		T182	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T228	9		T171	1		T181	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T3	1		T204	1		T164	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T161	1		T154	1		T16	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T157	1		T43	6		T44	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1367	1			T1	1		T7	13		T8	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T3	1		T6	15		T30	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T33	1		T162	8		T231	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T1	1		T28	1		T164	22
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T151	11		T41	3		T215	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T34	4		T107	1		T271	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T1	1		T12	1		T13	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T162	8		T172	1		T102	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T186	11		T156	17		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	363	1			T15	5		T166	3		T48	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17210	1			T2	20		T4	20		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T287	7		T343	4		T218	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T124	9		T184	13		T192	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T174	9		T298	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T300	17		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T15	9		T151	14		T232	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T7	12		T61	8		T40	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T237	12		T172	15		T173	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T178	7		T252	3		T88	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T228	7		T181	14		T93	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T3	16		T204	8		T164	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T158	10		T47	2		T215	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T43	4		T249	13		T246	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1291	1			T1	9		T7	11		T32	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T3	21		T6	11		T30	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T162	9		T231	6		T204	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T1	12		T28	6		T164	31
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T151	15		T215	8		T95	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T34	4		T107	16		T168	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T1	13		T12	11		T48	22
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T162	8		T172	14		T102	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T186	9		T156	18		T181	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T15	5		T48	13		T34	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22186

1

T1

3

T2

20

T3

2

auto[1]

auto[0]

4325

1

T1

34

T3

37

T6

11