Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26511

1

T1

37

T2

20

T3

39

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22608

1

T1

23

T2

20

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3903

1

T1

14

T3

39

T6

26

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20683

1

T1

24

T2

20

T3

22

auto[1]

5828

1

T1

13

T3

17

T6

26

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22444

1

T1

37

T2

20

T3

39

auto[1]

4067

1

T6

15

T7

15

T11

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	374	1			T3	17		T28	1		T34	8
values[0]	52	1			T210	12		T327	11		T328	29
values[1]	531	1			T15	10		T154	1		T16	5
values[2]	870	1			T1	10		T15	18		T28	7
values[3]	762	1			T3	22		T166	3		T30	25
values[4]	2923	1			T8	3		T11	11		T14	9
values[5]	586	1			T12	12		T161	2		T40	10
values[6]	793	1			T1	13		T7	16		T154	1
values[7]	731	1			T6	26		T7	24		T48	24
values[8]	585	1			T154	1		T34	29		T186	2
values[9]	1094	1			T1	14		T13	2		T61	14
minimum	17210	1			T2	20		T4	20		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	433	1			T15	10		T154	1		T16	1
values[1]	941	1			T1	10		T3	22		T15	18
values[2]	758	1			T30	25		T228	16		T232	10
values[3]	2842	1			T8	3		T11	11		T14	9
values[4]	697	1			T7	16		T12	12		T161	1
values[5]	775	1			T1	13		T7	24		T161	1
values[6]	556	1			T48	24		T162	16		T157	9
values[7]	732	1			T6	26		T154	1		T34	29
values[8]	1006	1			T3	17		T13	2		T28	1
values[9]	280	1			T1	14		T158	23		T164	13
minimum	17491	1			T2	20		T4	20		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22186

1

T1

3

T2

20

T3

2

auto[1]

4325

1

T1

34

T3

37

T6

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T204	9		T271	1		T174	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T15	6		T154	1		T16	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T1	10		T28	7		T61	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T3	22		T15	10		T166	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T164	16		T43	6		T124	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T30	14		T228	8		T232	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1598	1			T8	3		T11	1		T14	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T48	23		T249	14		T236	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T7	13		T170	1		T171	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T12	12		T161	1		T30	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T1	13		T7	12		T161	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T151	16		T156	6		T102	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T48	14		T157	3		T181	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T162	9		T172	1		T40	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T154	1		T34	17		T186	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T6	12		T181	15		T45	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T13	2		T34	5		T151	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T3	17		T28	1		T61	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T345	11		T346	8		T347	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T1	14		T158	12		T164	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17140	1			T2	20		T4	20		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T107	17		T297	1		T324	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T174	9		T168	14		T87	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T15	4		T173	15		T117	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T61	15		T186	12		T229	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T15	8		T166	2		T155	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T164	14		T43	4		T124	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T30	11		T228	8		T229	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1017	1			T11	10		T14	8		T152	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T48	4		T236	8		T266	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T7	3		T171	8		T40	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T30	5		T162	7		T38	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T7	12		T169	6		T108	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T151	10		T156	5		T102	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T48	10		T157	6		T181	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T162	7		T40	3		T43	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T34	12		T186	1		T165	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T6	14		T181	19		T45	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T34	3		T151	28		T186	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T61	5		T47	1		T236	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T345	12		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T158	11		T164	5		T251	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T6	1		T16	2		T28	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T243	1		T325	9		T272	17

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T34	5		T157	1		T229	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T3	17		T28	1		T158	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T210	1		T327	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T328	14		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T16	3		T178	8		T204	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T15	6		T154	1		T16	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T1	10		T28	7		T229	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T15	10		T155	1		T156	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T61	11		T186	3		T163	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T3	22		T166	1		T30	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1608	1			T8	3		T11	1		T14	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T48	23		T43	1		T249	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T161	1		T40	4		T44	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T12	12		T161	1		T236	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T1	13		T7	13		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T30	15		T162	10		T156	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T7	12		T48	14		T33	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T6	12		T162	9		T151	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T154	1		T34	17		T186	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T40	10		T43	6		T181	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T13	2		T151	18		T186	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T1	14		T61	9		T164	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17081	1			T2	20		T4	20		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T34	3		T229	6		T262	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T158	11		T236	10		T251	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T210	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T328	15		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T16	1		T178	6		T168	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T15	4		T173	15		T117	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T229	2		T164	6		T174	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T15	8		T155	12		T156	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T61	15		T186	12		T158	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T166	2		T30	11		T228	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1035	1			T11	10		T14	8		T152	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T48	4		T266	8		T261	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T40	6		T44	1		T188	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T236	8		T230	1		T272	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T7	3		T171	8		T169	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T30	5		T162	7		T175	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T7	12		T48	10		T18	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T6	14		T162	7		T151	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T34	12		T186	1		T157	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T40	3		T43	5		T181	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T151	28		T186	10		T155	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T61	5		T164	5		T45	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T6	1		T16	1		T28	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T204	1		T271	1		T174	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T15	5		T154	1		T16	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T1	1		T28	1		T61	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T3	1		T15	9		T166	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T164	15		T43	6		T124	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T30	12		T228	9		T232	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1363	1			T8	3		T11	11		T14	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T48	5		T249	1		T236	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T7	4		T170	1		T171	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T12	1		T161	1		T30	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T1	1		T7	13		T161	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T151	11		T156	6		T102	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T48	11		T157	7		T181	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T162	8		T172	1		T40	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T154	1		T34	13		T186	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T6	15		T181	20		T45	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T13	2		T34	4		T151	30
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T3	1		T28	1		T61	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T345	13		T346	1		T347	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T1	1		T158	12		T164	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17273	1			T2	20		T4	20		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T107	1		T297	1		T324	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T204	8		T174	9		T168	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T15	5		T231	6		T173	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T1	9		T28	6		T61	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T3	21		T15	9		T156	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T164	15		T43	4		T124	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T30	13		T228	7		T232	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1252	1			T32	17		T155	15		T172	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T48	22		T249	13		T95	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T7	12		T40	2		T249	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T12	11		T30	14		T162	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T1	12		T7	11		T169	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T151	15		T156	5		T102	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T48	13		T157	2		T181	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T162	8		T40	5		T43	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T34	16		T215	8		T244	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T6	11		T181	14		T45	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T34	4		T151	16		T186	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T3	16		T61	8		T189	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T345	10		T346	7		T347	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T1	13		T158	11		T164	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T178	7		T277	14		T194	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T107	16		T243	1		T208	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T34	4		T157	1		T229	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T3	1		T28	1		T158	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T210	12		T327	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T328	16		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T16	4		T178	7		T204	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T15	5		T154	1		T16	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T1	1		T28	1		T229	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T15	9		T155	13		T156	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T61	16		T186	13		T163	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T3	1		T166	3		T30	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1377	1			T8	3		T11	11		T14	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T48	5		T43	1		T249	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T161	1		T40	8		T44	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T12	1		T161	1		T236	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T1	1		T7	4		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T30	6		T162	8		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T7	13		T48	11		T33	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T6	15		T162	8		T151	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T154	1		T34	13		T186	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T40	8		T43	6		T181	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T13	2		T151	30		T186	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T1	1		T61	6		T164	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17210	1			T2	20		T4	20		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T34	4		T229	9		T88	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T3	16		T158	11		T251	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T327	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T328	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T178	7		T204	8		T168	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T15	5		T231	6		T107	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T1	9		T28	6		T229	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T15	9		T156	13		T204	22
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T61	10		T186	2		T158	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T3	21		T30	13		T228	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1266	1			T32	17		T155	15		T172	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T48	22		T249	13		T95	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T40	2		T188	9		T90	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T12	11		T329	10		T272	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T1	12		T7	12		T169	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T30	14		T162	9		T156	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T7	11		T48	13		T18	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T6	11		T162	8		T151	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T34	16		T157	2		T181	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T40	5		T43	5		T181	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T151	16		T186	9		T237	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T1	13		T61	8		T164	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22186

1

T1

3

T2

20

T3

2

auto[1]

auto[0]

4325

1

T1

34

T3

37

T6

11