Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T178	7		T231	1		T171	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T7	13		T186	11		T155	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1322	1			T8	3		T11	11		T14	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T1	2		T15	5		T227	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T6	15		T15	9		T48	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T186	13		T45	5		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T166	3		T16	1		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T117	13		T167	7		T188	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T30	12		T157	7		T100	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T3	1		T172	1		T206	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T1	1		T3	1		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T12	1		T154	1		T164	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T48	5		T16	4		T61	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T61	16		T186	2		T158	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T161	1		T162	8		T155	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T7	4		T161	1		T170	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T13	1		T162	8		T43	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T13	1		T151	11		T40	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T154	1		T228	9		T160	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T249	1		T194	10		T250	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17210	1			T2	20		T4	20		T5	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T178	7		T231	6		T40	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T7	11		T186	9		T204	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1175	1			T30	14		T32	17		T34	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T1	25		T15	5		T204	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T6	11		T15	9		T48	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T186	2		T45	1		T251	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T28	6		T237	12		T249	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T117	11		T167	6		T188	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T30	13		T157	2		T102	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T3	21		T172	15		T206	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T1	9		T3	16		T151	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T12	11		T164	16		T172	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T48	22		T61	8		T155	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T61	10		T158	10		T164	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T162	8		T156	13		T158	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T7	12		T164	15		T124	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T162	9		T43	4		T181	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T151	15		T40	5		T173	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T228	7		T254	3		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T249	15		T194	13		T250	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	458	1			T6	3		T42	1		T51	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T255	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T247	1		T248	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T231	1		T171	9		T165	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T186	11		T155	8		T157	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1312	1			T8	3		T11	11		T14	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T1	1		T7	13		T15	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T15	9		T33	1		T34	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T1	1		T227	1		T204	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T6	15		T166	3		T28	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T186	13		T45	5		T117	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T16	1		T237	2		T100	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T3	1		T167	7		T188	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T3	1		T154	1		T30	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T154	1		T61	16		T164	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T1	1		T48	5		T16	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T12	1		T158	12		T164	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T155	13		T158	18		T171	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T161	1		T186	2		T100	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	327	1			T13	1		T161	1		T154	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	426	1			T7	4		T13	1		T170	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16753	1			T2	20		T4	20		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T255	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T248	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T231	6		T40	2		T239	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T186	9		T204	8		T229	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1230	1			T48	13		T30	14		T32	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T1	12		T7	11		T15	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T15	9		T34	16		T151	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T1	13		T204	22		T17	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T6	11		T28	6		T232	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T186	2		T45	1		T117	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T237	12		T102	5		T169	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T3	21		T167	6		T188	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T3	16		T30	13		T43	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T61	10		T164	16		T172	29
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T1	9		T48	22		T61	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T12	11		T158	10		T164	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T158	15		T249	16		T256	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T234	4		T169	4		T95	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T228	7		T162	17		T156	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	376	1			T7	12		T151	15		T164	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22186

1

T1

3

T2

20

T3

2

auto[1]

auto[0]

4325

1

T1

34

T3

37

T6

11