Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26511

1

T1

37

T2

20

T3

39

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22716

1

T1

24

T2

20

T3

17

auto[ADC_CTRL_FILTER_COND_OUT]

3795

1

T1

13

T3

22

T6

26

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20105

1

T1

24

T2

20

T3

17

auto[1]

6406

1

T1

13

T3

22

T7

24

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22444

1

T1

37

T2

20

T3

39

auto[1]

4067

1

T6

15

T7

15

T11

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	13	1			T33	1		T257	12		-	-
values[0]	63	1			T258	14		T259	10		T218	15
values[1]	870	1			T3	22		T12	12		T151	15
values[2]	792	1			T7	16		T15	10		T154	1
values[3]	709	1			T48	27		T34	8		T228	16
values[4]	708	1			T7	24		T161	1		T48	24
values[5]	728	1			T6	26		T15	18		T30	1
values[6]	582	1			T161	1		T154	1		T16	4
values[7]	640	1			T1	13		T16	1		T186	20
values[8]	586	1			T166	3		T227	1		T157	1
values[9]	3610	1			T1	24		T3	17		T8	3
minimum	17210	1			T2	20		T4	20		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1246	1			T12	12		T154	1		T61	26
values[1]	615	1			T3	22		T7	16		T34	8
values[2]	704	1			T15	10		T48	27		T156	11
values[3]	713	1			T7	24		T161	1		T48	24
values[4]	724	1			T6	26		T15	18		T154	1
values[5]	555	1			T161	1		T16	4		T30	25
values[6]	2836	1			T1	13		T8	3		T11	11
values[7]	604	1			T166	3		T30	20		T157	1
values[8]	998	1			T1	10		T3	17		T13	2
values[9]	306	1			T1	14		T34	29		T173	30
minimum	17210	1			T2	20		T4	20		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22186

1

T1

3

T2

20

T3

2

auto[1]

4325

1

T1

34

T3

37

T6

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	330	1			T12	12		T154	1		T151	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	383	1			T61	11		T151	16		T155	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T7	13		T34	5		T228	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T3	22		T158	12		T223	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T164	8		T100	1		T107	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T15	6		T48	23		T156	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T161	1		T186	1		T204	23
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T7	12		T48	14		T28	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T154	1		T28	1		T61	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T6	12		T15	10		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T16	3		T155	1		T163	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T161	1		T30	14		T40	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1559	1			T8	3		T11	1		T14	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T1	13		T16	1		T158	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T166	1		T229	18		T164	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T30	15		T157	1		T47	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T1	10		T3	17		T13	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	373	1			T13	1		T154	1		T33	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T1	14		T44	1		T18	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T34	17		T173	15		T234	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17081	1			T2	20		T4	20		T5	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T151	12		T186	12		T102	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T61	15		T151	10		T155	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T7	3		T34	3		T228	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T158	11		T223	4		T230	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T164	5		T44	1		T46	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T15	4		T48	4		T156	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T186	1		T238	11		T191	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T7	12		T48	10		T155	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T61	5		T162	7		T167	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T6	14		T15	8		T102	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T16	1		T155	7		T182	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T30	11		T40	6		T43	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	993	1			T11	10		T14	8		T152	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T158	16		T260	14		T240	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T166	2		T229	16		T164	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T30	5		T47	1		T89	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T178	6		T233	2		T261	22
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T162	7		T151	16		T229	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T44	1		T18	9		T262	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T34	12		T173	15		T234	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T6	1		T16	1		T28	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T257	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T33	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T218	15		T263	1		T264	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T258	1		T259	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T12	12		T151	3		T231	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T3	22		T155	16		T156	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T7	13		T154	1		T170	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T15	6		T61	11		T151	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T34	5		T228	8		T157	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T48	23		T156	6		T43	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T161	1		T28	1		T204	23
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T7	12		T48	14		T28	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T61	9		T186	1		T172	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T6	12		T15	10		T30	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T154	1		T16	3		T162	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T161	1		T30	14		T40	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T186	10		T204	9		T163	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T1	13		T16	1		T158	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T166	1		T227	1		T229	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T157	1		T44	1		T47	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1648	1			T1	24		T3	17		T8	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	519	1			T13	1		T154	1		T30	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17081	1			T2	20		T4	20		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T257	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T264	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T258	13		T259	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T151	12		T186	12		T223	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T155	18		T164	6		T174	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T7	3		T156	10		T102	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T15	4		T61	15		T151	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T34	3		T228	8		T157	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T48	4		T156	5		T43	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T238	11		T191	4		T265	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T7	12		T48	10		T155	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T61	5		T186	1		T167	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T6	14		T15	8		T102	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T16	1		T162	7		T155	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T30	11		T43	5		T266	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T186	10		T171	8		T165	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T158	16		T40	6		T260	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T166	2		T229	16		T167	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T44	1		T47	1		T195	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1060	1			T11	10		T14	8		T152	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	383	1			T30	5		T34	12		T162	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T6	1		T16	1		T28	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	313	1			T12	1		T154	1		T151	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T61	16		T151	11		T155	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T7	4		T34	4		T228	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T3	1		T158	12		T223	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T164	6		T100	1		T107	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T15	5		T48	5		T156	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T161	1		T186	2		T204	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T7	13		T48	11		T28	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T154	1		T28	1		T61	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T6	15		T15	9		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T16	4		T155	8		T163	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T161	1		T30	12		T40	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1328	1			T8	3		T11	11		T14	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T1	1		T16	1		T158	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T166	3		T229	18		T164	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T30	6		T157	1		T47	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T1	1		T3	1		T13	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T13	1		T154	1		T33	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T1	1		T44	2		T18	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T34	13		T173	16		T234	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17210	1			T2	20		T4	20		T5	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T12	11		T151	2		T231	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T61	10		T151	15		T155	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T7	12		T34	4		T228	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T3	21		T158	11		T176	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T164	7		T107	16		T46	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T15	5		T48	22		T156	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T204	22		T215	8		T95	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T7	11		T48	13		T28	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T61	8		T162	8		T172	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T6	11		T15	9		T102	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T90	10		T240	1		T267	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T30	13		T40	2		T43	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1224	1			T32	17		T186	9		T204	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T1	12		T158	14		T215	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T229	16		T164	15		T167	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T30	14		T47	2		T268	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T1	9		T3	16		T178	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T162	9		T151	14		T229	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T1	13		T18	8		T262	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T34	16		T173	14		T234	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T257	12		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T33	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T218	1		T263	1		T264	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T258	14		T259	10		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T12	1		T151	13		T231	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T3	1		T155	19		T156	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T7	4		T154	1		T170	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T15	5		T61	16		T151	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T34	4		T228	9		T157	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T48	5		T156	6		T43	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T161	1		T28	1		T204	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T7	13		T48	11		T28	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T61	6		T186	2		T172	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T6	15		T15	9		T30	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T154	1		T16	4		T162	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T161	1		T30	12		T40	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T186	11		T204	1		T163	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T1	1		T16	1		T158	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T166	3		T227	1		T229	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T157	1		T44	2		T47	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1408	1			T1	2		T3	1		T8	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	465	1			T13	1		T154	1		T30	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17210	1			T2	20		T4	20		T5	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T218	14		T264	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T12	11		T151	2		T231	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T3	21		T155	15		T156	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T7	12		T156	13		T232	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T15	5		T61	10		T151	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T34	4		T228	7		T157	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T48	22		T156	5		T43	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T204	22		T215	8		T95	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T7	11		T48	13		T28	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T61	8		T172	14		T175	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T6	11		T15	9		T102	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T162	8		T225	8		T90	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T30	13		T43	5		T88	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T186	9		T204	8		T40	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T1	12		T158	14		T40	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T229	16		T167	6		T238	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T47	2		T215	5		T225	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1300	1			T1	22		T3	16		T32	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	437	1			T30	14		T34	16		T162	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22186

1

T1

3

T2

20

T3

2

auto[1]

auto[0]

4325

1

T1

34

T3

37

T6

11