Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26511

1

T1

37

T2

20

T3

39

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20769

1

T1

13

T2

20

T3

22

auto[ADC_CTRL_FILTER_COND_OUT]

5742

1

T1

24

T3

17

T8

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20804

1

T1

27

T2

20

T3

17

auto[1]

5707

1

T1

10

T3

22

T8

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22444

1

T1

37

T2

20

T3

39

auto[1]

4067

1

T6

15

T7

15

T11

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	16	1			T7	16		-	-		-	-
values[0]	119	1			T87	28		T269	1		T270	15
values[1]	877	1			T15	18		T16	1		T162	16
values[2]	608	1			T154	1		T16	4		T178	14
values[3]	630	1			T1	13		T161	1		T227	1
values[4]	686	1			T1	10		T3	22		T48	24
values[5]	708	1			T154	1		T156	24		T171	1
values[6]	705	1			T3	17		T13	1		T154	1
values[7]	623	1			T7	24		T161	1		T28	1
values[8]	1049	1			T34	29		T151	57		T155	8
values[9]	3280	1			T1	14		T6	26		T8	3
minimum	17210	1			T2	20		T4	20		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1121	1			T15	18		T154	1		T16	1
values[1]	2847	1			T8	3		T11	11		T14	9
values[2]	668	1			T1	13		T161	1		T227	1
values[3]	715	1			T1	10		T3	22		T48	24
values[4]	717	1			T154	1		T228	16		T44	4
values[5]	584	1			T3	17		T13	1		T154	1
values[6]	676	1			T7	24		T28	1		T33	1
values[7]	972	1			T6	26		T13	1		T161	1
values[8]	876	1			T12	12		T15	10		T166	3
values[9]	113	1			T1	14		T7	16		T48	27
minimum	17222	1			T2	20		T4	20		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22186

1

T1

3

T2

20

T3

2

auto[1]

4325

1

T1

34

T3

37

T6

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	324	1			T154	1		T204	9		T172	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T15	10		T16	1		T151	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T16	3		T34	5		T178	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1566	1			T8	3		T11	1		T14	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T1	13		T227	1		T61	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T161	1		T172	1		T128	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T3	22		T48	14		T28	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T1	10		T61	9		T171	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T44	1		T206	18		T271	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T154	1		T228	8		T44	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T154	1		T170	1		T155	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T3	17		T13	1		T231	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T7	12		T28	1		T33	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T162	10		T155	1		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	333	1			T6	12		T30	14		T34	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T13	1		T161	1		T151	31
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T15	6		T166	1		T237	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T12	12		T30	1		T186	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T7	13		T48	23		T89	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T1	14		T100	2		T182	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17082	1			T2	20		T4	20		T5	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T181	3		T45	1		T17	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T15	8		T151	12		T158	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T16	1		T34	3		T178	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1007	1			T11	10		T14	8		T152	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T61	15		T186	1		T229	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T244	3		T272	1		T273	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T48	10		T30	5		T158	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T61	5		T169	6		T266	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T44	1		T206	18		T188	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T228	8		T44	1		T167	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T155	18		T165	4		T173	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T156	10		T157	6		T171	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T7	12		T155	12		T156	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T162	7		T155	7		T158	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T6	14		T30	11		T34	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T151	26		T229	14		T234	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T15	4		T166	2		T237	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T186	10		T238	10		T230	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T7	3		T48	4		T274	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T182	6		T275	8		T276	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T6	1		T16	1		T28	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T7	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T87	15		T277	16		T278	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T269	1		T270	15		T200	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T204	9		T172	15		T181	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T15	10		T16	1		T162	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T154	1		T16	3		T178	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T40	1		T190	1		T89	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T1	13		T227	1		T34	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T161	1		T172	1		T128	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T3	22		T48	14		T28	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T1	10		T61	9		T220	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T206	18		T271	1		T188	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T154	1		T156	14		T171	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T154	1		T170	1		T165	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T3	17		T13	1		T228	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T7	12		T28	1		T30	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T161	1		T162	10		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	337	1			T34	17		T175	13		T225	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T151	31		T155	1		T204	23
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	338	1			T6	12		T15	6		T166	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1627	1			T1	14		T8	3		T11	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17081	1			T2	20		T4	20		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T7	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T87	13		T278	9		T279	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T200	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T181	3		T45	1		T17	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T15	8		T162	7		T151	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T16	1		T178	6		T186	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T184	11		T230	13		T268	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T34	3		T61	15		T186	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T89	2		T266	8		T207	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T48	10		T30	5		T158	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T61	5		T169	6		T280	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T206	18		T188	10		T93	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T156	10		T44	1		T168	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T165	4		T44	1		T182	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T228	8		T157	6		T43	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T7	12		T30	11		T155	30
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T162	7		T158	11		T171	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T34	12		T175	8		T236	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T151	26		T155	7		T229	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T6	14		T15	4		T166	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1072	1			T11	10		T14	8		T152	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T6	1		T16	1		T28	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T154	1		T204	1		T172	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T15	9		T16	1		T151	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T16	4		T34	4		T178	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1343	1			T8	3		T11	11		T14	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T1	1		T227	1		T61	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T161	1		T172	1		T128	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T3	1		T48	11		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T1	1		T61	6		T171	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T44	2		T206	19		T271	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T154	1		T228	9		T44	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T154	1		T170	1		T155	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T3	1		T13	1		T231	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T7	13		T28	1		T33	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T162	8		T155	8		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T6	15		T30	12		T34	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T13	1		T161	1		T151	28
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T15	5		T166	3		T237	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T12	1		T30	1		T186	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T7	4		T48	5		T89	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T1	1		T100	2		T182	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17222	1			T2	20		T4	20		T5	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T204	8		T172	14		T181	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T15	9		T151	2		T156	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T34	4		T178	7		T186	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1230	1			T32	17		T162	8		T126	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T1	12		T61	10		T229	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T215	8		T176	6		T244	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T3	21		T48	13		T28	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T1	9		T61	8		T169	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T206	17		T188	9		T215	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T228	7		T168	11		T267	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T155	15		T173	14		T281	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T3	16		T231	6		T156	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T7	11		T156	5		T238	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T162	9		T204	22		T158	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T6	11		T30	13		T34	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T151	29		T229	14		T234	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T15	5		T237	12		T229	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T12	11		T186	9		T93	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T7	12		T48	22		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T1	13		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T7	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T87	14		T277	1		T278	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T269	1		T270	1		T200	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T204	1		T172	1		T181	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T15	9		T16	1		T162	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T154	1		T16	4		T178	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T40	1		T190	1		T89	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T1	1		T227	1		T34	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T161	1		T172	1		T128	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T3	1		T48	11		T28	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T1	1		T61	6		T220	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T206	19		T271	1		T188	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T154	1		T156	11		T171	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T154	1		T170	1		T165	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T3	1		T13	1		T228	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T7	13		T28	1		T30	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T161	1		T162	8		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T34	13		T175	9		T225	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T151	28		T155	8		T204	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T6	15		T15	5		T166	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1423	1			T1	1		T8	3		T11	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17210	1			T2	20		T4	20		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T7	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T87	14		T277	15		T278	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T270	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T204	8		T172	14		T181	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T15	9		T162	8		T151	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T178	7		T186	2		T181	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T184	11		T230	11		T268	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T1	12		T34	4		T61	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T215	8		T176	6		T88	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T3	21		T48	13		T28	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T1	9		T61	8		T169	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T206	17		T188	9		T215	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T156	13		T168	11		T88	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T249	15		T281	16		T265	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T3	16		T228	7		T231	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T7	11		T30	13		T155	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T162	9		T158	11		T172	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T34	16		T175	12		T225	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T151	29		T204	22		T229	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T6	11		T15	5		T48	22
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1276	1			T1	13		T12	11		T32	17

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22186

1

T1

3

T2

20

T3

2

auto[1]

auto[0]

4325

1

T1

34

T3

37

T6

11