Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26511

1

T1

37

T2

20

T3

39

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22889

1

T1

10

T2

20

T3

17

auto[ADC_CTRL_FILTER_COND_OUT]

3622

1

T1

27

T3

22

T6

26

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20680

1

T1

23

T2

20

T4

20

auto[1]

5831

1

T1

14

T3

39

T7

24

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22444

1

T1

37

T2

20

T3

39

auto[1]

4067

1

T6

15

T7

15

T11

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	23	1			T282	23		-	-		-	-
values[0]	72	1			T164	23		T236	9		T283	17
values[1]	711	1			T161	1		T166	3		T33	1
values[2]	547	1			T13	1		T15	18		T48	27
values[3]	772	1			T1	23		T16	4		T28	1
values[4]	746	1			T3	22		T7	40		T154	1
values[5]	2974	1			T8	3		T11	11		T13	1
values[6]	696	1			T30	20		T151	31		T231	7
values[7]	743	1			T6	26		T162	17		T157	10
values[8]	723	1			T161	1		T154	1		T227	1
values[9]	1294	1			T1	14		T3	17		T12	12
minimum	17210	1			T2	20		T4	20		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	900	1			T161	1		T166	3		T33	1
values[1]	582	1			T1	13		T13	1		T15	18
values[2]	835	1			T1	10		T7	24		T154	1
values[3]	2896	1			T3	22		T7	16		T8	3
values[4]	765	1			T13	1		T48	24		T151	57
values[5]	596	1			T30	20		T162	17		T231	7
values[6]	843	1			T6	26		T227	1		T30	25
values[7]	830	1			T3	17		T161	1		T154	2
values[8]	887	1			T1	14		T12	12		T15	10
values[9]	139	1			T162	16		T158	22		T41	3
minimum	17238	1			T2	20		T4	20		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22186

1

T1

3

T2

20

T3

2

auto[1]

4325

1

T1

34

T3

37

T6

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T161	1		T33	1		T228	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T166	1		T158	12		T171	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T15	10		T48	23		T229	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T1	13		T13	1		T34	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T1	10		T7	12		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T61	11		T155	16		T271	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1547	1			T7	13		T8	3		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T3	22		T28	7		T158	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T13	1		T151	15		T157	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T48	14		T151	16		T156	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T162	10		T169	5		T87	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T30	15		T231	7		T204	23
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T227	1		T30	14		T157	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T6	12		T61	9		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T3	17		T161	1		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T154	1		T170	1		T186	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T155	1		T156	14		T102	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T1	14		T12	12		T15	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T284	13		T285	9		T286	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T162	9		T158	11		T41	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17081	1			T2	20		T4	20		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T236	1		T287	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T228	8		T229	6		T164	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T166	2		T158	11		T171	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T15	8		T48	4		T229	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T34	12		T186	1		T43	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T7	12		T16	1		T178	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T61	15		T155	18		T223	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	974	1			T7	3		T11	10		T14	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T158	5		T165	4		T262	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T151	16		T167	6		T266	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T48	10		T151	10		T256	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T162	7		T169	6		T87	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T30	5		T102	8		T288	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T30	11		T157	6		T164	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T6	14		T61	5		T181	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T155	7		T173	13		T188	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T186	12		T156	5		T117	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T155	12		T156	10		T102	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T15	4		T34	3		T40	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T285	8		T286	4		T255	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T162	7		T158	11		T44	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T6	1		T16	1		T28	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T236	8		T287	9		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T282	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T289	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T164	17		T236	1		T283	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T161	1		T33	1		T228	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T166	1		T158	12		T168	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T15	10		T48	23		T151	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T13	1		T34	17		T186	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T1	10		T16	3		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T1	13		T61	11		T155	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T7	25		T154	1		T178	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T3	22		T28	7		T158	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1552	1			T8	3		T11	1		T13	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T48	14		T151	16		T204	23
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T151	15		T167	7		T169	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T30	15		T231	7		T156	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T162	10		T157	3		T164	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T6	12		T157	1		T181	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T161	1		T154	1		T227	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T61	9		T170	1		T186	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	404	1			T3	17		T155	1		T156	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	344	1			T1	14		T12	12		T15	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17081	1			T2	20		T4	20		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T282	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T164	6		T236	8		T283	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T228	8		T229	8		T164	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T166	2		T158	11		T168	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T15	8		T48	4		T151	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T34	12		T186	1		T171	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T16	1		T237	1		T229	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T61	15		T155	18		T18	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T7	15		T178	6		T186	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T158	5		T165	4		T290	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	969	1			T11	10		T14	8		T152	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T48	10		T151	10		T256	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T151	16		T167	6		T169	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T30	5		T102	8		T184	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T162	7		T157	6		T164	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T6	14		T181	3		T108	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T30	11		T155	7		T188	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T61	5		T186	12		T167	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T155	12		T156	10		T102	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T15	4		T34	3		T162	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T6	1		T16	1		T28	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T161	1		T33	1		T228	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T166	3		T158	12		T171	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T15	9		T48	5		T229	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T1	1		T13	1		T34	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T1	1		T7	13		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T61	16		T155	19		T271	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1319	1			T7	4		T8	3		T11	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T3	1		T28	1		T158	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T13	1		T151	17		T157	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T48	11		T151	11		T156	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T162	8		T169	7		T87	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T30	6		T231	1		T204	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T227	1		T30	12		T157	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T6	15		T61	6		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T3	1		T161	1		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T154	1		T170	1		T186	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T155	13		T156	11		T102	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T1	1		T12	1		T15	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T284	1		T285	9		T286	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T162	8		T158	12		T41	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17210	1			T2	20		T4	20		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T236	9		T287	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T228	7		T229	9		T164	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T158	11		T164	16		T168	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T15	9		T48	22		T229	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T1	12		T34	16		T232	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T1	9		T7	11		T178	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T61	10		T155	15		T246	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1202	1			T7	12		T32	17		T186	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T3	21		T28	6		T158	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T151	14		T107	16		T167	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T48	13		T151	15		T156	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T162	9		T169	4		T87	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T30	14		T231	6		T204	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T30	13		T157	2		T164	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T6	11		T61	8		T181	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T3	16		T173	14		T188	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T186	2		T156	5		T117	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T156	13		T102	5		T17	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T1	13		T12	11		T15	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T284	12		T285	8		T286	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T162	8		T158	10		T35	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T287	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T282	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T289	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T164	7		T236	9		T283	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T161	1		T33	1		T228	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T166	3		T158	12		T168	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T15	9		T48	5		T151	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T13	1		T34	13		T186	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T1	1		T16	4		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T1	1		T61	16		T155	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T7	17		T154	1		T178	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T3	1		T28	1		T158	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1306	1			T8	3		T11	11		T13	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T48	11		T151	11		T204	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T151	17		T167	7		T169	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T30	6		T231	1		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T162	8		T157	7		T164	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T6	15		T157	1		T181	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T161	1		T154	1		T227	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T61	6		T170	1		T186	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	367	1			T3	1		T155	13		T156	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T1	1		T12	1		T15	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17210	1			T2	20		T4	20		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T282	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T164	16		T291	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T228	7		T229	11		T164	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T158	11		T168	11		T215	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T15	9		T48	22		T151	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T34	16		T43	4		T174	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T1	9		T237	12		T229	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T1	12		T61	10		T155	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T7	23		T178	7		T186	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T3	21		T28	6		T158	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1215	1			T32	17		T107	16		T43	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T48	13		T151	15		T204	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T151	14		T167	6		T169	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T30	14		T231	6		T156	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T162	9		T157	2		T164	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T6	11		T181	3		T189	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T30	13		T188	9		T47	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T61	8		T186	2		T189	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	341	1			T3	16		T156	13		T102	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T1	13		T12	11		T15	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22186

1

T1

3

T2

20

T3

2

auto[1]

auto[0]

4325

1

T1

34

T3

37

T6

11