Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26511

1

T1

37

T2

20

T3

39

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22895

1

T1

24

T2

20

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3616

1

T1

13

T3

39

T6

26

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20604

1

T1

24

T2

20

T4

20

auto[1]

5907

1

T1

13

T3

39

T6

26

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22444

1

T1

37

T2

20

T3

39

auto[1]

4067

1

T6

15

T7

15

T11

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	7	1			T181	7		-	-		-	-
values[0]	139	1			T13	1		T161	1		T174	19
values[1]	744	1			T7	16		T15	18		T154	1
values[2]	674	1			T3	17		T178	14		T186	2
values[3]	728	1			T157	1		T204	9		T171	1
values[4]	586	1			T161	1		T228	16		T170	1
values[5]	2910	1			T1	23		T3	22		T6	26
values[6]	764	1			T227	1		T28	7		T30	25
values[7]	638	1			T34	8		T162	16		T164	30
values[8]	640	1			T1	14		T12	12		T13	1
values[9]	1471	1			T15	10		T166	3		T48	24
minimum	17210	1			T2	20		T4	20		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	956	1			T7	16		T13	1		T15	18
values[1]	771	1			T61	14		T178	14		T186	2
values[2]	675	1			T3	17		T228	16		T204	9
values[3]	2806	1			T8	3		T11	11		T14	9
values[4]	847	1			T1	23		T3	22		T6	26
values[5]	651	1			T28	7		T33	1		T162	17
values[6]	648	1			T12	12		T30	20		T34	8
values[7]	667	1			T1	14		T13	1		T48	27
values[8]	1197	1			T15	10		T166	3		T48	24
values[9]	64	1			T157	1		T181	7		T271	1
minimum	17229	1			T2	20		T4	20		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22186

1

T1

3

T2

20

T3

2

auto[1]

4325

1

T1

34

T3

37

T6

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T15	10		T16	3		T28	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T7	13		T13	1		T161	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T186	1		T172	16		T40	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T61	9		T178	8		T164	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T228	8		T171	1		T181	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T3	17		T204	9		T117	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1484	1			T8	3		T11	1		T14	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T154	1		T157	1		T43	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T1	10		T7	12		T227	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T1	13		T3	22		T6	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T33	1		T162	10		T231	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T28	7		T164	33		T107	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T12	12		T30	15		T151	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T34	5		T172	15		T102	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T1	14		T13	1		T48	23
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T162	9		T158	12		T46	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T186	10		T156	20		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	351	1			T15	6		T166	1		T48	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T157	1		T271	1		T292	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T181	4		T194	1		T198	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17082	1			T2	20		T4	20		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T20	2		T264	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T15	8		T16	1		T151	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T7	3		T155	12		T40	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T186	1		T173	15		T167	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T61	5		T178	6		T164	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T228	8		T181	19		T47	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T117	12		T290	3		T293	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	990	1			T11	10		T14	8		T152	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T43	4		T44	2		T167	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T7	12		T229	6		T158	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T6	14		T30	11		T151	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T162	7		T44	1		T294	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T164	20		T245	11		T233	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T30	5		T151	10		T229	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T34	3		T102	8		T168	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T48	4		T61	15		T186	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T162	7		T158	11		T46	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T186	10		T156	15		T206	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	346	1			T15	4		T166	2		T48	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T295	13		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T181	3		T194	10		T274	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T6	1		T16	1		T28	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T20	1		T264	8		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T181	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T174	10		T183	1		T296	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T13	1		T161	1		T18	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T15	10		T16	3		T28	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T7	13		T154	1		T61	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T186	1		T237	13		T40	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T3	17		T178	8		T128	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T171	1		T172	16		T181	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T157	1		T204	9		T164	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T161	1		T228	8		T229	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T170	1		T44	1		T117	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1588	1			T1	10		T7	12		T8	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T1	13		T3	22		T6	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T227	1		T33	1		T162	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T28	7		T30	14		T164	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T41	3		T215	9		T297	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T34	5		T162	9		T164	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T1	14		T12	12		T13	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T172	15		T102	9		T46	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	317	1			T186	10		T156	20		T157	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	423	1			T15	6		T166	1		T48	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17081	1			T2	20		T4	20		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T181	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T174	9		T298	12		T299	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T18	9		T300	18		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T15	8		T16	1		T151	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T7	3		T61	5		T155	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T186	1		T237	1		T173	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T178	6		T252	3		T182	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T181	19		T47	1		T238	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T164	5		T165	4		T102	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T228	8		T229	6		T158	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T44	1		T117	12		T167	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1004	1			T7	12		T11	10		T14	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T6	14		T151	12		T43	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T162	7		T151	10		T44	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T30	11		T164	6		T40	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T238	11		T286	15		T208	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T34	3		T162	7		T164	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T48	4		T30	5		T61	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T102	8		T46	1		T168	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T186	10		T156	15		T157	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	425	1			T15	4		T166	2		T48	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T6	1		T16	1		T28	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T15	9		T16	4		T28	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T7	4		T13	1		T161	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T186	2		T172	1		T40	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T61	6		T178	7		T164	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T228	9		T171	1		T181	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T3	1		T204	1		T117	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1317	1			T8	3		T11	11		T14	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T154	1		T157	1		T43	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T1	1		T7	13		T227	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T1	1		T3	1		T6	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T33	1		T162	8		T231	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T28	1		T164	22		T107	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T12	1		T30	6		T151	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T34	4		T172	1		T102	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T1	1		T13	1		T48	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T162	8		T158	12		T46	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T186	11		T156	17		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	397	1			T15	5		T166	3		T48	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T157	1		T271	1		T292	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T181	4		T194	11		T198	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17211	1			T2	20		T4	20		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T20	2		T264	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T15	9		T151	14		T232	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T7	12		T40	2		T43	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T172	15		T173	14		T167	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T61	8		T178	7		T164	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T228	7		T181	14		T47	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T3	16		T204	8		T117	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1157	1			T32	17		T126	11		T111	33
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T43	4		T249	13		T256	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T1	9		T7	11		T229	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T1	12		T3	21		T6	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T162	9		T231	6		T204	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T28	6		T164	31		T107	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T12	11		T30	14		T151	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T34	4		T172	14		T102	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T1	13		T48	22		T61	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T162	8		T158	11		T46	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T186	9		T156	18		T206	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T15	5		T48	13		T34	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T292	1		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T181	3		T198	10		T301	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T20	1		T264	6		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T181	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T174	10		T183	1		T296	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T13	1		T161	1		T18	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T15	9		T16	4		T28	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T7	4		T154	1		T61	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T186	2		T237	2		T40	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T3	1		T178	7		T128	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T171	1		T172	1		T181	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T157	1		T204	1		T164	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T161	1		T228	9		T229	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T170	1		T44	2		T117	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1342	1			T1	1		T7	13		T8	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T1	1		T3	1		T6	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T227	1		T33	1		T162	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T28	1		T30	12		T164	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T41	3		T215	1		T297	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T34	4		T162	8		T164	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T1	1		T12	1		T13	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T172	1		T102	9		T46	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	372	1			T186	11		T156	17		T157	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	490	1			T15	5		T166	3		T48	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17210	1			T2	20		T4	20		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T181	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T174	9		T298	12		T299	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T18	8		T277	15		T302	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T15	9		T151	14		T232	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T7	12		T61	8		T40	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T237	12		T173	14		T167	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T3	16		T178	7		T252	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T172	15		T181	14		T47	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T204	8		T164	7		T102	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T228	7		T229	9		T158	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T117	11		T249	13		T246	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1250	1			T1	9		T7	11		T32	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T1	12		T3	21		T6	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T162	9		T151	15		T231	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T28	6		T30	13		T164	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T215	8		T95	6		T238	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T34	4		T162	8		T164	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T1	13		T12	11		T48	22
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T172	14		T102	8		T46	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T186	9		T156	18		T157	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	358	1			T15	5		T48	13		T34	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22186

1

T1

3

T2

20

T3

2

auto[1]

auto[0]

4325

1

T1

34

T3

37

T6

11