Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26511

1

T1

37

T2

20

T3

39

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23158

1

T1

10

T2

20

T3

17

auto[ADC_CTRL_FILTER_COND_OUT]

3353

1

T1

27

T3

22

T6

26

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20779

1

T1

37

T2

20

T4

20

auto[1]

5732

1

T3

39

T7

24

T8

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22444

1

T1

37

T2

20

T3

39

auto[1]

4067

1

T6

15

T7

15

T11

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	178	1			T12	12		T40	10		T128	1
values[0]	27	1			T291	22		T303	5		-	-
values[1]	765	1			T161	1		T166	3		T33	1
values[2]	547	1			T13	1		T15	18		T48	27
values[3]	764	1			T1	23		T16	4		T28	1
values[4]	822	1			T3	22		T7	40		T154	1
values[5]	2923	1			T8	3		T11	11		T13	1
values[6]	658	1			T30	20		T231	7		T156	11
values[7]	799	1			T6	26		T61	14		T162	17
values[8]	669	1			T161	1		T154	1		T227	1
values[9]	1149	1			T1	14		T3	17		T15	10
minimum	17210	1			T2	20		T4	20		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	640	1			T161	1		T166	3		T228	16
values[1]	568	1			T13	1		T15	18		T48	27
values[2]	871	1			T1	23		T7	24		T154	1
values[3]	2876	1			T3	22		T7	16		T8	3
values[4]	810	1			T13	1		T48	24		T151	57
values[5]	577	1			T30	20		T162	17		T102	17
values[6]	824	1			T6	26		T227	1		T30	25
values[7]	765	1			T161	1		T154	2		T186	15
values[8]	980	1			T1	14		T3	17		T12	12
values[9]	104	1			T158	22		T40	10		T41	3
minimum	17496	1			T2	20		T4	20		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22186

1

T1

3

T2

20

T3

2

auto[1]

4325

1

T1

34

T3

37

T6

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T161	1		T166	1		T228	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T186	1		T158	12		T171	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T13	1		T15	10		T48	23
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T34	17		T174	10		T36	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T1	10		T7	12		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T1	13		T61	11		T155	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1576	1			T7	13		T8	3		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T3	22		T28	7		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T13	1		T151	15		T157	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T48	14		T151	16		T231	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T102	9		T87	15		T268	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T30	15		T162	10		T189	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T227	1		T30	14		T157	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T6	12		T61	9		T170	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T161	1		T154	1		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T154	1		T186	3		T156	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	396	1			T3	17		T155	1		T156	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T1	14		T12	12		T15	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T158	11		T284	13		T255	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T40	4		T41	3		T92	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17169	1			T2	20		T4	20		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T164	16		T236	1		T287	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T166	2		T228	8		T229	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T186	1		T158	11		T171	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T15	8		T48	4		T229	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T34	12		T174	9		T36	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T7	12		T16	1		T178	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T61	15		T155	18		T124	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	988	1			T7	3		T11	10		T14	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T158	5		T165	4		T262	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T151	16		T260	4		T65	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T48	10		T151	10		T167	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T102	8		T87	13		T268	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T30	5		T162	7		T169	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T30	11		T157	6		T164	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T6	14		T61	5		T181	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T155	7		T117	12		T188	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T186	12		T156	5		T252	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T155	12		T156	10		T102	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T15	4		T34	3		T162	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T158	11		T255	7		T295	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T40	6		T285	8		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T6	1		T16	1		T28	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T164	14		T236	8		T287	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T128	1		T245	16		T238	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T12	12		T40	4		T44	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T291	11		T303	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T161	1		T166	1		T33	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T158	12		T171	1		T164	33
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T13	1		T15	10		T48	23
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T34	17		T186	1		T174	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T1	10		T16	3		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T1	13		T30	1		T61	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	316	1			T7	25		T154	1		T178	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T3	22		T28	7		T158	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1579	1			T8	3		T11	1		T13	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T48	14		T151	16		T204	23
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T102	9		T87	15		T88	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T30	15		T231	7		T156	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T157	3		T164	8		T172	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T6	12		T61	9		T162	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T161	1		T154	1		T227	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T170	1		T186	3		T189	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	431	1			T3	17		T155	1		T156	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T1	14		T15	6		T154	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17081	1			T2	20		T4	20		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T245	11		T238	2		T304	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T40	6		T44	1		T45	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T291	11		T303	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T166	2		T228	8		T229	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T158	11		T171	8		T164	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T15	8		T48	4		T43	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T34	12		T186	1		T174	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T16	1		T151	12		T229	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T61	15		T155	18		T124	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T7	15		T178	6		T186	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T158	5		T165	4		T89	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	981	1			T11	10		T14	8		T152	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T48	10		T151	10		T256	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T102	8		T87	13		T268	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T30	5		T167	6		T169	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T157	6		T164	5		T173	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T6	14		T61	5		T162	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T30	11		T155	7		T188	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T186	12		T252	3		T238	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T155	12		T156	10		T158	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T15	4		T34	3		T162	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T6	1		T16	1		T28	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T161	1		T166	3		T228	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T186	2		T158	12		T171	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T13	1		T15	9		T48	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T34	13		T174	10		T36	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T1	1		T7	13		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T1	1		T61	16		T155	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1332	1			T7	4		T8	3		T11	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T3	1		T28	1		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T13	1		T151	17		T157	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T48	11		T151	11		T231	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T102	9		T87	14		T268	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T30	6		T162	8		T189	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T227	1		T30	12		T157	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T6	15		T61	6		T170	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T161	1		T154	1		T155	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T154	1		T186	13		T156	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	326	1			T3	1		T155	13		T156	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T1	1		T12	1		T15	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T158	12		T284	1		T255	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T40	8		T41	3		T92	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17315	1			T2	20		T4	20		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T164	15		T236	9		T287	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T228	7		T229	11		T172	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T158	11		T164	16		T168	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T15	9		T48	22		T229	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T34	16		T174	9		T18	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T1	9		T7	11		T178	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T1	12		T61	10		T155	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1232	1			T7	12		T32	17		T186	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T3	21		T28	6		T158	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T151	14		T107	16		T249	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T48	13		T151	15		T231	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T102	8		T87	14		T268	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T30	14		T162	9		T189	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T30	13		T157	2		T164	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T6	11		T61	8		T181	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T117	11		T188	9		T47	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T186	2		T156	5		T252	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	340	1			T3	16		T156	13		T102	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T1	13		T12	11		T15	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T158	10		T284	12		T305	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T40	2		T285	8		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T241	11		T306	13		T208	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T164	15		T287	9		T24	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T128	1		T245	12		T238	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T12	1		T40	8		T44	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T291	12		T303	5		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T161	1		T166	3		T33	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T158	12		T171	9		T164	22
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T13	1		T15	9		T48	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T34	13		T186	2		T174	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T1	1		T16	4		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T1	1		T30	1		T61	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T7	17		T154	1		T178	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T3	1		T28	1		T158	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1316	1			T8	3		T11	11		T13	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T48	11		T151	11		T204	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T102	9		T87	14		T88	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T30	6		T231	1		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T157	7		T164	6		T172	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T6	15		T61	6		T162	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T161	1		T154	1		T227	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T170	1		T186	13		T189	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	374	1			T3	1		T155	13		T156	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T1	1		T15	5		T154	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17210	1			T2	20		T4	20		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T245	15		T238	8		T304	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T12	11		T40	2		T45	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T291	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T228	7		T229	11		T172	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T158	11		T164	31		T168	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T15	9		T48	22		T43	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T34	16		T174	9		T18	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T1	9		T151	2		T229	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T1	12		T61	10		T155	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T7	23		T178	7		T186	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T3	21		T28	6		T158	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1244	1			T32	17		T151	14		T107	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T48	13		T151	15		T204	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T102	8		T87	14		T88	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T30	14		T231	6		T156	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T157	2		T164	7		T172	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T6	11		T61	8		T162	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T30	13		T188	9		T47	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T186	2		T189	1		T252	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	368	1			T3	16		T156	13		T158	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T1	13		T15	5		T34	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22186

1

T1

3

T2

20

T3

2

auto[1]

auto[0]

4325

1

T1

34

T3

37

T6

11