Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26511

1

T1

37

T2

20

T3

39

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22748

1

T2

20

T3

22

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3763

1

T1

37

T3

17

T6

26

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20302

1

T1

27

T2

20

T3

39

auto[1]

6209

1

T1

10

T6

26

T7

40

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22444

1

T1

37

T2

20

T3

39

auto[1]

4067

1

T6

15

T7

15

T11

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	391	1			T15	18		T166	3		T158	22
values[0]	21	1			T157	9		T158	10		T307	2
values[1]	903	1			T48	24		T30	46		T33	1
values[2]	3108	1			T7	24		T8	3		T11	11
values[3]	590	1			T1	24		T3	22		T12	12
values[4]	620	1			T28	7		T228	16		T164	23
values[5]	554	1			T156	11		T157	1		T229	45
values[6]	776	1			T3	17		T13	1		T161	1
values[7]	742	1			T6	26		T154	1		T48	27
values[8]	619	1			T7	16		T13	1		T28	1
values[9]	977	1			T1	13		T15	10		T16	1
minimum	17210	1			T2	20		T4	20		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	799	1			T30	45		T33	1		T34	29
values[1]	3139	1			T1	14		T7	24		T8	3
values[2]	502	1			T1	10		T3	22		T12	12
values[3]	674	1			T228	16		T157	1		T164	23
values[4]	573	1			T154	1		T156	11		T229	45
values[5]	787	1			T3	17		T13	1		T161	1
values[6]	692	1			T6	26		T154	1		T48	27
values[7]	735	1			T7	16		T13	1		T28	1
values[8]	853	1			T1	13		T15	10		T166	3
values[9]	240	1			T15	18		T158	22		T44	2
minimum	17517	1			T2	20		T4	20		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22186

1

T1

3

T2

20

T3

2

auto[1]

4325

1

T1

34

T3

37

T6

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T30	15		T33	1		T34	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T30	14		T178	8		T186	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1517	1			T8	3		T11	1		T14	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	364	1			T1	14		T7	12		T161	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T3	22		T151	16		T238	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T1	10		T12	12		T227	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T228	8		T172	1		T43	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T157	1		T164	17		T230	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T156	11		T229	25		T165	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T154	1		T173	15		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T13	1		T204	23		T171	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T3	17		T161	1		T151	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T48	23		T170	1		T17	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T6	12		T154	1		T61	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T28	1		T163	1		T206	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T7	13		T13	1		T162	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T16	1		T155	17		T232	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T1	13		T15	6		T166	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T233	1		T194	13		T308	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T15	10		T158	11		T44	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17185	1			T2	20		T4	20		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T30	1		T157	3		T223	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T30	5		T34	12		T171	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T30	11		T178	6		T186	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	948	1			T11	10		T14	8		T152	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T7	12		T16	1		T151	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T151	10		T238	11		T240	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T156	5		T40	3		T223	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T228	8		T43	5		T44	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T164	6		T230	1		T235	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T229	20		T165	4		T181	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T173	13		T89	2		T93	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T173	15		T168	14		T236	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T151	16		T124	13		T117	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T48	4		T36	16		T188	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T6	14		T61	5		T237	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T206	18		T238	10		T239	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T7	3		T162	7		T158	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T155	30		T229	2		T188	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T15	4		T166	2		T61	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T194	16		T309	9		T257	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T15	8		T158	11		T44	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T6	1		T48	10		T16	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T157	6		T223	4		T245	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T188	10		T249	16		T176	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T15	10		T166	1		T158	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T157	3		T158	5		T307	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T48	14		T30	15		T33	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T30	15		T178	8		T186	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1538	1			T8	3		T11	1		T14	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T7	12		T161	1		T16	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T3	22		T154	1		T151	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T1	24		T12	12		T227	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T228	8		T172	1		T43	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T28	7		T164	17		T241	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T156	11		T229	25		T165	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T157	1		T173	15		T215	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T13	1		T171	1		T168	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T3	17		T161	1		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T48	23		T204	23		T100	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T6	12		T154	1		T61	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T28	1		T170	1		T169	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T7	13		T13	1		T162	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T16	1		T155	17		T232	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T1	13		T15	6		T61	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17081	1			T2	20		T4	20		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T188	10		T207	4		T244	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T15	8		T166	2		T158	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T157	6		T158	5		T307	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T48	10		T30	5		T34	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T30	11		T178	6		T186	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	968	1			T11	10		T14	8		T152	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T7	12		T16	1		T151	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T151	10		T192	8		T240	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T156	5		T40	3		T223	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T228	8		T43	5		T45	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T164	6		T241	12		T242	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T229	20		T165	4		T181	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T173	13		T243	1		T230	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T168	14		T236	8		T182	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T151	16		T124	13		T117	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T48	4		T173	15		T36	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T6	14		T61	5		T47	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T238	10		T239	12		T184	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T7	3		T162	7		T237	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T155	30		T229	2		T206	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T15	4		T61	15		T162	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T6	1		T16	1		T28	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T30	6		T33	1		T34	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T30	12		T178	7		T186	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1280	1			T8	3		T11	11		T14	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	362	1			T1	1		T7	13		T161	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T3	1		T151	11		T238	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T1	1		T12	1		T227	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T228	9		T172	1		T43	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T157	1		T164	7		T230	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T156	1		T229	22		T165	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T154	1		T173	14		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T13	1		T204	1		T171	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T3	1		T161	1		T151	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T48	5		T170	1		T17	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T6	15		T154	1		T61	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T28	1		T163	1		T206	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T7	4		T13	1		T162	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T16	1		T155	32		T232	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T1	1		T15	5		T166	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T233	1		T194	17		T308	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T15	9		T158	12		T44	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17296	1			T2	20		T4	20		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T30	1		T157	7		T223	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T30	14		T34	16		T204	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T30	13		T178	7		T186	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1185	1			T32	17		T34	4		T164	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T1	13		T7	11		T151	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T3	21		T151	15		T238	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T1	9		T12	11		T28	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T228	7		T43	5		T45	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T164	16		T242	12		T244	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T156	10		T229	23		T107	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T173	14		T215	8		T93	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T204	22		T173	14		T168	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T3	16		T151	14		T172	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T48	22		T188	5		T169	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T6	11		T61	8		T231	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T206	17		T183	11		T238	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T7	12		T162	8		T158	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T155	15		T232	9		T229	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T1	12		T15	5		T61	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T194	12		T309	13		T310	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T15	9		T158	10		T46	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T48	13		T234	4		T290	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T157	2		T245	15		T281	16

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T188	11		T249	1		T176	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T15	9		T166	3		T158	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T157	7		T158	6		T307	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T48	11		T30	6		T33	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T30	13		T178	7		T186	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1317	1			T8	3		T11	11		T14	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	348	1			T7	13		T161	1		T16	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T3	1		T154	1		T151	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T1	2		T12	1		T227	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T228	9		T172	1		T43	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T28	1		T164	7		T241	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T156	1		T229	22		T165	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T157	1		T173	14		T215	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T13	1		T171	1		T168	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T3	1		T161	1		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T48	5		T204	1		T100	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T6	15		T154	1		T61	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T28	1		T170	1		T169	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T7	4		T13	1		T162	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T16	1		T155	32		T232	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T1	1		T15	5		T61	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17210	1			T2	20		T4	20		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T188	9		T249	15		T176	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T15	9		T158	10		T164	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T157	2		T158	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T48	13		T30	14		T34	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T30	13		T178	7		T186	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1189	1			T32	17		T34	4		T204	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T7	11		T151	2		T156	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T3	21		T151	15		T192	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T1	22		T12	11		T156	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T228	7		T43	5		T45	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T28	6		T164	16		T241	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T156	10		T229	23		T107	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T173	14		T215	8		T243	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T168	11		T108	5		T191	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T3	16		T151	14		T172	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T48	22		T204	22		T173	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T6	11		T61	8		T231	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T169	7		T183	11		T238	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T7	12		T162	8		T237	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T155	15		T232	9		T229	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T1	12		T15	5		T61	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22186

1

T1

3

T2

20

T3

2

auto[1]

auto[0]

4325

1

T1

34

T3

37

T6

11