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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.74 99.07 96.67 100.00 100.00 98.83 98.33 91.27


Total test records in report: 918
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T793 /workspace/coverage/default/2.adc_ctrl_smoke.2352524068 Jun 05 05:25:39 PM PDT 24 Jun 05 05:25:42 PM PDT 24 6085860848 ps
T794 /workspace/coverage/default/23.adc_ctrl_lowpower_counter.2106038742 Jun 05 05:27:33 PM PDT 24 Jun 05 05:29:18 PM PDT 24 45020317007 ps
T795 /workspace/coverage/default/25.adc_ctrl_alert_test.3546802560 Jun 05 05:28:03 PM PDT 24 Jun 05 05:28:04 PM PDT 24 352505471 ps
T57 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2012534125 Jun 05 05:52:42 PM PDT 24 Jun 05 05:52:58 PM PDT 24 4640884914 ps
T796 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.4170620100 Jun 05 05:53:07 PM PDT 24 Jun 05 05:53:09 PM PDT 24 598641233 ps
T60 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3276775889 Jun 05 05:52:45 PM PDT 24 Jun 05 05:52:48 PM PDT 24 443142435 ps
T66 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1389315052 Jun 05 05:52:49 PM PDT 24 Jun 05 05:52:51 PM PDT 24 470672680 ps
T62 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3636058720 Jun 05 05:52:51 PM PDT 24 Jun 05 05:53:13 PM PDT 24 8529163183 ps
T71 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2980176417 Jun 05 05:53:04 PM PDT 24 Jun 05 05:53:07 PM PDT 24 437267087 ps
T58 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2965280774 Jun 05 05:52:39 PM PDT 24 Jun 05 05:52:44 PM PDT 24 2538077794 ps
T144 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.490154292 Jun 05 05:52:59 PM PDT 24 Jun 05 05:53:01 PM PDT 24 437705611 ps
T130 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.4148499011 Jun 05 05:52:42 PM PDT 24 Jun 05 05:52:44 PM PDT 24 901620936 ps
T59 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3588612874 Jun 05 05:52:43 PM PDT 24 Jun 05 05:54:25 PM PDT 24 26632784296 ps
T63 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1376054685 Jun 05 05:52:34 PM PDT 24 Jun 05 05:52:46 PM PDT 24 8508678789 ps
T64 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2306028783 Jun 05 05:52:36 PM PDT 24 Jun 05 05:52:44 PM PDT 24 8257758815 ps
T797 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.2445484400 Jun 05 05:52:54 PM PDT 24 Jun 05 05:52:55 PM PDT 24 334815662 ps
T798 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.202962242 Jun 05 05:53:08 PM PDT 24 Jun 05 05:53:10 PM PDT 24 484791314 ps
T67 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3741197679 Jun 05 05:52:48 PM PDT 24 Jun 05 05:52:52 PM PDT 24 4977981646 ps
T145 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2919972379 Jun 05 05:52:40 PM PDT 24 Jun 05 05:52:42 PM PDT 24 315144457 ps
T799 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.296784089 Jun 05 05:53:19 PM PDT 24 Jun 05 05:53:22 PM PDT 24 312915481 ps
T131 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.676518135 Jun 05 05:52:53 PM PDT 24 Jun 05 05:52:56 PM PDT 24 474290415 ps
T800 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1655099656 Jun 05 05:52:28 PM PDT 24 Jun 05 05:52:31 PM PDT 24 478553346 ps
T82 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3620092042 Jun 05 05:53:04 PM PDT 24 Jun 05 05:53:07 PM PDT 24 618038554 ps
T146 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.625479530 Jun 05 05:52:47 PM PDT 24 Jun 05 05:52:49 PM PDT 24 2518879814 ps
T98 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.4162867394 Jun 05 05:52:49 PM PDT 24 Jun 05 05:52:52 PM PDT 24 578261164 ps
T801 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.2156805092 Jun 05 05:53:10 PM PDT 24 Jun 05 05:53:12 PM PDT 24 512425692 ps
T147 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2275530449 Jun 05 05:52:28 PM PDT 24 Jun 05 05:52:30 PM PDT 24 484785809 ps
T81 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2793058566 Jun 05 05:52:51 PM PDT 24 Jun 05 05:53:12 PM PDT 24 7813935461 ps
T802 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.205309592 Jun 05 05:53:05 PM PDT 24 Jun 05 05:53:07 PM PDT 24 309556212 ps
T132 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1651442062 Jun 05 05:52:46 PM PDT 24 Jun 05 05:52:52 PM PDT 24 1089899025 ps
T148 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2280315726 Jun 05 05:53:03 PM PDT 24 Jun 05 05:53:06 PM PDT 24 2837078529 ps
T149 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2001383564 Jun 05 05:52:57 PM PDT 24 Jun 05 05:53:08 PM PDT 24 4300812879 ps
T72 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1916201406 Jun 05 05:52:56 PM PDT 24 Jun 05 05:52:59 PM PDT 24 716299956 ps
T803 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.4088584793 Jun 05 05:52:27 PM PDT 24 Jun 05 05:52:31 PM PDT 24 918749412 ps
T804 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1980934479 Jun 05 05:53:00 PM PDT 24 Jun 05 05:53:01 PM PDT 24 650679530 ps
T73 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1254806867 Jun 05 05:52:54 PM PDT 24 Jun 05 05:52:58 PM PDT 24 428021147 ps
T805 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1538634655 Jun 05 05:52:49 PM PDT 24 Jun 05 05:52:51 PM PDT 24 511804802 ps
T150 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2459810632 Jun 05 05:52:56 PM PDT 24 Jun 05 05:53:06 PM PDT 24 2359025858 ps
T806 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.475809137 Jun 05 05:52:54 PM PDT 24 Jun 05 05:52:55 PM PDT 24 416183117 ps
T807 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2237147394 Jun 05 05:52:57 PM PDT 24 Jun 05 05:53:00 PM PDT 24 1472851890 ps
T80 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3187908292 Jun 05 05:52:33 PM PDT 24 Jun 05 05:52:35 PM PDT 24 492580232 ps
T74 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1039475153 Jun 05 05:53:05 PM PDT 24 Jun 05 05:53:07 PM PDT 24 381238328 ps
T808 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.452301181 Jun 05 05:52:30 PM PDT 24 Jun 05 05:52:33 PM PDT 24 719166272 ps
T809 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3650840244 Jun 05 05:52:29 PM PDT 24 Jun 05 05:52:32 PM PDT 24 878112358 ps
T810 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1181807350 Jun 05 05:52:54 PM PDT 24 Jun 05 05:53:00 PM PDT 24 359036351 ps
T811 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3592785998 Jun 05 05:52:58 PM PDT 24 Jun 05 05:53:10 PM PDT 24 3984683570 ps
T348 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3665740884 Jun 05 05:52:53 PM PDT 24 Jun 05 05:53:06 PM PDT 24 4701416198 ps
T812 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.10294548 Jun 05 05:53:11 PM PDT 24 Jun 05 05:53:14 PM PDT 24 337464064 ps
T75 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1494661082 Jun 05 05:53:02 PM PDT 24 Jun 05 05:53:06 PM PDT 24 581285812 ps
T77 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3926961224 Jun 05 05:52:48 PM PDT 24 Jun 05 05:52:51 PM PDT 24 433601771 ps
T813 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2647753992 Jun 05 05:52:38 PM PDT 24 Jun 05 05:52:40 PM PDT 24 588969063 ps
T814 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1545129656 Jun 05 05:53:02 PM PDT 24 Jun 05 05:53:05 PM PDT 24 308894786 ps
T815 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.1678843825 Jun 05 05:53:10 PM PDT 24 Jun 05 05:53:12 PM PDT 24 394267997 ps
T133 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.1213505214 Jun 05 05:52:56 PM PDT 24 Jun 05 05:52:59 PM PDT 24 524390755 ps
T816 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2512463515 Jun 05 05:53:10 PM PDT 24 Jun 05 05:53:12 PM PDT 24 431512070 ps
T817 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2108554298 Jun 05 05:52:54 PM PDT 24 Jun 05 05:52:57 PM PDT 24 613118308 ps
T818 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3135378719 Jun 05 05:52:38 PM PDT 24 Jun 05 05:52:42 PM PDT 24 4449634013 ps
T819 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.974443993 Jun 05 05:52:59 PM PDT 24 Jun 05 05:53:04 PM PDT 24 4090315294 ps
T820 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2268901205 Jun 05 05:53:02 PM PDT 24 Jun 05 05:53:04 PM PDT 24 554968453 ps
T821 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2443302684 Jun 05 05:52:39 PM PDT 24 Jun 05 05:52:41 PM PDT 24 571417244 ps
T822 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.69757285 Jun 05 05:52:56 PM PDT 24 Jun 05 05:52:57 PM PDT 24 472742168 ps
T134 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2722233042 Jun 05 05:53:01 PM PDT 24 Jun 05 05:55:07 PM PDT 24 23860043936 ps
T823 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1128624394 Jun 05 05:52:25 PM PDT 24 Jun 05 05:52:29 PM PDT 24 688862074 ps
T135 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2420353463 Jun 05 05:52:28 PM PDT 24 Jun 05 05:52:30 PM PDT 24 366471592 ps
T824 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1178683526 Jun 05 05:52:48 PM PDT 24 Jun 05 05:52:53 PM PDT 24 4338396503 ps
T825 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.862459921 Jun 05 05:52:57 PM PDT 24 Jun 05 05:52:59 PM PDT 24 417145823 ps
T826 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.25385338 Jun 05 05:53:05 PM PDT 24 Jun 05 05:53:07 PM PDT 24 614940942 ps
T827 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1248431836 Jun 05 05:53:14 PM PDT 24 Jun 05 05:53:17 PM PDT 24 335703522 ps
T828 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3175010735 Jun 05 05:52:40 PM PDT 24 Jun 05 05:52:42 PM PDT 24 587939793 ps
T829 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.1591990987 Jun 05 05:53:16 PM PDT 24 Jun 05 05:53:21 PM PDT 24 497815286 ps
T136 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2594627087 Jun 05 05:52:25 PM PDT 24 Jun 05 05:52:28 PM PDT 24 477097147 ps
T830 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1340900634 Jun 05 05:52:48 PM PDT 24 Jun 05 05:52:49 PM PDT 24 347318141 ps
T831 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1755906579 Jun 05 05:52:50 PM PDT 24 Jun 05 05:52:54 PM PDT 24 2318317693 ps
T832 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3428660365 Jun 05 05:53:01 PM PDT 24 Jun 05 05:53:07 PM PDT 24 3966940004 ps
T833 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.4080325864 Jun 05 05:52:46 PM PDT 24 Jun 05 05:52:51 PM PDT 24 2144972686 ps
T834 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1018856858 Jun 05 05:52:24 PM PDT 24 Jun 05 05:52:27 PM PDT 24 511129139 ps
T835 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1638655317 Jun 05 05:53:10 PM PDT 24 Jun 05 05:53:30 PM PDT 24 4508458475 ps
T836 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.608500670 Jun 05 05:53:00 PM PDT 24 Jun 05 05:53:12 PM PDT 24 4456496973 ps
T837 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3219608760 Jun 05 05:52:26 PM PDT 24 Jun 05 05:52:29 PM PDT 24 799209078 ps
T83 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1962414279 Jun 05 05:52:49 PM PDT 24 Jun 05 05:53:01 PM PDT 24 8720091706 ps
T838 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3352459244 Jun 05 05:52:46 PM PDT 24 Jun 05 05:52:48 PM PDT 24 349448658 ps
T839 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2257881514 Jun 05 05:52:39 PM PDT 24 Jun 05 05:52:41 PM PDT 24 467884498 ps
T840 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.348508241 Jun 05 05:53:12 PM PDT 24 Jun 05 05:53:14 PM PDT 24 419471776 ps
T137 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2147331527 Jun 05 05:52:29 PM PDT 24 Jun 05 05:52:32 PM PDT 24 1252817686 ps
T841 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1520875076 Jun 05 05:52:54 PM PDT 24 Jun 05 05:52:55 PM PDT 24 458966342 ps
T842 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.3353335575 Jun 05 05:53:05 PM PDT 24 Jun 05 05:53:08 PM PDT 24 577811677 ps
T843 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3889395664 Jun 05 05:52:47 PM PDT 24 Jun 05 05:52:49 PM PDT 24 512695780 ps
T844 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.2958796270 Jun 05 05:52:50 PM PDT 24 Jun 05 05:53:02 PM PDT 24 4711947692 ps
T845 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.681619635 Jun 05 05:53:24 PM PDT 24 Jun 05 05:53:27 PM PDT 24 502835875 ps
T846 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2561231994 Jun 05 05:53:00 PM PDT 24 Jun 05 05:53:13 PM PDT 24 4413990652 ps
T847 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.3747811883 Jun 05 05:53:16 PM PDT 24 Jun 05 05:53:20 PM PDT 24 457392875 ps
T848 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1754459290 Jun 05 05:53:01 PM PDT 24 Jun 05 05:53:06 PM PDT 24 4990851942 ps
T138 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.570347880 Jun 05 05:52:37 PM PDT 24 Jun 05 05:54:09 PM PDT 24 19983191527 ps
T142 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1567261939 Jun 05 05:52:26 PM PDT 24 Jun 05 05:52:28 PM PDT 24 409583288 ps
T849 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.420675006 Jun 05 05:53:01 PM PDT 24 Jun 05 05:53:04 PM PDT 24 291705124 ps
T139 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1389515021 Jun 05 05:52:31 PM PDT 24 Jun 05 05:53:25 PM PDT 24 40155797275 ps
T850 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.1973103656 Jun 05 05:52:43 PM PDT 24 Jun 05 05:52:45 PM PDT 24 426700219 ps
T851 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2444818768 Jun 05 05:53:12 PM PDT 24 Jun 05 05:53:14 PM PDT 24 417649536 ps
T852 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2304108993 Jun 05 05:52:54 PM PDT 24 Jun 05 05:52:56 PM PDT 24 396598978 ps
T853 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.4048319782 Jun 05 05:52:32 PM PDT 24 Jun 05 05:52:35 PM PDT 24 460675246 ps
T854 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.752514578 Jun 05 05:53:03 PM PDT 24 Jun 05 05:53:05 PM PDT 24 413455345 ps
T855 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.1974858606 Jun 05 05:53:00 PM PDT 24 Jun 05 05:53:03 PM PDT 24 528023827 ps
T856 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2352977061 Jun 05 05:53:00 PM PDT 24 Jun 05 05:53:03 PM PDT 24 401227791 ps
T857 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.478245102 Jun 05 05:52:28 PM PDT 24 Jun 05 05:52:32 PM PDT 24 597767726 ps
T858 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.724943605 Jun 05 05:52:46 PM PDT 24 Jun 05 05:52:48 PM PDT 24 396367136 ps
T859 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.591078868 Jun 05 05:52:32 PM PDT 24 Jun 05 05:52:34 PM PDT 24 557002304 ps
T860 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2966832468 Jun 05 05:53:02 PM PDT 24 Jun 05 05:53:04 PM PDT 24 504784372 ps
T861 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.969910492 Jun 05 05:52:59 PM PDT 24 Jun 05 05:53:01 PM PDT 24 308376682 ps
T862 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1449238191 Jun 05 05:52:57 PM PDT 24 Jun 05 05:52:59 PM PDT 24 638537203 ps
T863 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1210551305 Jun 05 05:52:30 PM PDT 24 Jun 05 05:52:36 PM PDT 24 4551613791 ps
T864 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.1721866928 Jun 05 05:53:00 PM PDT 24 Jun 05 05:53:01 PM PDT 24 400971233 ps
T865 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.674611069 Jun 05 05:52:54 PM PDT 24 Jun 05 05:52:59 PM PDT 24 4198934384 ps
T866 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.1165524368 Jun 05 05:52:49 PM PDT 24 Jun 05 05:52:52 PM PDT 24 425890083 ps
T867 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1150668039 Jun 05 05:52:53 PM PDT 24 Jun 05 05:52:57 PM PDT 24 622655080 ps
T868 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3212899219 Jun 05 05:52:49 PM PDT 24 Jun 05 05:52:52 PM PDT 24 1907840352 ps
T869 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1326262083 Jun 05 05:53:10 PM PDT 24 Jun 05 05:53:13 PM PDT 24 497130558 ps
T870 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.434175577 Jun 05 05:52:29 PM PDT 24 Jun 05 05:52:35 PM PDT 24 645230211 ps
T871 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.1466968044 Jun 05 05:52:32 PM PDT 24 Jun 05 05:52:35 PM PDT 24 5144738986 ps
T872 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.3437568090 Jun 05 05:53:02 PM PDT 24 Jun 05 05:53:04 PM PDT 24 563265975 ps
T873 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3291822050 Jun 05 05:53:16 PM PDT 24 Jun 05 05:53:20 PM PDT 24 388146373 ps
T874 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.581533848 Jun 05 05:52:55 PM PDT 24 Jun 05 05:52:56 PM PDT 24 323172520 ps
T875 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.700586055 Jun 05 05:53:04 PM PDT 24 Jun 05 05:53:07 PM PDT 24 728109106 ps
T876 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.3140000658 Jun 05 05:52:47 PM PDT 24 Jun 05 05:52:54 PM PDT 24 2379113107 ps
T877 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.2124838028 Jun 05 05:52:21 PM PDT 24 Jun 05 05:52:24 PM PDT 24 563083668 ps
T878 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1191276903 Jun 05 05:52:49 PM PDT 24 Jun 05 05:53:13 PM PDT 24 8181781704 ps
T879 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1377392763 Jun 05 05:52:51 PM PDT 24 Jun 05 05:52:53 PM PDT 24 471736321 ps
T880 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3112119406 Jun 05 05:52:49 PM PDT 24 Jun 05 05:52:52 PM PDT 24 328522872 ps
T881 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2080193481 Jun 05 05:53:16 PM PDT 24 Jun 05 05:53:21 PM PDT 24 454367276 ps
T882 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.692564676 Jun 05 05:53:19 PM PDT 24 Jun 05 05:53:23 PM PDT 24 525463305 ps
T883 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.1464478834 Jun 05 05:53:12 PM PDT 24 Jun 05 05:53:14 PM PDT 24 417839167 ps
T884 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2763438619 Jun 05 05:52:54 PM PDT 24 Jun 05 05:52:56 PM PDT 24 531354118 ps
T885 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.1100797750 Jun 05 05:52:29 PM PDT 24 Jun 05 05:52:34 PM PDT 24 3869020244 ps
T886 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.3330551943 Jun 05 05:52:45 PM PDT 24 Jun 05 05:52:49 PM PDT 24 632553535 ps
T887 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.54541206 Jun 05 05:52:54 PM PDT 24 Jun 05 05:52:59 PM PDT 24 989915805 ps
T888 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.4121770729 Jun 05 05:53:02 PM PDT 24 Jun 05 05:53:05 PM PDT 24 554559109 ps
T889 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2329309529 Jun 05 05:52:54 PM PDT 24 Jun 05 05:52:58 PM PDT 24 8432333002 ps
T890 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.3237817630 Jun 05 05:53:11 PM PDT 24 Jun 05 05:53:14 PM PDT 24 419897703 ps
T140 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2887315672 Jun 05 05:52:28 PM PDT 24 Jun 05 05:52:31 PM PDT 24 362589409 ps
T891 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3055734764 Jun 05 05:52:25 PM PDT 24 Jun 05 05:52:28 PM PDT 24 377563281 ps
T892 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3885608225 Jun 05 05:52:23 PM PDT 24 Jun 05 05:52:25 PM PDT 24 551321693 ps
T141 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.74508114 Jun 05 05:52:34 PM PDT 24 Jun 05 05:52:36 PM PDT 24 385745720 ps
T893 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2335805081 Jun 05 05:52:32 PM PDT 24 Jun 05 05:52:35 PM PDT 24 442660358 ps
T894 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.429931007 Jun 05 05:52:57 PM PDT 24 Jun 05 05:52:59 PM PDT 24 1261924634 ps
T895 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2783207341 Jun 05 05:52:53 PM PDT 24 Jun 05 05:52:55 PM PDT 24 434312720 ps
T896 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.156100678 Jun 05 05:53:04 PM PDT 24 Jun 05 05:53:07 PM PDT 24 409683421 ps
T897 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.953731725 Jun 05 05:53:02 PM PDT 24 Jun 05 05:53:05 PM PDT 24 326947313 ps
T898 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.710253044 Jun 05 05:52:56 PM PDT 24 Jun 05 05:52:59 PM PDT 24 504687845 ps
T899 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2058932186 Jun 05 05:52:54 PM PDT 24 Jun 05 05:52:56 PM PDT 24 361045466 ps
T900 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.3889780320 Jun 05 05:52:24 PM PDT 24 Jun 05 05:52:35 PM PDT 24 2234089020 ps
T901 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.2555514130 Jun 05 05:52:44 PM PDT 24 Jun 05 05:52:48 PM PDT 24 333142703 ps
T902 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2761531652 Jun 05 05:52:25 PM PDT 24 Jun 05 05:52:28 PM PDT 24 529247289 ps
T903 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3507222103 Jun 05 05:52:57 PM PDT 24 Jun 05 05:53:02 PM PDT 24 8836514505 ps
T904 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.2728872278 Jun 05 05:52:50 PM PDT 24 Jun 05 05:52:52 PM PDT 24 585674163 ps
T905 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.2757271236 Jun 05 05:52:58 PM PDT 24 Jun 05 05:53:02 PM PDT 24 1562536255 ps
T143 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3054141258 Jun 05 05:52:51 PM PDT 24 Jun 05 05:52:53 PM PDT 24 440786734 ps
T906 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1365835148 Jun 05 05:52:44 PM PDT 24 Jun 05 05:52:48 PM PDT 24 2273345806 ps
T907 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.641424362 Jun 05 05:53:02 PM PDT 24 Jun 05 05:53:08 PM PDT 24 507825468 ps
T908 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.500421110 Jun 05 05:52:29 PM PDT 24 Jun 05 05:52:32 PM PDT 24 469240894 ps
T909 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.906194487 Jun 05 05:52:33 PM PDT 24 Jun 05 05:52:35 PM PDT 24 503774186 ps
T910 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1418269603 Jun 05 05:52:58 PM PDT 24 Jun 05 05:54:03 PM PDT 24 51267978254 ps
T911 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.515899908 Jun 05 05:53:01 PM PDT 24 Jun 05 05:53:04 PM PDT 24 476490274 ps
T912 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3563643191 Jun 05 05:52:42 PM PDT 24 Jun 05 05:52:56 PM PDT 24 8967975713 ps
T913 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.164931504 Jun 05 05:53:01 PM PDT 24 Jun 05 05:53:14 PM PDT 24 8004525620 ps
T914 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3274882560 Jun 05 05:52:58 PM PDT 24 Jun 05 05:53:00 PM PDT 24 528545168 ps
T915 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.420513568 Jun 05 05:52:50 PM PDT 24 Jun 05 05:52:57 PM PDT 24 2884331704 ps
T916 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1614332998 Jun 05 05:52:51 PM PDT 24 Jun 05 05:52:57 PM PDT 24 8960660081 ps
T917 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2799947775 Jun 05 05:52:56 PM PDT 24 Jun 05 05:52:57 PM PDT 24 302232663 ps
T918 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2519997781 Jun 05 05:53:01 PM PDT 24 Jun 05 05:53:04 PM PDT 24 461615703 ps

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.594597987
Short name T6
Test name
Test status
Simulation time 264283069425 ps
CPU time 418.77 seconds
Started Jun 05 05:25:29 PM PDT 24
Finished Jun 05 05:32:29 PM PDT 24
Peak memory 210380 kb
Host smart-17bf6210-bd7e-45ae-a988-6d072699da0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594597987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.594597987
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.3418910136
Short name T1
Test name
Test status
Simulation time 539584948212 ps
CPU time 1239.24 seconds
Started Jun 05 05:25:37 PM PDT 24
Finished Jun 05 05:46:17 PM PDT 24
Peak memory 201820 kb
Host smart-0f47ee91-2c2b-439d-86a3-6a5d7320a058
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418910136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.3418910136
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.1766841342
Short name T43
Test name
Test status
Simulation time 429337298470 ps
CPU time 606.48 seconds
Started Jun 05 05:25:51 PM PDT 24
Finished Jun 05 05:35:59 PM PDT 24
Peak memory 210712 kb
Host smart-7814b9d3-c8d6-4b3f-9c2f-b6629ea1bb6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766841342 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.1766841342
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.3351646406
Short name T156
Test name
Test status
Simulation time 509985102821 ps
CPU time 1167.71 seconds
Started Jun 05 05:30:11 PM PDT 24
Finished Jun 05 05:49:40 PM PDT 24
Peak memory 201808 kb
Host smart-5ee4fca4-9782-4067-94be-b02cf50a7458
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351646406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.3351646406
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.3878398281
Short name T16
Test name
Test status
Simulation time 95233025821 ps
CPU time 237.01 seconds
Started Jun 05 05:25:50 PM PDT 24
Finished Jun 05 05:29:48 PM PDT 24
Peak memory 211572 kb
Host smart-a47385a9-070c-4b42-bab3-910a2d0e8049
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878398281 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.3878398281
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.2874202885
Short name T164
Test name
Test status
Simulation time 521493526686 ps
CPU time 601.44 seconds
Started Jun 05 05:28:02 PM PDT 24
Finished Jun 05 05:38:04 PM PDT 24
Peak memory 201880 kb
Host smart-d7a12d60-d5ff-48e7-8420-9c79b71ac62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874202885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.2874202885
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.2711728322
Short name T186
Test name
Test status
Simulation time 611019071076 ps
CPU time 418.54 seconds
Started Jun 05 05:27:41 PM PDT 24
Finished Jun 05 05:34:40 PM PDT 24
Peak memory 201816 kb
Host smart-58123678-c2af-4e61-99f7-fbd15037ec5f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711728322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.2711728322
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.3018890584
Short name T158
Test name
Test status
Simulation time 488715967506 ps
CPU time 646.54 seconds
Started Jun 05 05:27:43 PM PDT 24
Finished Jun 05 05:38:30 PM PDT 24
Peak memory 201880 kb
Host smart-bfa16634-dd5e-474e-aaae-f50fdd24318c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018890584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.3018890584
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.1714116551
Short name T188
Test name
Test status
Simulation time 567849392495 ps
CPU time 700.32 seconds
Started Jun 05 05:29:50 PM PDT 24
Finished Jun 05 05:41:31 PM PDT 24
Peak memory 201860 kb
Host smart-1e3cf07d-1b6f-4eac-9643-03d6e7c8bc11
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714116551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.1714116551
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.3803732977
Short name T151
Test name
Test status
Simulation time 514140395219 ps
CPU time 586.86 seconds
Started Jun 05 05:31:14 PM PDT 24
Finished Jun 05 05:41:01 PM PDT 24
Peak memory 201812 kb
Host smart-ad6032fc-04df-4077-9c3e-a19729a21f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803732977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.3803732977
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1376054685
Short name T63
Test name
Test status
Simulation time 8508678789 ps
CPU time 11.72 seconds
Started Jun 05 05:52:34 PM PDT 24
Finished Jun 05 05:52:46 PM PDT 24
Peak memory 202116 kb
Host smart-35b6ff89-bc61-4855-8bbd-82569e873c39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376054685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.1376054685
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.1171261776
Short name T105
Test name
Test status
Simulation time 112169334486 ps
CPU time 563.07 seconds
Started Jun 05 05:26:18 PM PDT 24
Finished Jun 05 05:35:41 PM PDT 24
Peak memory 202116 kb
Host smart-b1423f81-172f-408c-b417-2393704590f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171261776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.1171261776
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.2838056680
Short name T48
Test name
Test status
Simulation time 351199309614 ps
CPU time 199.84 seconds
Started Jun 05 05:32:12 PM PDT 24
Finished Jun 05 05:35:33 PM PDT 24
Peak memory 201804 kb
Host smart-31555f38-fd2f-4600-a76f-4a0a5c194f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838056680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.2838056680
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.678684453
Short name T44
Test name
Test status
Simulation time 371284478509 ps
CPU time 194.6 seconds
Started Jun 05 05:29:13 PM PDT 24
Finished Jun 05 05:32:28 PM PDT 24
Peak memory 210164 kb
Host smart-9a7363f7-fe8c-491a-8013-3e0e13ec1966
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678684453 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.678684453
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.3025469091
Short name T238
Test name
Test status
Simulation time 495563838100 ps
CPU time 1173.96 seconds
Started Jun 05 05:32:18 PM PDT 24
Finished Jun 05 05:51:52 PM PDT 24
Peak memory 201808 kb
Host smart-d801aee4-9a9a-4bc5-a1ba-ab4553aab26b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025469091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.3025469091
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.2124496753
Short name T203
Test name
Test status
Simulation time 335339095 ps
CPU time 1.12 seconds
Started Jun 05 05:26:14 PM PDT 24
Finished Jun 05 05:26:15 PM PDT 24
Peak memory 201484 kb
Host smart-e6a24d02-6b60-472c-a78c-cc879b802b07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124496753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.2124496753
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.4136583864
Short name T88
Test name
Test status
Simulation time 539921889307 ps
CPU time 248.21 seconds
Started Jun 05 05:30:57 PM PDT 24
Finished Jun 05 05:35:06 PM PDT 24
Peak memory 201884 kb
Host smart-ef57a817-735e-4f22-8874-c4d93015202d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136583864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.4136583864
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.676518135
Short name T131
Test name
Test status
Simulation time 474290415 ps
CPU time 1.88 seconds
Started Jun 05 05:52:53 PM PDT 24
Finished Jun 05 05:52:56 PM PDT 24
Peak memory 201720 kb
Host smart-bd11b3f5-5648-4f4f-bbc0-8a5136097bbb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676518135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.676518135
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.2882742824
Short name T152
Test name
Test status
Simulation time 490170076245 ps
CPU time 295.28 seconds
Started Jun 05 05:26:04 PM PDT 24
Finished Jun 05 05:31:01 PM PDT 24
Peak memory 201796 kb
Host smart-a56d94bf-4b4f-49f6-b7e7-5cb1792d59f9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882742824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.2882742824
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.2958627107
Short name T287
Test name
Test status
Simulation time 329494233872 ps
CPU time 350.16 seconds
Started Jun 05 05:25:52 PM PDT 24
Finished Jun 05 05:31:43 PM PDT 24
Peak memory 201872 kb
Host smart-598e4bdb-6262-4d4d-a082-a002234f30ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958627107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
2958627107
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.885198849
Short name T184
Test name
Test status
Simulation time 521481814509 ps
CPU time 1131.87 seconds
Started Jun 05 05:25:59 PM PDT 24
Finished Jun 05 05:44:52 PM PDT 24
Peak memory 201940 kb
Host smart-1097b620-24ad-4e0a-ad2b-bd022cb050b7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885198849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gatin
g.885198849
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1254806867
Short name T73
Test name
Test status
Simulation time 428021147 ps
CPU time 2.84 seconds
Started Jun 05 05:52:54 PM PDT 24
Finished Jun 05 05:52:58 PM PDT 24
Peak memory 202008 kb
Host smart-2a8ef48c-c195-43be-8f66-9ad536e99170
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254806867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.1254806867
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.113788338
Short name T102
Test name
Test status
Simulation time 334588532211 ps
CPU time 183.93 seconds
Started Jun 05 05:26:21 PM PDT 24
Finished Jun 05 05:29:25 PM PDT 24
Peak memory 201780 kb
Host smart-9e4c06ca-57cb-4d79-9b5f-9e79ba9b0365
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113788338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gati
ng.113788338
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.1849966294
Short name T272
Test name
Test status
Simulation time 544193098624 ps
CPU time 210.12 seconds
Started Jun 05 05:25:37 PM PDT 24
Finished Jun 05 05:29:08 PM PDT 24
Peak memory 201860 kb
Host smart-c63b7d78-5617-479b-9362-4951b67ec847
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849966294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
1849966294
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.4267842945
Short name T194
Test name
Test status
Simulation time 690419038664 ps
CPU time 464.33 seconds
Started Jun 05 05:28:11 PM PDT 24
Finished Jun 05 05:35:56 PM PDT 24
Peak memory 202080 kb
Host smart-02f42f3c-1254-4c2e-b675-a291fd1bc53e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267842945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.4267842945
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.2002122277
Short name T47
Test name
Test status
Simulation time 55015605246 ps
CPU time 56.69 seconds
Started Jun 05 05:31:51 PM PDT 24
Finished Jun 05 05:32:48 PM PDT 24
Peak memory 210436 kb
Host smart-e8fe9932-7b38-4bfa-8cc6-1de2dc1b2a5f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002122277 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.2002122277
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.474423938
Short name T229
Test name
Test status
Simulation time 525457307022 ps
CPU time 585.36 seconds
Started Jun 05 05:31:30 PM PDT 24
Finished Jun 05 05:41:16 PM PDT 24
Peak memory 201792 kb
Host smart-64870267-de5b-4b7e-ab8f-fca151b809ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474423938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.474423938
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.2270357053
Short name T264
Test name
Test status
Simulation time 490176090006 ps
CPU time 82.87 seconds
Started Jun 05 05:31:32 PM PDT 24
Finished Jun 05 05:32:55 PM PDT 24
Peak memory 201800 kb
Host smart-9c7f3ddb-83c6-4d6b-abed-b5640fd1e3d8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270357053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.2270357053
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.2883721760
Short name T173
Test name
Test status
Simulation time 359619290970 ps
CPU time 235.82 seconds
Started Jun 05 05:25:45 PM PDT 24
Finished Jun 05 05:29:42 PM PDT 24
Peak memory 201884 kb
Host smart-756053ec-41da-4037-b99c-c0a7e96c4a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883721760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.2883721760
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.2525844945
Short name T85
Test name
Test status
Simulation time 3994871483 ps
CPU time 5.36 seconds
Started Jun 05 05:25:34 PM PDT 24
Finished Jun 05 05:25:40 PM PDT 24
Peak memory 217448 kb
Host smart-eb4ff66e-2685-4441-854b-8ed299f3ad56
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525844945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.2525844945
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.720913284
Short name T174
Test name
Test status
Simulation time 166117205083 ps
CPU time 89.56 seconds
Started Jun 05 05:28:20 PM PDT 24
Finished Jun 05 05:29:50 PM PDT 24
Peak memory 201812 kb
Host smart-5f881297-3d38-40b2-a016-4635cdddf99d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720913284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gati
ng.720913284
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.39171883
Short name T40
Test name
Test status
Simulation time 303916896155 ps
CPU time 185.44 seconds
Started Jun 05 05:28:23 PM PDT 24
Finished Jun 05 05:31:29 PM PDT 24
Peak memory 210088 kb
Host smart-2ecd95bd-26d1-4405-9c3a-878627efb93a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39171883 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.39171883
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.3659428289
Short name T244
Test name
Test status
Simulation time 794072210950 ps
CPU time 144.95 seconds
Started Jun 05 05:29:44 PM PDT 24
Finished Jun 05 05:32:10 PM PDT 24
Peak memory 218372 kb
Host smart-42a00959-e386-45ad-a8ea-26e18c66ad97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659428289 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.3659428289
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.10126736
Short name T277
Test name
Test status
Simulation time 581527551625 ps
CPU time 1373.61 seconds
Started Jun 05 05:32:05 PM PDT 24
Finished Jun 05 05:54:59 PM PDT 24
Peak memory 201828 kb
Host smart-5b270fcd-e162-41c1-aee8-220665a821b5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10126736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_w
akeup.10126736
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.1225500055
Short name T162
Test name
Test status
Simulation time 330700048373 ps
CPU time 189.1 seconds
Started Jun 05 05:28:37 PM PDT 24
Finished Jun 05 05:31:47 PM PDT 24
Peak memory 201808 kb
Host smart-0b2c306a-26d3-4eda-bd17-ce3a670707da
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225500055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.1225500055
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.2008326831
Short name T328
Test name
Test status
Simulation time 193791052530 ps
CPU time 126.09 seconds
Started Jun 05 05:28:17 PM PDT 24
Finished Jun 05 05:30:24 PM PDT 24
Peak memory 201808 kb
Host smart-b23230bc-5c1e-47c9-89be-ef555cb4bcfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008326831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.2008326831
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.1387193127
Short name T181
Test name
Test status
Simulation time 334055073253 ps
CPU time 232.29 seconds
Started Jun 05 05:26:08 PM PDT 24
Finished Jun 05 05:30:01 PM PDT 24
Peak memory 201788 kb
Host smart-9a0648d0-b26b-4b24-adb7-e787209f4fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387193127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.1387193127
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.575995634
Short name T284
Test name
Test status
Simulation time 595183219522 ps
CPU time 339.29 seconds
Started Jun 05 05:25:49 PM PDT 24
Finished Jun 05 05:31:28 PM PDT 24
Peak memory 201800 kb
Host smart-faa71e97-9bcf-48fe-9f5f-afcf721dfb97
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575995634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_w
akeup.575995634
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.584998707
Short name T218
Test name
Test status
Simulation time 373963673315 ps
CPU time 206.75 seconds
Started Jun 05 05:25:44 PM PDT 24
Finished Jun 05 05:29:12 PM PDT 24
Peak memory 201828 kb
Host smart-0aa3be50-7bc0-43b7-9831-f19ab35572c6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584998707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_w
akeup.584998707
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.2387457084
Short name T325
Test name
Test status
Simulation time 459673193766 ps
CPU time 571.61 seconds
Started Jun 05 05:32:26 PM PDT 24
Finished Jun 05 05:41:58 PM PDT 24
Peak memory 202196 kb
Host smart-7cd913f3-9986-43c4-9a5b-86f61e7d2b37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387457084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.2387457084
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.337647811
Short name T270
Test name
Test status
Simulation time 170640857756 ps
CPU time 413.21 seconds
Started Jun 05 05:27:12 PM PDT 24
Finished Jun 05 05:34:05 PM PDT 24
Peak memory 201864 kb
Host smart-6e76c85a-e7a0-4d7a-9843-ceac9beaf492
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337647811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_
wakeup.337647811
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.3504714395
Short name T282
Test name
Test status
Simulation time 679206032575 ps
CPU time 443.84 seconds
Started Jun 05 05:27:47 PM PDT 24
Finished Jun 05 05:35:11 PM PDT 24
Peak memory 201808 kb
Host smart-a08eb1d6-b7c8-437f-92e0-adfcf2985e97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504714395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.3504714395
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.3118746053
Short name T191
Test name
Test status
Simulation time 161057760695 ps
CPU time 108.46 seconds
Started Jun 05 05:25:44 PM PDT 24
Finished Jun 05 05:27:33 PM PDT 24
Peak memory 201844 kb
Host smart-cebeddd0-03d9-409b-8840-432b69036f7e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118746053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.3118746053
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.2240016778
Short name T327
Test name
Test status
Simulation time 390684062385 ps
CPU time 714.09 seconds
Started Jun 05 05:28:17 PM PDT 24
Finished Jun 05 05:40:12 PM PDT 24
Peak memory 201800 kb
Host smart-9c1faba3-27e8-41da-b9b2-857932a19c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240016778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.2240016778
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.1104179608
Short name T208
Test name
Test status
Simulation time 517059937133 ps
CPU time 82.94 seconds
Started Jun 05 05:28:45 PM PDT 24
Finished Jun 05 05:30:09 PM PDT 24
Peak memory 201872 kb
Host smart-382db723-aff2-42ef-b5c5-3ae8b8655084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104179608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.1104179608
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.3337838176
Short name T7
Test name
Test status
Simulation time 333888326551 ps
CPU time 210.91 seconds
Started Jun 05 05:30:28 PM PDT 24
Finished Jun 05 05:33:59 PM PDT 24
Peak memory 201880 kb
Host smart-da17d616-8826-40c6-897b-8fa6db31bb57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337838176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.3337838176
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.3845428754
Short name T20
Test name
Test status
Simulation time 310614536663 ps
CPU time 158.47 seconds
Started Jun 05 05:31:06 PM PDT 24
Finished Jun 05 05:33:45 PM PDT 24
Peak memory 217892 kb
Host smart-a0ba4c90-17a8-49ec-a4b5-7670c192f1e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845428754 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.3845428754
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.625479530
Short name T146
Test name
Test status
Simulation time 2518879814 ps
CPU time 1.61 seconds
Started Jun 05 05:52:47 PM PDT 24
Finished Jun 05 05:52:49 PM PDT 24
Peak memory 201748 kb
Host smart-3aa37cc1-a13e-483f-9042-8bf2d278d656
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625479530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ct
rl_same_csr_outstanding.625479530
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.1826960520
Short name T291
Test name
Test status
Simulation time 549279947812 ps
CPU time 1398.13 seconds
Started Jun 05 05:27:34 PM PDT 24
Finished Jun 05 05:50:53 PM PDT 24
Peak memory 201788 kb
Host smart-ad4d1614-26da-492c-bd62-f3b2c0a6f4ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826960520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.1826960520
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.3410555622
Short name T185
Test name
Test status
Simulation time 57232319173 ps
CPU time 91.16 seconds
Started Jun 05 05:32:12 PM PDT 24
Finished Jun 05 05:33:44 PM PDT 24
Peak memory 210436 kb
Host smart-9ba0747c-a90c-4877-9da6-323c5334b991
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410555622 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.3410555622
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.2993493521
Short name T257
Test name
Test status
Simulation time 156126679151 ps
CPU time 188.69 seconds
Started Jun 05 05:26:07 PM PDT 24
Finished Jun 05 05:29:17 PM PDT 24
Peak memory 201864 kb
Host smart-26128967-b20e-4e40-a66f-f34d4467edaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993493521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.2993493521
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.2322841068
Short name T248
Test name
Test status
Simulation time 504491810199 ps
CPU time 773.5 seconds
Started Jun 05 05:29:41 PM PDT 24
Finished Jun 05 05:42:35 PM PDT 24
Peak memory 201820 kb
Host smart-80b7c326-6f4b-4cfa-8dec-e1eae2404184
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322841068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.2322841068
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.2725516695
Short name T300
Test name
Test status
Simulation time 375646206201 ps
CPU time 234.85 seconds
Started Jun 05 05:30:15 PM PDT 24
Finished Jun 05 05:34:10 PM PDT 24
Peak memory 201800 kb
Host smart-e186c661-f4d7-403a-8944-b16e88e7d35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725516695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.2725516695
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3636058720
Short name T62
Test name
Test status
Simulation time 8529163183 ps
CPU time 21.14 seconds
Started Jun 05 05:52:51 PM PDT 24
Finished Jun 05 05:53:13 PM PDT 24
Peak memory 201808 kb
Host smart-bc27738b-d5fd-45b1-94b4-d75eddb7e0ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636058720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.3636058720
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.1514666410
Short name T345
Test name
Test status
Simulation time 537080346089 ps
CPU time 816.39 seconds
Started Jun 05 05:25:32 PM PDT 24
Finished Jun 05 05:39:10 PM PDT 24
Peak memory 201816 kb
Host smart-f45010a3-fb0d-47b6-903e-6cbe45559b58
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514666410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.1514666410
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.3296101147
Short name T255
Test name
Test status
Simulation time 524279249569 ps
CPU time 1275.77 seconds
Started Jun 05 05:26:42 PM PDT 24
Finished Jun 05 05:47:58 PM PDT 24
Peak memory 201860 kb
Host smart-aa469efe-7a67-4278-bd91-852ac4829ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296101147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.3296101147
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.3228861388
Short name T301
Test name
Test status
Simulation time 182984711737 ps
CPU time 437.33 seconds
Started Jun 05 05:27:56 PM PDT 24
Finished Jun 05 05:35:14 PM PDT 24
Peak memory 201800 kb
Host smart-e5a9adfc-c01c-41a9-83a8-9f127e6b936c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228861388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.3228861388
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.2798072552
Short name T337
Test name
Test status
Simulation time 372196187091 ps
CPU time 777.87 seconds
Started Jun 05 05:28:31 PM PDT 24
Finished Jun 05 05:41:30 PM PDT 24
Peak memory 201808 kb
Host smart-7274fd50-f585-4ef9-a4c0-2f0b99834443
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798072552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.2798072552
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.2227299689
Short name T51
Test name
Test status
Simulation time 90741961088 ps
CPU time 387.63 seconds
Started Jun 05 05:28:51 PM PDT 24
Finished Jun 05 05:35:19 PM PDT 24
Peak memory 202032 kb
Host smart-5cd9a10e-6db3-484c-ad0b-52dc08e66537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227299689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.2227299689
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.3041343104
Short name T271
Test name
Test status
Simulation time 493661682976 ps
CPU time 708.62 seconds
Started Jun 05 05:29:03 PM PDT 24
Finished Jun 05 05:40:52 PM PDT 24
Peak memory 201868 kb
Host smart-b89c4493-fde7-4aec-b9b9-d13da17682d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041343104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.3041343104
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.817322606
Short name T3
Test name
Test status
Simulation time 343440980560 ps
CPU time 857.45 seconds
Started Jun 05 05:31:19 PM PDT 24
Finished Jun 05 05:45:37 PM PDT 24
Peak memory 201876 kb
Host smart-94031276-960d-4c4e-96eb-a939096ef708
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817322606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_
wakeup.817322606
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.692852081
Short name T275
Test name
Test status
Simulation time 452433619288 ps
CPU time 1526.26 seconds
Started Jun 05 05:32:12 PM PDT 24
Finished Jun 05 05:57:39 PM PDT 24
Peak memory 210384 kb
Host smart-09b275c6-93c6-4bda-9635-05c6eb941597
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692852081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all.
692852081
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.1408847479
Short name T313
Test name
Test status
Simulation time 248621529020 ps
CPU time 55.44 seconds
Started Jun 05 05:25:37 PM PDT 24
Finished Jun 05 05:26:33 PM PDT 24
Peak memory 210100 kb
Host smart-c825f324-95c2-4425-af19-e231f86f1e45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408847479 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.1408847479
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.827457520
Short name T258
Test name
Test status
Simulation time 332230503781 ps
CPU time 378.23 seconds
Started Jun 05 05:32:10 PM PDT 24
Finished Jun 05 05:38:29 PM PDT 24
Peak memory 201796 kb
Host smart-d2ae154b-5459-4bd8-aa2b-723397cd813b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827457520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.827457520
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.349752454
Short name T289
Test name
Test status
Simulation time 486549591318 ps
CPU time 618.35 seconds
Started Jun 05 05:26:13 PM PDT 24
Finished Jun 05 05:36:32 PM PDT 24
Peak memory 201780 kb
Host smart-c1404abb-9bdb-4c66-9be8-e88e5ce7eba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349752454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.349752454
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.685078758
Short name T357
Test name
Test status
Simulation time 79254991791 ps
CPU time 275.69 seconds
Started Jun 05 05:26:51 PM PDT 24
Finished Jun 05 05:31:27 PM PDT 24
Peak memory 202092 kb
Host smart-ef72ef49-52ba-41a8-9d3e-dbfa3bb90922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685078758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.685078758
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.2026568997
Short name T33
Test name
Test status
Simulation time 160373081903 ps
CPU time 96.84 seconds
Started Jun 05 05:27:00 PM PDT 24
Finished Jun 05 05:28:37 PM PDT 24
Peak memory 201764 kb
Host smart-1732f7b8-ad4f-490a-bf15-5c85f0f8b315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026568997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.2026568997
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.2734510560
Short name T262
Test name
Test status
Simulation time 164338279057 ps
CPU time 102.73 seconds
Started Jun 05 05:27:34 PM PDT 24
Finished Jun 05 05:29:17 PM PDT 24
Peak memory 201804 kb
Host smart-c0db9f04-6df3-4184-a4c9-1383bdecf309
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734510560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.2734510560
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.3343265155
Short name T319
Test name
Test status
Simulation time 547721504640 ps
CPU time 101.15 seconds
Started Jun 05 05:29:09 PM PDT 24
Finished Jun 05 05:30:51 PM PDT 24
Peak memory 201796 kb
Host smart-c8289e2d-3f63-47a8-96bb-4820da83bc3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343265155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.3343265155
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.2482664740
Short name T311
Test name
Test status
Simulation time 683301320282 ps
CPU time 668.21 seconds
Started Jun 05 05:31:13 PM PDT 24
Finished Jun 05 05:42:22 PM PDT 24
Peak memory 201808 kb
Host smart-49dd70ce-ce87-4403-8d32-1df252f78159
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482664740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.2482664740
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.2725882021
Short name T252
Test name
Test status
Simulation time 246181578820 ps
CPU time 128.22 seconds
Started Jun 05 05:32:03 PM PDT 24
Finished Jun 05 05:34:11 PM PDT 24
Peak memory 201848 kb
Host smart-51a916f4-7ce7-409c-8316-da102089d4b0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725882021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.2725882021
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1916201406
Short name T72
Test name
Test status
Simulation time 716299956 ps
CPU time 1.98 seconds
Started Jun 05 05:52:56 PM PDT 24
Finished Jun 05 05:52:59 PM PDT 24
Peak memory 202016 kb
Host smart-6ed03e16-b793-4a25-84d8-05645181f882
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916201406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.1916201406
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.2766606645
Short name T299
Test name
Test status
Simulation time 332944829276 ps
CPU time 815.04 seconds
Started Jun 05 05:25:35 PM PDT 24
Finished Jun 05 05:39:11 PM PDT 24
Peak memory 201780 kb
Host smart-ad44f2bb-c69d-467a-8ed1-f69bb8f18451
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766606645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.2766606645
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.3753742428
Short name T228
Test name
Test status
Simulation time 161873067788 ps
CPU time 316.75 seconds
Started Jun 05 05:26:09 PM PDT 24
Finished Jun 05 05:31:27 PM PDT 24
Peak memory 201728 kb
Host smart-8abcd859-0d79-4100-bc49-262e359965ca
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753742428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.3753742428
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.3228917139
Short name T365
Test name
Test status
Simulation time 78842935459 ps
CPU time 315.41 seconds
Started Jun 05 05:26:06 PM PDT 24
Finished Jun 05 05:31:23 PM PDT 24
Peak memory 202172 kb
Host smart-f37cb6fe-64be-4e6f-8df1-ecd41c1b13a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228917139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.3228917139
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.4033804072
Short name T391
Test name
Test status
Simulation time 583826061402 ps
CPU time 1429.82 seconds
Started Jun 05 05:26:09 PM PDT 24
Finished Jun 05 05:50:00 PM PDT 24
Peak memory 201804 kb
Host smart-c0a845d2-a531-4c44-adb6-923e7b8ebe93
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033804072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.4033804072
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.88667000
Short name T675
Test name
Test status
Simulation time 108347474282 ps
CPU time 632.8 seconds
Started Jun 05 05:26:44 PM PDT 24
Finished Jun 05 05:37:17 PM PDT 24
Peak memory 202128 kb
Host smart-3ff875a1-dad3-4585-aadd-58bdf64fa2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88667000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.88667000
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.3212740821
Short name T292
Test name
Test status
Simulation time 145036364334 ps
CPU time 110.8 seconds
Started Jun 05 05:27:12 PM PDT 24
Finished Jun 05 05:29:03 PM PDT 24
Peak memory 217780 kb
Host smart-0b275505-a9e4-4e5d-8f96-b49b061d5271
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212740821 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.3212740821
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.2405093844
Short name T361
Test name
Test status
Simulation time 126644110977 ps
CPU time 189.55 seconds
Started Jun 05 05:27:27 PM PDT 24
Finished Jun 05 05:30:37 PM PDT 24
Peak memory 210472 kb
Host smart-9e41005d-b77a-44c2-ae01-6ee1845a6604
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405093844 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.2405093844
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.3478732412
Short name T349
Test name
Test status
Simulation time 134346504340 ps
CPU time 575.41 seconds
Started Jun 05 05:27:33 PM PDT 24
Finished Jun 05 05:37:09 PM PDT 24
Peak memory 202180 kb
Host smart-f8b3d607-66cf-4ac9-a7d6-3d3f786ca742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478732412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.3478732412
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.795915157
Short name T200
Test name
Test status
Simulation time 329553052348 ps
CPU time 184.25 seconds
Started Jun 05 05:28:04 PM PDT 24
Finished Jun 05 05:31:09 PM PDT 24
Peak memory 201824 kb
Host smart-6672fe35-51c5-4d47-afee-632039d4e736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795915157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.795915157
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.3967112561
Short name T295
Test name
Test status
Simulation time 493238330352 ps
CPU time 1063.73 seconds
Started Jun 05 05:25:45 PM PDT 24
Finished Jun 05 05:43:29 PM PDT 24
Peak memory 201800 kb
Host smart-11188d0c-527c-4283-9bcc-00e1ce70828e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967112561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.3967112561
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.841075420
Short name T279
Test name
Test status
Simulation time 334890630116 ps
CPU time 193.95 seconds
Started Jun 05 05:28:53 PM PDT 24
Finished Jun 05 05:32:07 PM PDT 24
Peak memory 201796 kb
Host smart-8fc3772d-2ab3-461b-b314-ddc4fc3ade92
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841075420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gati
ng.841075420
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.852741343
Short name T38
Test name
Test status
Simulation time 324978018145 ps
CPU time 538.4 seconds
Started Jun 05 05:29:29 PM PDT 24
Finished Jun 05 05:38:28 PM PDT 24
Peak memory 210292 kb
Host smart-0f5a66bf-e1c8-45fd-b70f-e0f78db31062
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852741343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all.
852741343
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.4040546115
Short name T356
Test name
Test status
Simulation time 125474247275 ps
CPU time 482.71 seconds
Started Jun 05 05:32:26 PM PDT 24
Finished Jun 05 05:40:29 PM PDT 24
Peak memory 202168 kb
Host smart-55f3e950-a894-4398-9999-2a484a9c402c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040546115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.4040546115
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.928630491
Short name T35
Test name
Test status
Simulation time 103104345494 ps
CPU time 93.65 seconds
Started Jun 05 05:32:34 PM PDT 24
Finished Jun 05 05:34:08 PM PDT 24
Peak memory 211208 kb
Host smart-51db1b62-7462-4f84-b40c-2ae04496146d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928630491 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.928630491
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.450786042
Short name T46
Test name
Test status
Simulation time 163761733411 ps
CPU time 115.11 seconds
Started Jun 05 05:32:48 PM PDT 24
Finished Jun 05 05:34:43 PM PDT 24
Peak memory 210408 kb
Host smart-d455fa1b-fc63-4cd2-8804-b7081d81f63a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450786042 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.450786042
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.372404538
Short name T210
Test name
Test status
Simulation time 330404105795 ps
CPU time 381.8 seconds
Started Jun 05 05:25:52 PM PDT 24
Finished Jun 05 05:32:15 PM PDT 24
Peak memory 201880 kb
Host smart-583caa86-2e97-407d-8402-92417e025d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372404538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.372404538
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2237147394
Short name T807
Test name
Test status
Simulation time 1472851890 ps
CPU time 2.98 seconds
Started Jun 05 05:52:57 PM PDT 24
Finished Jun 05 05:53:00 PM PDT 24
Peak memory 201908 kb
Host smart-70fa3b0b-01ba-4b51-a114-cd769dbb5ab5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237147394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.2237147394
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2722233042
Short name T134
Test name
Test status
Simulation time 23860043936 ps
CPU time 124.11 seconds
Started Jun 05 05:53:01 PM PDT 24
Finished Jun 05 05:55:07 PM PDT 24
Peak memory 201816 kb
Host smart-2bea4d13-d8ca-4204-9347-722f3f47e02e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722233042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.2722233042
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2147331527
Short name T137
Test name
Test status
Simulation time 1252817686 ps
CPU time 2.15 seconds
Started Jun 05 05:52:29 PM PDT 24
Finished Jun 05 05:52:32 PM PDT 24
Peak memory 201712 kb
Host smart-0fbfdd53-d5ae-40de-a86c-5ed4e8368805
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147331527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.2147331527
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2257881514
Short name T839
Test name
Test status
Simulation time 467884498 ps
CPU time 1.55 seconds
Started Jun 05 05:52:39 PM PDT 24
Finished Jun 05 05:52:41 PM PDT 24
Peak memory 201756 kb
Host smart-b05b33fe-1867-43a7-8362-09f55822a1fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257881514 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.2257881514
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1567261939
Short name T142
Test name
Test status
Simulation time 409583288 ps
CPU time 1.63 seconds
Started Jun 05 05:52:26 PM PDT 24
Finished Jun 05 05:52:28 PM PDT 24
Peak memory 201752 kb
Host smart-7a5a90c6-6c1f-4e54-8cc9-ef84c510bba1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567261939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.1567261939
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1655099656
Short name T800
Test name
Test status
Simulation time 478553346 ps
CPU time 1.73 seconds
Started Jun 05 05:52:28 PM PDT 24
Finished Jun 05 05:52:31 PM PDT 24
Peak memory 201732 kb
Host smart-19de3c0a-85e1-4735-aca3-71bfb45462c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655099656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.1655099656
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3219608760
Short name T837
Test name
Test status
Simulation time 799209078 ps
CPU time 2.13 seconds
Started Jun 05 05:52:26 PM PDT 24
Finished Jun 05 05:52:29 PM PDT 24
Peak memory 211188 kb
Host smart-b572f6b2-3c53-44df-aaa3-b56392802e7f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219608760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.3219608760
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3428660365
Short name T832
Test name
Test status
Simulation time 3966940004 ps
CPU time 4.02 seconds
Started Jun 05 05:53:01 PM PDT 24
Finished Jun 05 05:53:07 PM PDT 24
Peak memory 201668 kb
Host smart-8b364d2d-4500-45ef-8718-5c35d570adf5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428660365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.3428660365
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.2757271236
Short name T905
Test name
Test status
Simulation time 1562536255 ps
CPU time 3.02 seconds
Started Jun 05 05:52:58 PM PDT 24
Finished Jun 05 05:53:02 PM PDT 24
Peak memory 201916 kb
Host smart-ce5336a5-6bee-415a-a142-8caaa31bdb0b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757271236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.2757271236
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3588612874
Short name T59
Test name
Test status
Simulation time 26632784296 ps
CPU time 101.34 seconds
Started Jun 05 05:52:43 PM PDT 24
Finished Jun 05 05:54:25 PM PDT 24
Peak memory 201968 kb
Host smart-a3f87b95-0080-4b36-942e-534c84d12243
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588612874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.3588612874
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.4148499011
Short name T130
Test name
Test status
Simulation time 901620936 ps
CPU time 1.25 seconds
Started Jun 05 05:52:42 PM PDT 24
Finished Jun 05 05:52:44 PM PDT 24
Peak memory 201712 kb
Host smart-83950ad7-4188-4f22-bafb-74888554bec2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148499011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.4148499011
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.4048319782
Short name T853
Test name
Test status
Simulation time 460675246 ps
CPU time 1.75 seconds
Started Jun 05 05:52:32 PM PDT 24
Finished Jun 05 05:52:35 PM PDT 24
Peak memory 201752 kb
Host smart-46752d29-51a7-487f-8d04-a86acaf4b788
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048319782 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.4048319782
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2275530449
Short name T147
Test name
Test status
Simulation time 484785809 ps
CPU time 1 seconds
Started Jun 05 05:52:28 PM PDT 24
Finished Jun 05 05:52:30 PM PDT 24
Peak memory 201716 kb
Host smart-dbed3d0e-919c-4e9b-876f-6dbc43e2c799
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275530449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.2275530449
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.69757285
Short name T822
Test name
Test status
Simulation time 472742168 ps
CPU time 0.86 seconds
Started Jun 05 05:52:56 PM PDT 24
Finished Jun 05 05:52:57 PM PDT 24
Peak memory 201672 kb
Host smart-ed6e627d-238a-414b-8ee6-4ac4fba2595d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69757285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.69757285
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2965280774
Short name T58
Test name
Test status
Simulation time 2538077794 ps
CPU time 3.86 seconds
Started Jun 05 05:52:39 PM PDT 24
Finished Jun 05 05:52:44 PM PDT 24
Peak memory 201796 kb
Host smart-a48c07e4-0404-415e-8725-db1f563507c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965280774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.2965280774
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3926961224
Short name T77
Test name
Test status
Simulation time 433601771 ps
CPU time 2.49 seconds
Started Jun 05 05:52:48 PM PDT 24
Finished Jun 05 05:52:51 PM PDT 24
Peak memory 201852 kb
Host smart-2285fbf1-b3ec-438e-baef-0e50f6b69ea1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926961224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.3926961224
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1377392763
Short name T879
Test name
Test status
Simulation time 471736321 ps
CPU time 1.12 seconds
Started Jun 05 05:52:51 PM PDT 24
Finished Jun 05 05:52:53 PM PDT 24
Peak memory 201744 kb
Host smart-a8558ec8-6b97-4afd-a19d-b17a7a7077fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377392763 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.1377392763
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.641424362
Short name T907
Test name
Test status
Simulation time 507825468 ps
CPU time 1.35 seconds
Started Jun 05 05:53:02 PM PDT 24
Finished Jun 05 05:53:08 PM PDT 24
Peak memory 201696 kb
Host smart-38246be3-74de-4be3-9307-7e1f9c9f2fc9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641424362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.641424362
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.420675006
Short name T849
Test name
Test status
Simulation time 291705124 ps
CPU time 1.27 seconds
Started Jun 05 05:53:01 PM PDT 24
Finished Jun 05 05:53:04 PM PDT 24
Peak memory 201548 kb
Host smart-21061913-8a9e-4e38-ad7a-dd0c590656cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420675006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.420675006
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.4080325864
Short name T833
Test name
Test status
Simulation time 2144972686 ps
CPU time 5.15 seconds
Started Jun 05 05:52:46 PM PDT 24
Finished Jun 05 05:52:51 PM PDT 24
Peak memory 201704 kb
Host smart-1e859b28-48fc-4f40-bf27-efc516eb49e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080325864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.4080325864
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3741197679
Short name T67
Test name
Test status
Simulation time 4977981646 ps
CPU time 3.33 seconds
Started Jun 05 05:52:48 PM PDT 24
Finished Jun 05 05:52:52 PM PDT 24
Peak memory 202016 kb
Host smart-566e037c-23ee-4668-892c-23ba9ba035f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741197679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.3741197679
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.724943605
Short name T858
Test name
Test status
Simulation time 396367136 ps
CPU time 1.85 seconds
Started Jun 05 05:52:46 PM PDT 24
Finished Jun 05 05:52:48 PM PDT 24
Peak memory 201744 kb
Host smart-4cfe7a45-54b2-46cd-9ba7-3efd09c29d1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724943605 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.724943605
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3054141258
Short name T143
Test name
Test status
Simulation time 440786734 ps
CPU time 1.27 seconds
Started Jun 05 05:52:51 PM PDT 24
Finished Jun 05 05:52:53 PM PDT 24
Peak memory 201724 kb
Host smart-bcdd0bbb-425a-4149-a0de-23101be4eaf6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054141258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.3054141258
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2783207341
Short name T895
Test name
Test status
Simulation time 434312720 ps
CPU time 1.73 seconds
Started Jun 05 05:52:53 PM PDT 24
Finished Jun 05 05:52:55 PM PDT 24
Peak memory 201268 kb
Host smart-44311d78-5cc7-4294-abd4-bfe47c7e358b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783207341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.2783207341
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3212899219
Short name T868
Test name
Test status
Simulation time 1907840352 ps
CPU time 2.53 seconds
Started Jun 05 05:52:49 PM PDT 24
Finished Jun 05 05:52:52 PM PDT 24
Peak memory 201732 kb
Host smart-d0f0349d-1386-4497-8a31-bfbcc6a8314f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212899219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.3212899219
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3187908292
Short name T80
Test name
Test status
Simulation time 492580232 ps
CPU time 1.73 seconds
Started Jun 05 05:52:33 PM PDT 24
Finished Jun 05 05:52:35 PM PDT 24
Peak memory 201976 kb
Host smart-be72fd9d-0a6e-4bd5-9227-5a5c7097cc15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187908292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.3187908292
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.1165524368
Short name T866
Test name
Test status
Simulation time 425890083 ps
CPU time 1.98 seconds
Started Jun 05 05:52:49 PM PDT 24
Finished Jun 05 05:52:52 PM PDT 24
Peak memory 201776 kb
Host smart-93a57306-8ca8-4976-9676-4ee1751adce0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165524368 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.1165524368
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1340900634
Short name T830
Test name
Test status
Simulation time 347318141 ps
CPU time 0.96 seconds
Started Jun 05 05:52:48 PM PDT 24
Finished Jun 05 05:52:49 PM PDT 24
Peak memory 201744 kb
Host smart-c6cf33b4-53df-4e11-bc1f-5a6f0622a20e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340900634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.1340900634
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.2445484400
Short name T797
Test name
Test status
Simulation time 334815662 ps
CPU time 0.83 seconds
Started Jun 05 05:52:54 PM PDT 24
Finished Jun 05 05:52:55 PM PDT 24
Peak memory 201656 kb
Host smart-e5895d4c-8478-43d7-82c6-1ef84df4259a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445484400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.2445484400
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.420513568
Short name T915
Test name
Test status
Simulation time 2884331704 ps
CPU time 6.91 seconds
Started Jun 05 05:52:50 PM PDT 24
Finished Jun 05 05:52:57 PM PDT 24
Peak memory 201756 kb
Host smart-c34ac0ba-034a-4c7a-bfbc-c2f48cf349a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420513568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_c
trl_same_csr_outstanding.420513568
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.2555514130
Short name T901
Test name
Test status
Simulation time 333142703 ps
CPU time 3.17 seconds
Started Jun 05 05:52:44 PM PDT 24
Finished Jun 05 05:52:48 PM PDT 24
Peak memory 202020 kb
Host smart-97ff54db-8247-41ec-b567-b3819559ba89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555514130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.2555514130
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.674611069
Short name T865
Test name
Test status
Simulation time 4198934384 ps
CPU time 4.64 seconds
Started Jun 05 05:52:54 PM PDT 24
Finished Jun 05 05:52:59 PM PDT 24
Peak memory 201948 kb
Host smart-fd3dad8a-cfb3-4c02-916b-3f16feda1da0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674611069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_in
tg_err.674611069
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1520875076
Short name T841
Test name
Test status
Simulation time 458966342 ps
CPU time 1.21 seconds
Started Jun 05 05:52:54 PM PDT 24
Finished Jun 05 05:52:55 PM PDT 24
Peak memory 201772 kb
Host smart-ccf7190d-e1ec-4762-8835-0afeb27a91fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520875076 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.1520875076
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.490154292
Short name T144
Test name
Test status
Simulation time 437705611 ps
CPU time 0.98 seconds
Started Jun 05 05:52:59 PM PDT 24
Finished Jun 05 05:53:01 PM PDT 24
Peak memory 201744 kb
Host smart-1534f228-e402-4845-a690-04f110eac6bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490154292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.490154292
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.500421110
Short name T908
Test name
Test status
Simulation time 469240894 ps
CPU time 1.14 seconds
Started Jun 05 05:52:29 PM PDT 24
Finished Jun 05 05:52:32 PM PDT 24
Peak memory 201700 kb
Host smart-756d4f89-30f1-4b7b-a766-4c114907de98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500421110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.500421110
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1210551305
Short name T863
Test name
Test status
Simulation time 4551613791 ps
CPU time 4.94 seconds
Started Jun 05 05:52:30 PM PDT 24
Finished Jun 05 05:52:36 PM PDT 24
Peak memory 201936 kb
Host smart-b10fb07a-bb03-4a57-9385-6c044c80b40f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210551305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.1210551305
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2519997781
Short name T918
Test name
Test status
Simulation time 461615703 ps
CPU time 1.63 seconds
Started Jun 05 05:53:01 PM PDT 24
Finished Jun 05 05:53:04 PM PDT 24
Peak memory 201624 kb
Host smart-d881aa94-d0e3-4caa-9032-a66010380411
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519997781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.2519997781
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1178683526
Short name T824
Test name
Test status
Simulation time 4338396503 ps
CPU time 4.05 seconds
Started Jun 05 05:52:48 PM PDT 24
Finished Jun 05 05:52:53 PM PDT 24
Peak memory 201952 kb
Host smart-5149c427-805b-4135-ab24-2d7fcc446211
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178683526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.1178683526
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.710253044
Short name T898
Test name
Test status
Simulation time 504687845 ps
CPU time 1.9 seconds
Started Jun 05 05:52:56 PM PDT 24
Finished Jun 05 05:52:59 PM PDT 24
Peak memory 201740 kb
Host smart-39ba4ca8-4c7d-4b8d-a5db-bb1521b9d6a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710253044 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.710253044
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2420353463
Short name T135
Test name
Test status
Simulation time 366471592 ps
CPU time 1.13 seconds
Started Jun 05 05:52:28 PM PDT 24
Finished Jun 05 05:52:30 PM PDT 24
Peak memory 201756 kb
Host smart-4f749c7a-cabd-4723-a1eb-0681e831b372
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420353463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.2420353463
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.475809137
Short name T806
Test name
Test status
Simulation time 416183117 ps
CPU time 0.92 seconds
Started Jun 05 05:52:54 PM PDT 24
Finished Jun 05 05:52:55 PM PDT 24
Peak memory 201672 kb
Host smart-eb180026-f580-44c4-86d5-6f74dbc28785
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475809137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.475809137
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2459810632
Short name T150
Test name
Test status
Simulation time 2359025858 ps
CPU time 8.8 seconds
Started Jun 05 05:52:56 PM PDT 24
Finished Jun 05 05:53:06 PM PDT 24
Peak memory 201968 kb
Host smart-5eac84a9-e66d-4783-a9df-14be65119c5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459810632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.2459810632
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1494661082
Short name T75
Test name
Test status
Simulation time 581285812 ps
CPU time 2.33 seconds
Started Jun 05 05:53:02 PM PDT 24
Finished Jun 05 05:53:06 PM PDT 24
Peak memory 201960 kb
Host smart-4c7852c5-eea6-485b-8458-fe690f7707ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494661082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.1494661082
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2793058566
Short name T81
Test name
Test status
Simulation time 7813935461 ps
CPU time 20.51 seconds
Started Jun 05 05:52:51 PM PDT 24
Finished Jun 05 05:53:12 PM PDT 24
Peak memory 201956 kb
Host smart-ba66f024-d6c2-4c58-829a-8df37c63a857
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793058566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.2793058566
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2108554298
Short name T817
Test name
Test status
Simulation time 613118308 ps
CPU time 2.46 seconds
Started Jun 05 05:52:54 PM PDT 24
Finished Jun 05 05:52:57 PM PDT 24
Peak memory 201772 kb
Host smart-cc318307-a3e0-4c61-889d-0516aaa9a005
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108554298 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.2108554298
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3274882560
Short name T914
Test name
Test status
Simulation time 528545168 ps
CPU time 1.79 seconds
Started Jun 05 05:52:58 PM PDT 24
Finished Jun 05 05:53:00 PM PDT 24
Peak memory 201704 kb
Host smart-77513c15-e7ce-49b1-a7f8-2fb42c6b3426
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274882560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.3274882560
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3291822050
Short name T873
Test name
Test status
Simulation time 388146373 ps
CPU time 1.13 seconds
Started Jun 05 05:53:16 PM PDT 24
Finished Jun 05 05:53:20 PM PDT 24
Peak memory 201716 kb
Host smart-4a9341df-e628-40e3-8a5e-831825f310c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291822050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.3291822050
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1755906579
Short name T831
Test name
Test status
Simulation time 2318317693 ps
CPU time 2.76 seconds
Started Jun 05 05:52:50 PM PDT 24
Finished Jun 05 05:52:54 PM PDT 24
Peak memory 201804 kb
Host smart-e04200e0-9579-46e3-999e-f2ea2c78773f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755906579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.1755906579
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.700586055
Short name T875
Test name
Test status
Simulation time 728109106 ps
CPU time 1.98 seconds
Started Jun 05 05:53:04 PM PDT 24
Finished Jun 05 05:53:07 PM PDT 24
Peak memory 201952 kb
Host smart-fa682b39-c732-4961-8b9d-d2f7b93564fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700586055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.700586055
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2329309529
Short name T889
Test name
Test status
Simulation time 8432333002 ps
CPU time 4.18 seconds
Started Jun 05 05:52:54 PM PDT 24
Finished Jun 05 05:52:58 PM PDT 24
Peak memory 201980 kb
Host smart-0fd4079b-709d-4445-8bb0-2306fcdee415
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329309529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.2329309529
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.3353335575
Short name T842
Test name
Test status
Simulation time 577811677 ps
CPU time 1.41 seconds
Started Jun 05 05:53:05 PM PDT 24
Finished Jun 05 05:53:08 PM PDT 24
Peak memory 201680 kb
Host smart-5011a1b3-04f6-43fb-af5d-91cf09c7fd02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353335575 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.3353335575
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3276775889
Short name T60
Test name
Test status
Simulation time 443142435 ps
CPU time 1.86 seconds
Started Jun 05 05:52:45 PM PDT 24
Finished Jun 05 05:52:48 PM PDT 24
Peak memory 201740 kb
Host smart-b0de4c15-e4cd-4b27-9a6c-699701e7681e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276775889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.3276775889
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.862459921
Short name T825
Test name
Test status
Simulation time 417145823 ps
CPU time 1.59 seconds
Started Jun 05 05:52:57 PM PDT 24
Finished Jun 05 05:52:59 PM PDT 24
Peak memory 201676 kb
Host smart-22d026a4-8f62-4052-9c95-f7152fa5565c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862459921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.862459921
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.3140000658
Short name T876
Test name
Test status
Simulation time 2379113107 ps
CPU time 6.35 seconds
Started Jun 05 05:52:47 PM PDT 24
Finished Jun 05 05:52:54 PM PDT 24
Peak memory 201784 kb
Host smart-1b41aff0-0e1f-4398-a396-5ed85ccf41cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140000658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.3140000658
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.4121770729
Short name T888
Test name
Test status
Simulation time 554559109 ps
CPU time 2.12 seconds
Started Jun 05 05:53:02 PM PDT 24
Finished Jun 05 05:53:05 PM PDT 24
Peak memory 201992 kb
Host smart-15e417e8-b509-49bb-9f4c-72b9406419ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121770729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.4121770729
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.608500670
Short name T836
Test name
Test status
Simulation time 4456496973 ps
CPU time 11.1 seconds
Started Jun 05 05:53:00 PM PDT 24
Finished Jun 05 05:53:12 PM PDT 24
Peak memory 202032 kb
Host smart-cbaa3d58-d71c-4b80-9fbe-d449c1183cdc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608500670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_in
tg_err.608500670
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3175010735
Short name T828
Test name
Test status
Simulation time 587939793 ps
CPU time 0.96 seconds
Started Jun 05 05:52:40 PM PDT 24
Finished Jun 05 05:52:42 PM PDT 24
Peak memory 201752 kb
Host smart-42a940b5-2999-420b-9d5b-f2b17c5619ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175010735 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.3175010735
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.1678843825
Short name T815
Test name
Test status
Simulation time 394267997 ps
CPU time 1.57 seconds
Started Jun 05 05:53:10 PM PDT 24
Finished Jun 05 05:53:12 PM PDT 24
Peak memory 201656 kb
Host smart-05e26570-5a55-4d92-810b-66fb20f88d0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678843825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.1678843825
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3592785998
Short name T811
Test name
Test status
Simulation time 3984683570 ps
CPU time 10.92 seconds
Started Jun 05 05:52:58 PM PDT 24
Finished Jun 05 05:53:10 PM PDT 24
Peak memory 202040 kb
Host smart-7e4b86bb-3b9f-4fef-90e7-0de2ae8f3dc0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592785998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.3592785998
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2980176417
Short name T71
Test name
Test status
Simulation time 437267087 ps
CPU time 1.55 seconds
Started Jun 05 05:53:04 PM PDT 24
Finished Jun 05 05:53:07 PM PDT 24
Peak memory 201976 kb
Host smart-a294ba70-0ba0-45c4-a670-98ddd9e2e1e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980176417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.2980176417
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3665740884
Short name T348
Test name
Test status
Simulation time 4701416198 ps
CPU time 12.07 seconds
Started Jun 05 05:52:53 PM PDT 24
Finished Jun 05 05:53:06 PM PDT 24
Peak memory 202148 kb
Host smart-a906eb7d-02c4-482c-8184-c3547c6f8d71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665740884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.3665740884
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3620092042
Short name T82
Test name
Test status
Simulation time 618038554 ps
CPU time 1.19 seconds
Started Jun 05 05:53:04 PM PDT 24
Finished Jun 05 05:53:07 PM PDT 24
Peak memory 201752 kb
Host smart-9686f866-356a-4c86-9d50-9ca7153585b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620092042 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.3620092042
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2058932186
Short name T899
Test name
Test status
Simulation time 361045466 ps
CPU time 1.15 seconds
Started Jun 05 05:52:54 PM PDT 24
Finished Jun 05 05:52:56 PM PDT 24
Peak memory 201708 kb
Host smart-de4c6fde-eac8-4042-b48f-861ee0f43b1e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058932186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.2058932186
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.1973103656
Short name T850
Test name
Test status
Simulation time 426700219 ps
CPU time 1.52 seconds
Started Jun 05 05:52:43 PM PDT 24
Finished Jun 05 05:52:45 PM PDT 24
Peak memory 201700 kb
Host smart-500e79cc-f7fa-4d3d-b67e-4834ab3f0335
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973103656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.1973103656
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1365835148
Short name T906
Test name
Test status
Simulation time 2273345806 ps
CPU time 3.31 seconds
Started Jun 05 05:52:44 PM PDT 24
Finished Jun 05 05:52:48 PM PDT 24
Peak memory 201780 kb
Host smart-00a5ade5-e4e4-4593-9a38-f7c4609434e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365835148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.1365835148
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1039475153
Short name T74
Test name
Test status
Simulation time 381238328 ps
CPU time 1.8 seconds
Started Jun 05 05:53:05 PM PDT 24
Finished Jun 05 05:53:07 PM PDT 24
Peak memory 211192 kb
Host smart-60f5dedf-426b-47c7-a28f-451508af2909
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039475153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.1039475153
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.974443993
Short name T819
Test name
Test status
Simulation time 4090315294 ps
CPU time 4.18 seconds
Started Jun 05 05:52:59 PM PDT 24
Finished Jun 05 05:53:04 PM PDT 24
Peak memory 201996 kb
Host smart-22345a02-7481-45aa-be07-6c572e61c3c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974443993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_in
tg_err.974443993
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2763438619
Short name T884
Test name
Test status
Simulation time 531354118 ps
CPU time 1.15 seconds
Started Jun 05 05:52:54 PM PDT 24
Finished Jun 05 05:52:56 PM PDT 24
Peak memory 201752 kb
Host smart-bfe59329-41a0-41cf-859d-05d04042abb2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763438619 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.2763438619
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.953731725
Short name T897
Test name
Test status
Simulation time 326947313 ps
CPU time 1.61 seconds
Started Jun 05 05:53:02 PM PDT 24
Finished Jun 05 05:53:05 PM PDT 24
Peak memory 201604 kb
Host smart-c88ccfae-666b-46fa-8742-3ef76f019e99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953731725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.953731725
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1326262083
Short name T869
Test name
Test status
Simulation time 497130558 ps
CPU time 1.73 seconds
Started Jun 05 05:53:10 PM PDT 24
Finished Jun 05 05:53:13 PM PDT 24
Peak memory 201700 kb
Host smart-38aaa000-f93e-4417-824a-f24dbb7cbae5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326262083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.1326262083
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1638655317
Short name T835
Test name
Test status
Simulation time 4508458475 ps
CPU time 19.01 seconds
Started Jun 05 05:53:10 PM PDT 24
Finished Jun 05 05:53:30 PM PDT 24
Peak memory 201844 kb
Host smart-02dbbebd-2fc4-409b-96f9-8089f18727d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638655317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.1638655317
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2352977061
Short name T856
Test name
Test status
Simulation time 401227791 ps
CPU time 2.26 seconds
Started Jun 05 05:53:00 PM PDT 24
Finished Jun 05 05:53:03 PM PDT 24
Peak memory 210192 kb
Host smart-0cf3b724-2ab3-4510-ae39-e1443f8a67cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352977061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.2352977061
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1191276903
Short name T878
Test name
Test status
Simulation time 8181781704 ps
CPU time 23.32 seconds
Started Jun 05 05:52:49 PM PDT 24
Finished Jun 05 05:53:13 PM PDT 24
Peak memory 202016 kb
Host smart-d9ab106b-b757-4508-9360-7d64a5fbeeaf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191276903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.1191276903
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.54541206
Short name T887
Test name
Test status
Simulation time 989915805 ps
CPU time 4.45 seconds
Started Jun 05 05:52:54 PM PDT 24
Finished Jun 05 05:52:59 PM PDT 24
Peak memory 201880 kb
Host smart-af323280-ac76-44c6-9d61-049d09b64bec
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54541206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_aliasi
ng.54541206
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.570347880
Short name T138
Test name
Test status
Simulation time 19983191527 ps
CPU time 90.94 seconds
Started Jun 05 05:52:37 PM PDT 24
Finished Jun 05 05:54:09 PM PDT 24
Peak memory 201992 kb
Host smart-ed3d5e37-ab8b-45e5-9baa-173b74d3ca1a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570347880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_b
ash.570347880
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.452301181
Short name T808
Test name
Test status
Simulation time 719166272 ps
CPU time 1.79 seconds
Started Jun 05 05:52:30 PM PDT 24
Finished Jun 05 05:52:33 PM PDT 24
Peak memory 201716 kb
Host smart-5f0a2b88-b428-4034-907c-a214bf8260d5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452301181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_re
set.452301181
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2761531652
Short name T902
Test name
Test status
Simulation time 529247289 ps
CPU time 2.05 seconds
Started Jun 05 05:52:25 PM PDT 24
Finished Jun 05 05:52:28 PM PDT 24
Peak memory 201748 kb
Host smart-e0e90c46-7102-4ef6-8bcf-939e83191cc6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761531652 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.2761531652
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2594627087
Short name T136
Test name
Test status
Simulation time 477097147 ps
CPU time 1.94 seconds
Started Jun 05 05:52:25 PM PDT 24
Finished Jun 05 05:52:28 PM PDT 24
Peak memory 201720 kb
Host smart-28a2cf1b-39a4-4768-9f4f-68ef979e693b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594627087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.2594627087
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2443302684
Short name T821
Test name
Test status
Simulation time 571417244 ps
CPU time 0.86 seconds
Started Jun 05 05:52:39 PM PDT 24
Finished Jun 05 05:52:41 PM PDT 24
Peak memory 201684 kb
Host smart-c6353047-1b8b-4db4-954e-bb6d30474f72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443302684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.2443302684
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2280315726
Short name T148
Test name
Test status
Simulation time 2837078529 ps
CPU time 2.44 seconds
Started Jun 05 05:53:03 PM PDT 24
Finished Jun 05 05:53:06 PM PDT 24
Peak memory 201984 kb
Host smart-be620a14-7c0a-467b-9499-0e36dfc01cbb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280315726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.2280315726
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1128624394
Short name T823
Test name
Test status
Simulation time 688862074 ps
CPU time 2.42 seconds
Started Jun 05 05:52:25 PM PDT 24
Finished Jun 05 05:52:29 PM PDT 24
Peak memory 201992 kb
Host smart-49df2960-a575-4a7a-bffa-09410a73d72e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128624394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.1128624394
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3563643191
Short name T912
Test name
Test status
Simulation time 8967975713 ps
CPU time 13.38 seconds
Started Jun 05 05:52:42 PM PDT 24
Finished Jun 05 05:52:56 PM PDT 24
Peak memory 201968 kb
Host smart-039b29f2-0c0d-4895-a9d3-50208d15145e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563643191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.3563643191
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.515899908
Short name T911
Test name
Test status
Simulation time 476490274 ps
CPU time 1.15 seconds
Started Jun 05 05:53:01 PM PDT 24
Finished Jun 05 05:53:04 PM PDT 24
Peak memory 201688 kb
Host smart-1bc1301f-4eef-4dbb-806e-e494283c559e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515899908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.515899908
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.3437568090
Short name T872
Test name
Test status
Simulation time 563265975 ps
CPU time 0.76 seconds
Started Jun 05 05:53:02 PM PDT 24
Finished Jun 05 05:53:04 PM PDT 24
Peak memory 201712 kb
Host smart-788e9e5b-d06e-4f7f-a6f8-46bb01cb855d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437568090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.3437568090
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.2156805092
Short name T801
Test name
Test status
Simulation time 512425692 ps
CPU time 0.78 seconds
Started Jun 05 05:53:10 PM PDT 24
Finished Jun 05 05:53:12 PM PDT 24
Peak memory 201712 kb
Host smart-123c45d7-3bcf-40f0-ae05-cd974068f347
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156805092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.2156805092
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.10294548
Short name T812
Test name
Test status
Simulation time 337464064 ps
CPU time 1.34 seconds
Started Jun 05 05:53:11 PM PDT 24
Finished Jun 05 05:53:14 PM PDT 24
Peak memory 201676 kb
Host smart-1484121c-fb96-42c0-b417-74a9119cb2b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10294548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.10294548
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.4170620100
Short name T796
Test name
Test status
Simulation time 598641233 ps
CPU time 0.73 seconds
Started Jun 05 05:53:07 PM PDT 24
Finished Jun 05 05:53:09 PM PDT 24
Peak memory 201700 kb
Host smart-b2e69754-ed68-49ee-914e-1f178173beb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170620100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.4170620100
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2512463515
Short name T816
Test name
Test status
Simulation time 431512070 ps
CPU time 0.9 seconds
Started Jun 05 05:53:10 PM PDT 24
Finished Jun 05 05:53:12 PM PDT 24
Peak memory 201692 kb
Host smart-5f8b8d24-2c72-44f8-bda0-5526c745dfd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512463515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.2512463515
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2799947775
Short name T917
Test name
Test status
Simulation time 302232663 ps
CPU time 0.83 seconds
Started Jun 05 05:52:56 PM PDT 24
Finished Jun 05 05:52:57 PM PDT 24
Peak memory 201700 kb
Host smart-3cf0290e-a444-4c43-82d1-5650dc791044
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799947775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.2799947775
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.1721866928
Short name T864
Test name
Test status
Simulation time 400971233 ps
CPU time 0.78 seconds
Started Jun 05 05:53:00 PM PDT 24
Finished Jun 05 05:53:01 PM PDT 24
Peak memory 201708 kb
Host smart-5e155012-49bd-4a7f-9119-52f19c798424
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721866928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.1721866928
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2304108993
Short name T852
Test name
Test status
Simulation time 396598978 ps
CPU time 0.73 seconds
Started Jun 05 05:52:54 PM PDT 24
Finished Jun 05 05:52:56 PM PDT 24
Peak memory 201712 kb
Host smart-e25651cd-d273-4fc9-8c05-9deb1109e8ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304108993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.2304108993
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.581533848
Short name T874
Test name
Test status
Simulation time 323172520 ps
CPU time 1.03 seconds
Started Jun 05 05:52:55 PM PDT 24
Finished Jun 05 05:52:56 PM PDT 24
Peak memory 201692 kb
Host smart-ad2ccb3e-4f7d-42a6-8df3-56c0e29cfd0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581533848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.581533848
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3650840244
Short name T809
Test name
Test status
Simulation time 878112358 ps
CPU time 2.02 seconds
Started Jun 05 05:52:29 PM PDT 24
Finished Jun 05 05:52:32 PM PDT 24
Peak memory 201920 kb
Host smart-d6545f60-ec49-4cb2-9558-187d033368cc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650840244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.3650840244
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1418269603
Short name T910
Test name
Test status
Simulation time 51267978254 ps
CPU time 64.77 seconds
Started Jun 05 05:52:58 PM PDT 24
Finished Jun 05 05:54:03 PM PDT 24
Peak memory 201984 kb
Host smart-465a20f4-e4af-4704-9b22-b8808a3b8f01
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418269603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.1418269603
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.429931007
Short name T894
Test name
Test status
Simulation time 1261924634 ps
CPU time 1.53 seconds
Started Jun 05 05:52:57 PM PDT 24
Finished Jun 05 05:52:59 PM PDT 24
Peak memory 201716 kb
Host smart-86d83602-7441-4214-b634-2424b2f9a361
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429931007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_re
set.429931007
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3055734764
Short name T891
Test name
Test status
Simulation time 377563281 ps
CPU time 1.54 seconds
Started Jun 05 05:52:25 PM PDT 24
Finished Jun 05 05:52:28 PM PDT 24
Peak memory 201732 kb
Host smart-520f0303-2256-4c8e-8149-1337db11df42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055734764 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.3055734764
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.156100678
Short name T896
Test name
Test status
Simulation time 409683421 ps
CPU time 1.65 seconds
Started Jun 05 05:53:04 PM PDT 24
Finished Jun 05 05:53:07 PM PDT 24
Peak memory 201720 kb
Host smart-730f88b6-b4be-4101-b33d-e387d7fd3a5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156100678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.156100678
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.1974858606
Short name T855
Test name
Test status
Simulation time 528023827 ps
CPU time 1.78 seconds
Started Jun 05 05:53:00 PM PDT 24
Finished Jun 05 05:53:03 PM PDT 24
Peak memory 201704 kb
Host smart-bb16d4f0-3fbb-4971-b311-1537cafffe26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974858606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.1974858606
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3135378719
Short name T818
Test name
Test status
Simulation time 4449634013 ps
CPU time 3.66 seconds
Started Jun 05 05:52:38 PM PDT 24
Finished Jun 05 05:52:42 PM PDT 24
Peak memory 201956 kb
Host smart-99efb6d9-2887-4612-ac4f-5a501099266c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135378719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.3135378719
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.434175577
Short name T870
Test name
Test status
Simulation time 645230211 ps
CPU time 3.99 seconds
Started Jun 05 05:52:29 PM PDT 24
Finished Jun 05 05:52:35 PM PDT 24
Peak memory 217996 kb
Host smart-719f62e7-d9a9-44af-a252-0a08fcaf857e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434175577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.434175577
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3507222103
Short name T903
Test name
Test status
Simulation time 8836514505 ps
CPU time 4.85 seconds
Started Jun 05 05:52:57 PM PDT 24
Finished Jun 05 05:53:02 PM PDT 24
Peak memory 201936 kb
Host smart-b0347418-1ec5-43a9-9dfd-209b93062225
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507222103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.3507222103
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1980934479
Short name T804
Test name
Test status
Simulation time 650679530 ps
CPU time 0.72 seconds
Started Jun 05 05:53:00 PM PDT 24
Finished Jun 05 05:53:01 PM PDT 24
Peak memory 201700 kb
Host smart-9b40ecc6-841a-41c2-bd5e-f9fc91adb8e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980934479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.1980934479
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.969910492
Short name T861
Test name
Test status
Simulation time 308376682 ps
CPU time 0.82 seconds
Started Jun 05 05:52:59 PM PDT 24
Finished Jun 05 05:53:01 PM PDT 24
Peak memory 201884 kb
Host smart-7b4a3c3e-1177-46d7-aeb8-a14d592c9b6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969910492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.969910492
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1545129656
Short name T814
Test name
Test status
Simulation time 308894786 ps
CPU time 1.42 seconds
Started Jun 05 05:53:02 PM PDT 24
Finished Jun 05 05:53:05 PM PDT 24
Peak memory 201696 kb
Host smart-92aff955-4672-4e46-bc50-5e063346bff2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545129656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.1545129656
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.205309592
Short name T802
Test name
Test status
Simulation time 309556212 ps
CPU time 0.93 seconds
Started Jun 05 05:53:05 PM PDT 24
Finished Jun 05 05:53:07 PM PDT 24
Peak memory 201672 kb
Host smart-c4349416-4ac8-4896-96ab-5ea1d4ac56dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205309592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.205309592
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2268901205
Short name T820
Test name
Test status
Simulation time 554968453 ps
CPU time 0.85 seconds
Started Jun 05 05:53:02 PM PDT 24
Finished Jun 05 05:53:04 PM PDT 24
Peak memory 201716 kb
Host smart-b3a4ebed-9686-4532-b80c-8e105a62c648
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268901205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.2268901205
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1181807350
Short name T810
Test name
Test status
Simulation time 359036351 ps
CPU time 0.88 seconds
Started Jun 05 05:52:54 PM PDT 24
Finished Jun 05 05:53:00 PM PDT 24
Peak memory 201676 kb
Host smart-3507b647-743b-47c7-852d-95aeb88d1a2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181807350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.1181807350
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2080193481
Short name T881
Test name
Test status
Simulation time 454367276 ps
CPU time 1.74 seconds
Started Jun 05 05:53:16 PM PDT 24
Finished Jun 05 05:53:21 PM PDT 24
Peak memory 201736 kb
Host smart-d8162853-efc2-4252-a4d6-2566a8542d9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080193481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.2080193481
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.1464478834
Short name T883
Test name
Test status
Simulation time 417839167 ps
CPU time 0.91 seconds
Started Jun 05 05:53:12 PM PDT 24
Finished Jun 05 05:53:14 PM PDT 24
Peak memory 201708 kb
Host smart-348dbbf1-2548-4cc1-b5d0-28bccdcf8a87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464478834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.1464478834
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.25385338
Short name T826
Test name
Test status
Simulation time 614940942 ps
CPU time 0.74 seconds
Started Jun 05 05:53:05 PM PDT 24
Finished Jun 05 05:53:07 PM PDT 24
Peak memory 201680 kb
Host smart-020f0a21-3b7d-4c0f-a51d-60a33288d288
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25385338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.25385338
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.692564676
Short name T882
Test name
Test status
Simulation time 525463305 ps
CPU time 1.98 seconds
Started Jun 05 05:53:19 PM PDT 24
Finished Jun 05 05:53:23 PM PDT 24
Peak memory 201712 kb
Host smart-bd84181a-a939-4b3b-a8c0-6c0b424e70b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692564676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.692564676
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1651442062
Short name T132
Test name
Test status
Simulation time 1089899025 ps
CPU time 4.82 seconds
Started Jun 05 05:52:46 PM PDT 24
Finished Jun 05 05:52:52 PM PDT 24
Peak memory 201944 kb
Host smart-20656936-f2bf-4598-a773-8ade382fccd2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651442062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.1651442062
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1389515021
Short name T139
Test name
Test status
Simulation time 40155797275 ps
CPU time 53.22 seconds
Started Jun 05 05:52:31 PM PDT 24
Finished Jun 05 05:53:25 PM PDT 24
Peak memory 202008 kb
Host smart-aad6e5b9-8e06-43ec-b8da-07fc76c679af
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389515021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.1389515021
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.4088584793
Short name T803
Test name
Test status
Simulation time 918749412 ps
CPU time 2.53 seconds
Started Jun 05 05:52:27 PM PDT 24
Finished Jun 05 05:52:31 PM PDT 24
Peak memory 201720 kb
Host smart-2847c0e2-7705-4f66-a2fb-a003101ba8b4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088584793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.4088584793
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2335805081
Short name T893
Test name
Test status
Simulation time 442660358 ps
CPU time 1.49 seconds
Started Jun 05 05:52:32 PM PDT 24
Finished Jun 05 05:52:35 PM PDT 24
Peak memory 201784 kb
Host smart-5dc9752a-9aba-41e4-9aab-5575764cfb1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335805081 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.2335805081
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.74508114
Short name T141
Test name
Test status
Simulation time 385745720 ps
CPU time 1.77 seconds
Started Jun 05 05:52:34 PM PDT 24
Finished Jun 05 05:52:36 PM PDT 24
Peak memory 201724 kb
Host smart-132cded3-343b-40a1-9126-13a32881086e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74508114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.74508114
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3352459244
Short name T838
Test name
Test status
Simulation time 349448658 ps
CPU time 1.34 seconds
Started Jun 05 05:52:46 PM PDT 24
Finished Jun 05 05:52:48 PM PDT 24
Peak memory 201700 kb
Host smart-bada3283-555b-4c72-9e7c-a791713d3a21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352459244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.3352459244
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.3889780320
Short name T900
Test name
Test status
Simulation time 2234089020 ps
CPU time 9.56 seconds
Started Jun 05 05:52:24 PM PDT 24
Finished Jun 05 05:52:35 PM PDT 24
Peak memory 201792 kb
Host smart-745a718f-5e7d-4bd8-9ac3-05cfbbf0dad1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889780320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.3889780320
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.3330551943
Short name T886
Test name
Test status
Simulation time 632553535 ps
CPU time 3.94 seconds
Started Jun 05 05:52:45 PM PDT 24
Finished Jun 05 05:52:49 PM PDT 24
Peak memory 218040 kb
Host smart-909d4556-360a-4c2c-b4e9-7ce4151c729f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330551943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.3330551943
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.164931504
Short name T913
Test name
Test status
Simulation time 8004525620 ps
CPU time 12.69 seconds
Started Jun 05 05:53:01 PM PDT 24
Finished Jun 05 05:53:14 PM PDT 24
Peak memory 201952 kb
Host smart-cb101c4b-adfb-449e-8f7f-cb048ad128ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164931504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_int
g_err.164931504
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1248431836
Short name T827
Test name
Test status
Simulation time 335703522 ps
CPU time 1.34 seconds
Started Jun 05 05:53:14 PM PDT 24
Finished Jun 05 05:53:17 PM PDT 24
Peak memory 201704 kb
Host smart-d05555bd-5c14-4ab5-b1f7-830b97b15e97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248431836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.1248431836
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2444818768
Short name T851
Test name
Test status
Simulation time 417649536 ps
CPU time 0.77 seconds
Started Jun 05 05:53:12 PM PDT 24
Finished Jun 05 05:53:14 PM PDT 24
Peak memory 201700 kb
Host smart-ea1fd063-47fb-4a8b-89d2-f012fd35bc84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444818768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.2444818768
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.3237817630
Short name T890
Test name
Test status
Simulation time 419897703 ps
CPU time 1.66 seconds
Started Jun 05 05:53:11 PM PDT 24
Finished Jun 05 05:53:14 PM PDT 24
Peak memory 201708 kb
Host smart-a81e601b-0dab-4743-bc65-0a2c065178d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237817630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.3237817630
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.3747811883
Short name T847
Test name
Test status
Simulation time 457392875 ps
CPU time 0.88 seconds
Started Jun 05 05:53:16 PM PDT 24
Finished Jun 05 05:53:20 PM PDT 24
Peak memory 201668 kb
Host smart-21e7b6f5-e168-4000-a9a0-e78af6e4d4b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747811883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.3747811883
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.202962242
Short name T798
Test name
Test status
Simulation time 484791314 ps
CPU time 1.02 seconds
Started Jun 05 05:53:08 PM PDT 24
Finished Jun 05 05:53:10 PM PDT 24
Peak memory 201632 kb
Host smart-d22b7562-42fe-4b61-9d94-e9519004d7a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202962242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.202962242
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.681619635
Short name T845
Test name
Test status
Simulation time 502835875 ps
CPU time 1.78 seconds
Started Jun 05 05:53:24 PM PDT 24
Finished Jun 05 05:53:27 PM PDT 24
Peak memory 201672 kb
Host smart-7d98f6ba-495f-4e5d-b659-2a8f23b0555d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681619635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.681619635
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.296784089
Short name T799
Test name
Test status
Simulation time 312915481 ps
CPU time 1.35 seconds
Started Jun 05 05:53:19 PM PDT 24
Finished Jun 05 05:53:22 PM PDT 24
Peak memory 201724 kb
Host smart-b98f4949-b6bf-4e71-98fa-34f734a354a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296784089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.296784089
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.1591990987
Short name T829
Test name
Test status
Simulation time 497815286 ps
CPU time 1.89 seconds
Started Jun 05 05:53:16 PM PDT 24
Finished Jun 05 05:53:21 PM PDT 24
Peak memory 201668 kb
Host smart-088a727e-b4b7-497e-a512-0d5c00bd23da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591990987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.1591990987
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2966832468
Short name T860
Test name
Test status
Simulation time 504784372 ps
CPU time 0.99 seconds
Started Jun 05 05:53:02 PM PDT 24
Finished Jun 05 05:53:04 PM PDT 24
Peak memory 201672 kb
Host smart-4d568962-b6cd-4aa9-82a3-6d001f203c7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966832468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.2966832468
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.348508241
Short name T840
Test name
Test status
Simulation time 419471776 ps
CPU time 0.76 seconds
Started Jun 05 05:53:12 PM PDT 24
Finished Jun 05 05:53:14 PM PDT 24
Peak memory 201668 kb
Host smart-2385be23-0935-425e-b629-4d212218b520
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348508241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.348508241
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.591078868
Short name T859
Test name
Test status
Simulation time 557002304 ps
CPU time 1.47 seconds
Started Jun 05 05:52:32 PM PDT 24
Finished Jun 05 05:52:34 PM PDT 24
Peak memory 201760 kb
Host smart-31cb453e-8e80-49f1-b9c1-e2be03ae2f5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591078868 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.591078868
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2887315672
Short name T140
Test name
Test status
Simulation time 362589409 ps
CPU time 1.71 seconds
Started Jun 05 05:52:28 PM PDT 24
Finished Jun 05 05:52:31 PM PDT 24
Peak memory 201728 kb
Host smart-d72a210c-d288-4a0b-b29b-600c6c97b89d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887315672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.2887315672
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1018856858
Short name T834
Test name
Test status
Simulation time 511129139 ps
CPU time 0.95 seconds
Started Jun 05 05:52:24 PM PDT 24
Finished Jun 05 05:52:27 PM PDT 24
Peak memory 201712 kb
Host smart-caf1be52-9767-4d7f-b829-dc8dd1d1783c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018856858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.1018856858
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.2958796270
Short name T844
Test name
Test status
Simulation time 4711947692 ps
CPU time 11.57 seconds
Started Jun 05 05:52:50 PM PDT 24
Finished Jun 05 05:53:02 PM PDT 24
Peak memory 201856 kb
Host smart-add0f29d-2bc0-4b4f-9804-2bdae6df0d55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958796270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.2958796270
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1150668039
Short name T867
Test name
Test status
Simulation time 622655080 ps
CPU time 4.19 seconds
Started Jun 05 05:52:53 PM PDT 24
Finished Jun 05 05:52:57 PM PDT 24
Peak memory 217552 kb
Host smart-cbbe3678-af21-4f60-abab-8743512532ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150668039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.1150668039
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1754459290
Short name T848
Test name
Test status
Simulation time 4990851942 ps
CPU time 3.5 seconds
Started Jun 05 05:53:01 PM PDT 24
Finished Jun 05 05:53:06 PM PDT 24
Peak memory 201704 kb
Host smart-391db021-e128-4520-837f-2c584eaa4c1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754459290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.1754459290
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.906194487
Short name T909
Test name
Test status
Simulation time 503774186 ps
CPU time 1.29 seconds
Started Jun 05 05:52:33 PM PDT 24
Finished Jun 05 05:52:35 PM PDT 24
Peak memory 201756 kb
Host smart-bdf3bbe0-8ca9-4684-a0b4-044217b6e1fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906194487 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.906194487
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.2124838028
Short name T877
Test name
Test status
Simulation time 563083668 ps
CPU time 1.53 seconds
Started Jun 05 05:52:21 PM PDT 24
Finished Jun 05 05:52:24 PM PDT 24
Peak memory 201580 kb
Host smart-23176386-8ddf-4577-82b5-1f6a03582f4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124838028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.2124838028
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.752514578
Short name T854
Test name
Test status
Simulation time 413455345 ps
CPU time 1.59 seconds
Started Jun 05 05:53:03 PM PDT 24
Finished Jun 05 05:53:05 PM PDT 24
Peak memory 201540 kb
Host smart-be63e722-62fe-436f-809a-4038bcd750be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752514578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.752514578
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.1100797750
Short name T885
Test name
Test status
Simulation time 3869020244 ps
CPU time 3.47 seconds
Started Jun 05 05:52:29 PM PDT 24
Finished Jun 05 05:52:34 PM PDT 24
Peak memory 201852 kb
Host smart-a18ff826-8906-4492-acb3-3533e7dfea54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100797750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.1100797750
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2647753992
Short name T813
Test name
Test status
Simulation time 588969063 ps
CPU time 2.21 seconds
Started Jun 05 05:52:38 PM PDT 24
Finished Jun 05 05:52:40 PM PDT 24
Peak memory 218336 kb
Host smart-b1d83021-dde7-4b18-aece-66c66da001cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647753992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.2647753992
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1614332998
Short name T916
Test name
Test status
Simulation time 8960660081 ps
CPU time 4.54 seconds
Started Jun 05 05:52:51 PM PDT 24
Finished Jun 05 05:52:57 PM PDT 24
Peak memory 201844 kb
Host smart-b5996828-c43d-4d3a-be8a-012840384271
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614332998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.1614332998
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.4162867394
Short name T98
Test name
Test status
Simulation time 578261164 ps
CPU time 2.06 seconds
Started Jun 05 05:52:49 PM PDT 24
Finished Jun 05 05:52:52 PM PDT 24
Peak memory 201804 kb
Host smart-62dc76cc-1c39-4494-99bf-466ca74dd282
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162867394 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.4162867394
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2919972379
Short name T145
Test name
Test status
Simulation time 315144457 ps
CPU time 1.35 seconds
Started Jun 05 05:52:40 PM PDT 24
Finished Jun 05 05:52:42 PM PDT 24
Peak memory 201704 kb
Host smart-c381ab29-f614-4c80-bbf9-b0ddaf492379
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919972379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.2919972379
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1538634655
Short name T805
Test name
Test status
Simulation time 511804802 ps
CPU time 1.74 seconds
Started Jun 05 05:52:49 PM PDT 24
Finished Jun 05 05:52:51 PM PDT 24
Peak memory 201688 kb
Host smart-cc88dd24-0e94-4b39-b1a4-2e527e5be9f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538634655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.1538634655
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2001383564
Short name T149
Test name
Test status
Simulation time 4300812879 ps
CPU time 10.5 seconds
Started Jun 05 05:52:57 PM PDT 24
Finished Jun 05 05:53:08 PM PDT 24
Peak memory 201976 kb
Host smart-902e52a5-45f0-4e5c-a24d-dc1075e9e6f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001383564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.2001383564
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.478245102
Short name T857
Test name
Test status
Simulation time 597767726 ps
CPU time 3.04 seconds
Started Jun 05 05:52:28 PM PDT 24
Finished Jun 05 05:52:32 PM PDT 24
Peak memory 217988 kb
Host smart-f7e7c3e9-2332-4765-8871-11abf937b681
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478245102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.478245102
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2306028783
Short name T64
Test name
Test status
Simulation time 8257758815 ps
CPU time 7.19 seconds
Started Jun 05 05:52:36 PM PDT 24
Finished Jun 05 05:52:44 PM PDT 24
Peak memory 201964 kb
Host smart-056d707d-04da-4941-8c69-bca890606925
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306028783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.2306028783
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1449238191
Short name T862
Test name
Test status
Simulation time 638537203 ps
CPU time 1.37 seconds
Started Jun 05 05:52:57 PM PDT 24
Finished Jun 05 05:52:59 PM PDT 24
Peak memory 201800 kb
Host smart-a5bebd66-30eb-4a11-902b-a5602e55eec5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449238191 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.1449238191
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.1213505214
Short name T133
Test name
Test status
Simulation time 524390755 ps
CPU time 1.98 seconds
Started Jun 05 05:52:56 PM PDT 24
Finished Jun 05 05:52:59 PM PDT 24
Peak memory 201740 kb
Host smart-3b570117-9af1-4d4c-9e1d-44f50f749282
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213505214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.1213505214
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3885608225
Short name T892
Test name
Test status
Simulation time 551321693 ps
CPU time 0.95 seconds
Started Jun 05 05:52:23 PM PDT 24
Finished Jun 05 05:52:25 PM PDT 24
Peak memory 201836 kb
Host smart-128ab5a4-163b-4709-b57c-afb7378f5f1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885608225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.3885608225
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2012534125
Short name T57
Test name
Test status
Simulation time 4640884914 ps
CPU time 15.35 seconds
Started Jun 05 05:52:42 PM PDT 24
Finished Jun 05 05:52:58 PM PDT 24
Peak memory 202008 kb
Host smart-85c2be32-5f68-47d0-b829-0c0ee83fabc6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012534125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.2012534125
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2561231994
Short name T846
Test name
Test status
Simulation time 4413990652 ps
CPU time 11.9 seconds
Started Jun 05 05:53:00 PM PDT 24
Finished Jun 05 05:53:13 PM PDT 24
Peak memory 201968 kb
Host smart-52ee813c-9a62-4955-9570-e14d1363f148
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561231994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.2561231994
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1389315052
Short name T66
Test name
Test status
Simulation time 470672680 ps
CPU time 1.18 seconds
Started Jun 05 05:52:49 PM PDT 24
Finished Jun 05 05:52:51 PM PDT 24
Peak memory 201752 kb
Host smart-52630210-8ab6-4063-a1a8-23099049cdac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389315052 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.1389315052
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.2728872278
Short name T904
Test name
Test status
Simulation time 585674163 ps
CPU time 1.15 seconds
Started Jun 05 05:52:50 PM PDT 24
Finished Jun 05 05:52:52 PM PDT 24
Peak memory 201732 kb
Host smart-764aaa38-94e0-4a1d-88d2-eb3041625b4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728872278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.2728872278
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3889395664
Short name T843
Test name
Test status
Simulation time 512695780 ps
CPU time 1.3 seconds
Started Jun 05 05:52:47 PM PDT 24
Finished Jun 05 05:52:49 PM PDT 24
Peak memory 201684 kb
Host smart-2004f5ea-a017-4b22-a121-8c8298b54eb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889395664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.3889395664
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.1466968044
Short name T871
Test name
Test status
Simulation time 5144738986 ps
CPU time 1.81 seconds
Started Jun 05 05:52:32 PM PDT 24
Finished Jun 05 05:52:35 PM PDT 24
Peak memory 201964 kb
Host smart-1aa20d17-9196-4c5f-9bb1-a87351e5bbf0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466968044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.1466968044
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3112119406
Short name T880
Test name
Test status
Simulation time 328522872 ps
CPU time 2.98 seconds
Started Jun 05 05:52:49 PM PDT 24
Finished Jun 05 05:52:52 PM PDT 24
Peak memory 210188 kb
Host smart-1dc60f61-15e7-42ee-9231-403a2a9e44fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112119406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.3112119406
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1962414279
Short name T83
Test name
Test status
Simulation time 8720091706 ps
CPU time 11.69 seconds
Started Jun 05 05:52:49 PM PDT 24
Finished Jun 05 05:53:01 PM PDT 24
Peak memory 202000 kb
Host smart-4a4002ac-a991-4416-89d4-6e9cd9c9fdca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962414279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.1962414279
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.2913230104
Short name T682
Test name
Test status
Simulation time 526581852 ps
CPU time 1.3 seconds
Started Jun 05 05:25:36 PM PDT 24
Finished Jun 05 05:25:38 PM PDT 24
Peak memory 201484 kb
Host smart-16655c08-0424-4f51-a9d1-f6d8393ce050
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913230104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.2913230104
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.1224625996
Short name T251
Test name
Test status
Simulation time 163349364816 ps
CPU time 397.24 seconds
Started Jun 05 05:25:28 PM PDT 24
Finished Jun 05 05:32:06 PM PDT 24
Peak memory 201880 kb
Host smart-58663b3c-51d5-4b47-8c8a-64c316d7acfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224625996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.1224625996
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.1832231324
Short name T697
Test name
Test status
Simulation time 337367966813 ps
CPU time 444.98 seconds
Started Jun 05 05:25:31 PM PDT 24
Finished Jun 05 05:32:57 PM PDT 24
Peak memory 201808 kb
Host smart-4aa48428-ab0b-4de2-8af8-e75a436e8095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832231324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.1832231324
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.1015957630
Short name T724
Test name
Test status
Simulation time 163059352306 ps
CPU time 69.35 seconds
Started Jun 05 05:25:35 PM PDT 24
Finished Jun 05 05:26:45 PM PDT 24
Peak memory 201780 kb
Host smart-c4077c8e-69ca-4bc1-aed4-2451200a7f34
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015957630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.1015957630
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.2928355052
Short name T448
Test name
Test status
Simulation time 166863784957 ps
CPU time 51.4 seconds
Started Jun 05 05:25:34 PM PDT 24
Finished Jun 05 05:26:26 PM PDT 24
Peak memory 201868 kb
Host smart-fd63b56f-7ca6-44e8-97fb-afa9c7f5a394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928355052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.2928355052
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.1008148673
Short name T558
Test name
Test status
Simulation time 167899136374 ps
CPU time 380.78 seconds
Started Jun 05 05:25:30 PM PDT 24
Finished Jun 05 05:31:52 PM PDT 24
Peak memory 201820 kb
Host smart-456764a7-c4bc-4f7e-8c08-4848fc8a74d6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008148673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.1008148673
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.4293104519
Short name T343
Test name
Test status
Simulation time 194610936054 ps
CPU time 117.47 seconds
Started Jun 05 05:25:32 PM PDT 24
Finished Jun 05 05:27:31 PM PDT 24
Peak memory 201860 kb
Host smart-5d0d1e3b-ee00-44b0-8820-24411b3b57e1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293104519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.4293104519
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.2200135835
Short name T462
Test name
Test status
Simulation time 201499713551 ps
CPU time 187.66 seconds
Started Jun 05 05:25:32 PM PDT 24
Finished Jun 05 05:28:41 PM PDT 24
Peak memory 201804 kb
Host smart-f14b1b6b-dca5-4f68-a076-7d633aa3d212
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200135835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.2200135835
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.1972324345
Short name T748
Test name
Test status
Simulation time 95251383917 ps
CPU time 341.37 seconds
Started Jun 05 05:25:27 PM PDT 24
Finished Jun 05 05:31:09 PM PDT 24
Peak memory 202144 kb
Host smart-66b78335-ca17-4f37-aec3-61d065256e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972324345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.1972324345
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.2383568331
Short name T684
Test name
Test status
Simulation time 33119034750 ps
CPU time 41.19 seconds
Started Jun 05 05:25:31 PM PDT 24
Finished Jun 05 05:26:13 PM PDT 24
Peak memory 201608 kb
Host smart-ee7cc210-fb33-412f-8ce9-9854ec1a93c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383568331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.2383568331
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.3886381614
Short name T549
Test name
Test status
Simulation time 5240320376 ps
CPU time 13.16 seconds
Started Jun 05 05:25:30 PM PDT 24
Finished Jun 05 05:25:44 PM PDT 24
Peak memory 201620 kb
Host smart-12d3eea0-2c04-44ca-b9cd-b23ac833cd9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886381614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.3886381614
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.3902929397
Short name T110
Test name
Test status
Simulation time 5856803907 ps
CPU time 2.59 seconds
Started Jun 05 05:25:33 PM PDT 24
Finished Jun 05 05:25:36 PM PDT 24
Peak memory 201612 kb
Host smart-45ef53fe-86b3-4452-ae7f-687233d8ad36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902929397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.3902929397
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.2565398722
Short name T783
Test name
Test status
Simulation time 221198924906 ps
CPU time 277.93 seconds
Started Jun 05 05:25:31 PM PDT 24
Finished Jun 05 05:30:10 PM PDT 24
Peak memory 210412 kb
Host smart-7cbd7f9b-dede-4f47-a6b9-6b9d578e323b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565398722 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.2565398722
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.264441250
Short name T449
Test name
Test status
Simulation time 387919761 ps
CPU time 1.08 seconds
Started Jun 05 05:25:36 PM PDT 24
Finished Jun 05 05:25:37 PM PDT 24
Peak memory 201468 kb
Host smart-cd5ddd19-196e-4a72-8578-ea39e55a37eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264441250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.264441250
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.3303540185
Short name T213
Test name
Test status
Simulation time 515904873407 ps
CPU time 1260.43 seconds
Started Jun 05 05:25:38 PM PDT 24
Finished Jun 05 05:46:39 PM PDT 24
Peak memory 201824 kb
Host smart-a28742f3-4cda-43e3-8623-001224b8f8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303540185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.3303540185
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.52291472
Short name T779
Test name
Test status
Simulation time 167136317712 ps
CPU time 96.52 seconds
Started Jun 05 05:25:31 PM PDT 24
Finished Jun 05 05:27:09 PM PDT 24
Peak memory 201780 kb
Host smart-c0e8454e-15b8-4b49-8c9b-b4864b29aa39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52291472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.52291472
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.2475891936
Short name T106
Test name
Test status
Simulation time 327226587416 ps
CPU time 361.05 seconds
Started Jun 05 05:25:30 PM PDT 24
Finished Jun 05 05:31:32 PM PDT 24
Peak memory 201764 kb
Host smart-d68dde6d-da68-4562-8447-720020e53ad5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475891936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.2475891936
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.1135299675
Short name T247
Test name
Test status
Simulation time 482160054743 ps
CPU time 1109.24 seconds
Started Jun 05 05:25:32 PM PDT 24
Finished Jun 05 05:44:03 PM PDT 24
Peak memory 201788 kb
Host smart-26d979f1-169e-4dbf-b255-9058d41e40fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135299675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.1135299675
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.698716232
Short name T481
Test name
Test status
Simulation time 494864652022 ps
CPU time 403.81 seconds
Started Jun 05 05:25:31 PM PDT 24
Finished Jun 05 05:32:17 PM PDT 24
Peak memory 201808 kb
Host smart-53860c1d-1a5f-4cce-aa90-70979868f22e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=698716232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixed
.698716232
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.2295456848
Short name T12
Test name
Test status
Simulation time 177489185494 ps
CPU time 111.43 seconds
Started Jun 05 05:25:31 PM PDT 24
Finished Jun 05 05:27:24 PM PDT 24
Peak memory 202064 kb
Host smart-3986c8e4-34ec-44bf-b745-2d375cc673ac
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295456848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.2295456848
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.1701833608
Short name T660
Test name
Test status
Simulation time 592952555649 ps
CPU time 365.73 seconds
Started Jun 05 05:25:38 PM PDT 24
Finished Jun 05 05:31:44 PM PDT 24
Peak memory 201796 kb
Host smart-8f26bb52-1d7c-4d19-9e4c-3fa84fe8e088
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701833608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.1701833608
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.121465448
Short name T586
Test name
Test status
Simulation time 111311675190 ps
CPU time 611 seconds
Started Jun 05 05:25:40 PM PDT 24
Finished Jun 05 05:35:52 PM PDT 24
Peak memory 202148 kb
Host smart-dc39c46f-bc01-4b4b-8905-752751592cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121465448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.121465448
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.3586156697
Short name T492
Test name
Test status
Simulation time 39915036883 ps
CPU time 94.07 seconds
Started Jun 05 05:25:43 PM PDT 24
Finished Jun 05 05:27:18 PM PDT 24
Peak memory 201628 kb
Host smart-950cefde-5f47-47ae-ae60-b638b65c0ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586156697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.3586156697
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.1307031659
Short name T397
Test name
Test status
Simulation time 3190977407 ps
CPU time 2.68 seconds
Started Jun 05 05:25:44 PM PDT 24
Finished Jun 05 05:25:48 PM PDT 24
Peak memory 201584 kb
Host smart-f8a0f4dc-840b-402e-b619-3456fb04d793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307031659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.1307031659
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.86460060
Short name T68
Test name
Test status
Simulation time 8087098829 ps
CPU time 19.56 seconds
Started Jun 05 05:25:40 PM PDT 24
Finished Jun 05 05:26:00 PM PDT 24
Peak memory 218392 kb
Host smart-ae92750c-dc1d-4594-a48a-6bebf524e00a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86460060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.86460060
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.4219700710
Short name T444
Test name
Test status
Simulation time 5898946685 ps
CPU time 9.46 seconds
Started Jun 05 05:25:34 PM PDT 24
Finished Jun 05 05:25:44 PM PDT 24
Peak memory 201636 kb
Host smart-bd7abdea-5662-4a68-b3ec-238d1978a9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219700710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.4219700710
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.3714157254
Short name T109
Test name
Test status
Simulation time 191714655583 ps
CPU time 46.97 seconds
Started Jun 05 05:25:36 PM PDT 24
Finished Jun 05 05:26:24 PM PDT 24
Peak memory 210180 kb
Host smart-cd76d26d-9407-496b-8284-1c0250a93e64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714157254 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.3714157254
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.671694256
Short name T623
Test name
Test status
Simulation time 411493793 ps
CPU time 1.66 seconds
Started Jun 05 05:26:08 PM PDT 24
Finished Jun 05 05:26:11 PM PDT 24
Peak memory 201516 kb
Host smart-818f6d30-3e4c-4d77-ae46-b8972d043527
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671694256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.671694256
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.432250381
Short name T268
Test name
Test status
Simulation time 498779443242 ps
CPU time 599.07 seconds
Started Jun 05 05:26:07 PM PDT 24
Finished Jun 05 05:36:08 PM PDT 24
Peak memory 201860 kb
Host smart-6fe6b23e-74c5-4afc-a49b-d0c5a630acc9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432250381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gati
ng.432250381
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.9927299
Short name T568
Test name
Test status
Simulation time 163962345837 ps
CPU time 206.28 seconds
Started Jun 05 05:25:59 PM PDT 24
Finished Jun 05 05:29:26 PM PDT 24
Peak memory 201808 kb
Host smart-a7f57ec1-74a8-4cbd-8005-75f9f5f54d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9927299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.9927299
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.867553251
Short name T296
Test name
Test status
Simulation time 322397995110 ps
CPU time 102.33 seconds
Started Jun 05 05:25:59 PM PDT 24
Finished Jun 05 05:27:42 PM PDT 24
Peak memory 201792 kb
Host smart-c99454ef-02f5-4ed6-87a2-26eb6eb4619d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867553251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.867553251
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.3125489163
Short name T31
Test name
Test status
Simulation time 169203590297 ps
CPU time 93.24 seconds
Started Jun 05 05:26:00 PM PDT 24
Finished Jun 05 05:27:33 PM PDT 24
Peak memory 201796 kb
Host smart-084831f4-fd64-4178-950d-e6391b51e4d0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125489163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.3125489163
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.3503901694
Short name T310
Test name
Test status
Simulation time 356876235578 ps
CPU time 565.08 seconds
Started Jun 05 05:26:04 PM PDT 24
Finished Jun 05 05:35:31 PM PDT 24
Peak memory 201820 kb
Host smart-36565fde-3d25-47b7-b3f5-5a20ffb9eaa3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503901694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.3503901694
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.1218537487
Short name T521
Test name
Test status
Simulation time 588043452090 ps
CPU time 1418.83 seconds
Started Jun 05 05:26:07 PM PDT 24
Finished Jun 05 05:49:47 PM PDT 24
Peak memory 201788 kb
Host smart-55d1b01c-7108-4b77-8707-5f62b6a77f82
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218537487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.1218537487
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.3495478207
Short name T55
Test name
Test status
Simulation time 121227130970 ps
CPU time 529.76 seconds
Started Jun 05 05:26:10 PM PDT 24
Finished Jun 05 05:35:00 PM PDT 24
Peak memory 202076 kb
Host smart-af092a6e-a30e-44c6-b6a2-90ef81cec28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495478207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.3495478207
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.3973001487
Short name T53
Test name
Test status
Simulation time 37944635627 ps
CPU time 8.54 seconds
Started Jun 05 05:26:08 PM PDT 24
Finished Jun 05 05:26:18 PM PDT 24
Peak memory 201632 kb
Host smart-022e9a1c-4d00-44f1-9ded-2228d5a10fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973001487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.3973001487
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.3940808202
Short name T772
Test name
Test status
Simulation time 3016728573 ps
CPU time 2.51 seconds
Started Jun 05 05:26:10 PM PDT 24
Finished Jun 05 05:26:13 PM PDT 24
Peak memory 201600 kb
Host smart-b1b45399-0af3-40a0-a261-0924b3542b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940808202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.3940808202
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.1516336286
Short name T615
Test name
Test status
Simulation time 5974174292 ps
CPU time 12.16 seconds
Started Jun 05 05:25:57 PM PDT 24
Finished Jun 05 05:26:09 PM PDT 24
Peak memory 201640 kb
Host smart-239e2919-6dfa-4829-beff-769ce5f4111d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516336286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.1516336286
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.3406548730
Short name T499
Test name
Test status
Simulation time 210953642800 ps
CPU time 245.7 seconds
Started Jun 05 05:26:07 PM PDT 24
Finished Jun 05 05:30:14 PM PDT 24
Peak memory 201852 kb
Host smart-bb90a835-647d-41f0-91cc-3947ddf7eff2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406548730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.3406548730
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.1428472516
Short name T256
Test name
Test status
Simulation time 56001571114 ps
CPU time 112.45 seconds
Started Jun 05 05:26:06 PM PDT 24
Finished Jun 05 05:28:00 PM PDT 24
Peak memory 202516 kb
Host smart-d69b2eb5-92ec-4eb1-95c7-81ad34480437
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428472516 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.1428472516
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.2870874768
Short name T576
Test name
Test status
Simulation time 404983260 ps
CPU time 0.84 seconds
Started Jun 05 05:26:06 PM PDT 24
Finished Jun 05 05:26:08 PM PDT 24
Peak memory 201516 kb
Host smart-c4f4c5a7-4038-44a6-8d54-19e8a305e1e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870874768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.2870874768
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.211071947
Short name T341
Test name
Test status
Simulation time 173237932113 ps
CPU time 211.94 seconds
Started Jun 05 05:26:08 PM PDT 24
Finished Jun 05 05:29:42 PM PDT 24
Peak memory 201796 kb
Host smart-f12d3f8b-65c5-46ac-a017-b146322dc46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211071947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.211071947
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.3555971342
Short name T754
Test name
Test status
Simulation time 496347636500 ps
CPU time 284.72 seconds
Started Jun 05 05:26:06 PM PDT 24
Finished Jun 05 05:30:53 PM PDT 24
Peak memory 201812 kb
Host smart-2705132c-82d0-47f9-89d4-a25efff43294
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555971342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.3555971342
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.2769104042
Short name T534
Test name
Test status
Simulation time 492743599314 ps
CPU time 1165.14 seconds
Started Jun 05 05:26:05 PM PDT 24
Finished Jun 05 05:45:31 PM PDT 24
Peak memory 201732 kb
Host smart-d548bb36-09d3-4881-bd1d-ed47e8f2f2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769104042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.2769104042
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.617686926
Short name T538
Test name
Test status
Simulation time 165523113457 ps
CPU time 423.55 seconds
Started Jun 05 05:26:07 PM PDT 24
Finished Jun 05 05:33:12 PM PDT 24
Peak memory 201880 kb
Host smart-c0d12ae6-f526-460d-892f-b491c68f785d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=617686926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fixe
d.617686926
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.2554894899
Short name T339
Test name
Test status
Simulation time 203400677237 ps
CPU time 185.9 seconds
Started Jun 05 05:26:06 PM PDT 24
Finished Jun 05 05:29:13 PM PDT 24
Peak memory 201820 kb
Host smart-53ee5a52-cd11-44ba-9120-77befbf8c4d0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554894899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.2554894899
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.2403360507
Short name T628
Test name
Test status
Simulation time 390721307416 ps
CPU time 796.65 seconds
Started Jun 05 05:26:06 PM PDT 24
Finished Jun 05 05:39:24 PM PDT 24
Peak memory 201792 kb
Host smart-53692c8d-72dd-4aa0-86d5-eb1237980e99
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403360507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.2403360507
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.3190730725
Short name T371
Test name
Test status
Simulation time 40703359049 ps
CPU time 95.37 seconds
Started Jun 05 05:26:06 PM PDT 24
Finished Jun 05 05:27:43 PM PDT 24
Peak memory 201628 kb
Host smart-e2919d40-3fb7-417e-ac43-1f5e74ded9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190730725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.3190730725
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.1820610645
Short name T612
Test name
Test status
Simulation time 3510810146 ps
CPU time 9.47 seconds
Started Jun 05 05:26:05 PM PDT 24
Finished Jun 05 05:26:16 PM PDT 24
Peak memory 201556 kb
Host smart-441ce564-a1a3-47ab-b44f-e05cd3bc63cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820610645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.1820610645
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.3098837299
Short name T690
Test name
Test status
Simulation time 5811363636 ps
CPU time 7.39 seconds
Started Jun 05 05:26:08 PM PDT 24
Finished Jun 05 05:26:16 PM PDT 24
Peak memory 201616 kb
Host smart-0d7f5b2b-65e8-4057-a6cb-4c134afcacec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098837299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.3098837299
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.3483266618
Short name T76
Test name
Test status
Simulation time 6749741527 ps
CPU time 16.98 seconds
Started Jun 05 05:26:08 PM PDT 24
Finished Jun 05 05:26:27 PM PDT 24
Peak memory 201620 kb
Host smart-2f2efcf3-abfb-437f-9178-785a5b08c990
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483266618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.3483266618
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.3649735820
Short name T309
Test name
Test status
Simulation time 426642503185 ps
CPU time 320.97 seconds
Started Jun 05 05:26:07 PM PDT 24
Finished Jun 05 05:31:29 PM PDT 24
Peak memory 218584 kb
Host smart-614e4dd1-6179-4d5c-88c3-db972c199a8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649735820 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.3649735820
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.178912931
Short name T493
Test name
Test status
Simulation time 540352672 ps
CPU time 1.22 seconds
Started Jun 05 05:26:09 PM PDT 24
Finished Jun 05 05:26:11 PM PDT 24
Peak memory 201464 kb
Host smart-c6fec209-a60b-4b01-9a61-94d23a268fee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178912931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.178912931
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.2879362549
Short name T230
Test name
Test status
Simulation time 521750213583 ps
CPU time 258.02 seconds
Started Jun 05 05:26:07 PM PDT 24
Finished Jun 05 05:30:27 PM PDT 24
Peak memory 201872 kb
Host smart-ba5212c9-65ac-4052-a513-893c9ef54463
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879362549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.2879362549
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.2142865025
Short name T592
Test name
Test status
Simulation time 359007447740 ps
CPU time 393.58 seconds
Started Jun 05 05:26:06 PM PDT 24
Finished Jun 05 05:32:42 PM PDT 24
Peak memory 201856 kb
Host smart-076af2dd-4755-4319-a1e5-1aa3ab2442ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142865025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.2142865025
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.2561782
Short name T721
Test name
Test status
Simulation time 167815051884 ps
CPU time 108.73 seconds
Started Jun 05 05:26:06 PM PDT 24
Finished Jun 05 05:27:57 PM PDT 24
Peak memory 201760 kb
Host smart-5615ede5-064c-4d5a-b595-0ac9e28fb3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.2561782
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.1887687575
Short name T533
Test name
Test status
Simulation time 489507972465 ps
CPU time 322.66 seconds
Started Jun 05 05:26:06 PM PDT 24
Finished Jun 05 05:31:29 PM PDT 24
Peak memory 201820 kb
Host smart-d2cd9653-e1d5-4466-9d0f-ed6aac2f84e8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887687575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.1887687575
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.4178636602
Short name T582
Test name
Test status
Simulation time 336265784319 ps
CPU time 406.34 seconds
Started Jun 05 05:26:06 PM PDT 24
Finished Jun 05 05:32:53 PM PDT 24
Peak memory 202028 kb
Host smart-e2a39d5c-6ebd-4968-97b9-822f47c8fa6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178636602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.4178636602
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.397042047
Short name T715
Test name
Test status
Simulation time 159816548614 ps
CPU time 371.74 seconds
Started Jun 05 05:26:09 PM PDT 24
Finished Jun 05 05:32:22 PM PDT 24
Peak memory 201800 kb
Host smart-e66c8c06-099a-4fa0-b23c-c6e7d6d3b170
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=397042047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fixe
d.397042047
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.603113631
Short name T726
Test name
Test status
Simulation time 598712893724 ps
CPU time 331.74 seconds
Started Jun 05 05:26:06 PM PDT 24
Finished Jun 05 05:31:40 PM PDT 24
Peak memory 201808 kb
Host smart-52ecd2e0-f5d8-470d-8f83-2c38d04304af
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603113631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_
wakeup.603113631
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.448544843
Short name T427
Test name
Test status
Simulation time 194671576408 ps
CPU time 135.97 seconds
Started Jun 05 05:26:05 PM PDT 24
Finished Jun 05 05:28:22 PM PDT 24
Peak memory 201800 kb
Host smart-e4edff3b-df99-4238-896f-29995523f283
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448544843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
adc_ctrl_filters_wakeup_fixed.448544843
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.712487573
Short name T121
Test name
Test status
Simulation time 114592939016 ps
CPU time 419.61 seconds
Started Jun 05 05:26:09 PM PDT 24
Finished Jun 05 05:33:10 PM PDT 24
Peak memory 202172 kb
Host smart-3dd03bd1-ca09-4e24-8aab-17e257f824d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712487573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.712487573
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.1460891250
Short name T408
Test name
Test status
Simulation time 33334173306 ps
CPU time 19.4 seconds
Started Jun 05 05:26:06 PM PDT 24
Finished Jun 05 05:26:27 PM PDT 24
Peak memory 201628 kb
Host smart-d5d3c132-0c87-4aec-8f68-f702548759e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460891250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.1460891250
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.1809603874
Short name T547
Test name
Test status
Simulation time 2962845454 ps
CPU time 4.94 seconds
Started Jun 05 05:26:09 PM PDT 24
Finished Jun 05 05:26:15 PM PDT 24
Peak memory 201596 kb
Host smart-0a10bf01-2236-44c1-b28f-6ea81820f6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809603874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.1809603874
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.1109532018
Short name T735
Test name
Test status
Simulation time 5779422449 ps
CPU time 4.17 seconds
Started Jun 05 05:26:06 PM PDT 24
Finished Jun 05 05:26:11 PM PDT 24
Peak memory 201612 kb
Host smart-cef7a8d5-4aeb-4b8f-909c-f6ea7ab8bd23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109532018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.1109532018
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.191668974
Short name T362
Test name
Test status
Simulation time 245869576264 ps
CPU time 388.63 seconds
Started Jun 05 05:26:07 PM PDT 24
Finished Jun 05 05:32:37 PM PDT 24
Peak memory 202160 kb
Host smart-b25130ee-fa6c-47de-b83d-8e449e55b8e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191668974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all.
191668974
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.2765719676
Short name T22
Test name
Test status
Simulation time 19417908000 ps
CPU time 14.08 seconds
Started Jun 05 05:26:06 PM PDT 24
Finished Jun 05 05:26:21 PM PDT 24
Peak memory 210180 kb
Host smart-81bedab7-6090-4b67-aad3-dc3575dfc7b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765719676 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.2765719676
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.4040276492
Short name T762
Test name
Test status
Simulation time 373504078 ps
CPU time 1.33 seconds
Started Jun 05 05:26:12 PM PDT 24
Finished Jun 05 05:26:14 PM PDT 24
Peak memory 201512 kb
Host smart-ae2be028-6c7c-4c89-8b0b-932ade4cb3f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040276492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.4040276492
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.1868045182
Short name T34
Test name
Test status
Simulation time 360238378285 ps
CPU time 405.33 seconds
Started Jun 05 05:26:08 PM PDT 24
Finished Jun 05 05:32:54 PM PDT 24
Peak memory 201876 kb
Host smart-966ae334-971c-4727-a8e8-e0a6f791e855
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868045182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.1868045182
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.3850282763
Short name T302
Test name
Test status
Simulation time 328986836443 ps
CPU time 390.77 seconds
Started Jun 05 05:26:07 PM PDT 24
Finished Jun 05 05:32:40 PM PDT 24
Peak memory 201808 kb
Host smart-cbc0523c-c4e2-4d93-9a54-254e87f172f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850282763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.3850282763
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.448520919
Short name T784
Test name
Test status
Simulation time 328888165942 ps
CPU time 726.44 seconds
Started Jun 05 05:26:04 PM PDT 24
Finished Jun 05 05:38:11 PM PDT 24
Peak memory 201788 kb
Host smart-a738b618-3452-4694-a219-52e92dbab134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448520919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.448520919
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.2321123179
Short name T419
Test name
Test status
Simulation time 326590024401 ps
CPU time 807.34 seconds
Started Jun 05 05:26:08 PM PDT 24
Finished Jun 05 05:39:37 PM PDT 24
Peak memory 201712 kb
Host smart-f0e3a178-ad76-4fc8-ad10-5de92722f34c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321123179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.2321123179
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.3817766210
Short name T308
Test name
Test status
Simulation time 326367147369 ps
CPU time 195.02 seconds
Started Jun 05 05:26:07 PM PDT 24
Finished Jun 05 05:29:23 PM PDT 24
Peak memory 201880 kb
Host smart-fbc03138-1019-4892-b6cf-a4b4b2527647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817766210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.3817766210
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.713201984
Short name T99
Test name
Test status
Simulation time 161063256464 ps
CPU time 98.82 seconds
Started Jun 05 05:26:07 PM PDT 24
Finished Jun 05 05:27:47 PM PDT 24
Peak memory 201800 kb
Host smart-a5d56863-7be8-456d-af77-0049dde17b4e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=713201984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fixe
d.713201984
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.4045375717
Short name T215
Test name
Test status
Simulation time 499325386957 ps
CPU time 296.67 seconds
Started Jun 05 05:26:08 PM PDT 24
Finished Jun 05 05:31:06 PM PDT 24
Peak memory 201892 kb
Host smart-09b0cd8f-22c2-41c9-9c67-be2d9a830685
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045375717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.4045375717
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.3772988936
Short name T460
Test name
Test status
Simulation time 118682094815 ps
CPU time 410.55 seconds
Started Jun 05 05:26:12 PM PDT 24
Finished Jun 05 05:33:03 PM PDT 24
Peak memory 202088 kb
Host smart-1af09fec-bc4f-434f-bed0-216f12c8fc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772988936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.3772988936
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.4015354309
Short name T536
Test name
Test status
Simulation time 45416669046 ps
CPU time 107.89 seconds
Started Jun 05 05:26:08 PM PDT 24
Finished Jun 05 05:27:57 PM PDT 24
Peak memory 201576 kb
Host smart-7402f897-68e7-49b6-aa28-8a02287f4f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015354309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.4015354309
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.4046763045
Short name T603
Test name
Test status
Simulation time 3525552853 ps
CPU time 1.74 seconds
Started Jun 05 05:26:07 PM PDT 24
Finished Jun 05 05:26:10 PM PDT 24
Peak memory 201588 kb
Host smart-9b8cc27b-498c-46ca-9696-6fc19a483bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046763045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.4046763045
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.3003019440
Short name T115
Test name
Test status
Simulation time 5783982013 ps
CPU time 4.58 seconds
Started Jun 05 05:26:08 PM PDT 24
Finished Jun 05 05:26:14 PM PDT 24
Peak memory 201628 kb
Host smart-7dc8efce-8429-4c24-a696-2e6e3fc90927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003019440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.3003019440
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.450494651
Short name T505
Test name
Test status
Simulation time 271277187104 ps
CPU time 328.61 seconds
Started Jun 05 05:26:15 PM PDT 24
Finished Jun 05 05:31:44 PM PDT 24
Peak memory 202120 kb
Host smart-acb59e3a-698a-465d-8336-8c6ef597eeba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450494651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all.
450494651
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.1515700272
Short name T714
Test name
Test status
Simulation time 90612858412 ps
CPU time 125.56 seconds
Started Jun 05 05:26:13 PM PDT 24
Finished Jun 05 05:28:19 PM PDT 24
Peak memory 210484 kb
Host smart-7b050339-ffd5-43f5-a86f-e767f4d5ef35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515700272 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.1515700272
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.2953830950
Short name T232
Test name
Test status
Simulation time 205061349252 ps
CPU time 232.93 seconds
Started Jun 05 05:26:18 PM PDT 24
Finished Jun 05 05:30:12 PM PDT 24
Peak memory 201788 kb
Host smart-006849f3-b19f-45d4-96ad-ec28b533a789
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953830950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.2953830950
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.3267496912
Short name T234
Test name
Test status
Simulation time 162388368675 ps
CPU time 209.22 seconds
Started Jun 05 05:26:17 PM PDT 24
Finished Jun 05 05:29:47 PM PDT 24
Peak memory 201808 kb
Host smart-83b4a1a6-818f-4351-8b28-5457701251c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267496912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.3267496912
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.3894222475
Short name T526
Test name
Test status
Simulation time 166186246029 ps
CPU time 404.29 seconds
Started Jun 05 05:26:14 PM PDT 24
Finished Jun 05 05:32:59 PM PDT 24
Peak memory 201804 kb
Host smart-6e87fa9a-0520-481f-9175-3a4d0cad4721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894222475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.3894222475
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.587636916
Short name T205
Test name
Test status
Simulation time 161481246687 ps
CPU time 98.43 seconds
Started Jun 05 05:26:18 PM PDT 24
Finished Jun 05 05:27:57 PM PDT 24
Peak memory 201800 kb
Host smart-03773fe6-db5a-4283-aa2f-809d18e08e89
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=587636916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrup
t_fixed.587636916
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.1182368254
Short name T216
Test name
Test status
Simulation time 501951191498 ps
CPU time 304.46 seconds
Started Jun 05 05:26:12 PM PDT 24
Finished Jun 05 05:31:17 PM PDT 24
Peak memory 201812 kb
Host smart-f0b06bda-bcc5-4054-9658-c52c634a43f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182368254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.1182368254
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.2793241768
Short name T474
Test name
Test status
Simulation time 163167033294 ps
CPU time 171.6 seconds
Started Jun 05 05:26:18 PM PDT 24
Finished Jun 05 05:29:10 PM PDT 24
Peak memory 201856 kb
Host smart-04888108-b69a-497c-b566-16fd2c450b86
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793241768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.2793241768
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.369072505
Short name T176
Test name
Test status
Simulation time 185622935273 ps
CPU time 69.53 seconds
Started Jun 05 05:26:13 PM PDT 24
Finished Jun 05 05:27:23 PM PDT 24
Peak memory 201916 kb
Host smart-9799ba86-d3a5-4589-8c32-87b6db486faa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369072505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_
wakeup.369072505
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.3057645585
Short name T514
Test name
Test status
Simulation time 603267181131 ps
CPU time 622.21 seconds
Started Jun 05 05:26:12 PM PDT 24
Finished Jun 05 05:36:35 PM PDT 24
Peak memory 201992 kb
Host smart-ec9ee3b0-7dd6-409f-9c7a-086e36ec53bf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057645585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.3057645585
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.2859827126
Short name T694
Test name
Test status
Simulation time 100775947032 ps
CPU time 557.13 seconds
Started Jun 05 05:26:14 PM PDT 24
Finished Jun 05 05:35:32 PM PDT 24
Peak memory 202152 kb
Host smart-111fe01d-285c-48ae-8742-604baccd3402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859827126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.2859827126
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.274105007
Short name T501
Test name
Test status
Simulation time 44778112897 ps
CPU time 16.32 seconds
Started Jun 05 05:26:19 PM PDT 24
Finished Jun 05 05:26:36 PM PDT 24
Peak memory 201600 kb
Host smart-bc6bd020-1c70-4c0d-b74f-baf4e199d937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274105007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.274105007
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.573776369
Short name T508
Test name
Test status
Simulation time 4870136597 ps
CPU time 6.76 seconds
Started Jun 05 05:26:14 PM PDT 24
Finished Jun 05 05:26:21 PM PDT 24
Peak memory 201628 kb
Host smart-323c31c8-663f-4849-8e8f-1396eee64786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573776369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.573776369
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.3667949339
Short name T495
Test name
Test status
Simulation time 5825101041 ps
CPU time 4.31 seconds
Started Jun 05 05:26:20 PM PDT 24
Finished Jun 05 05:26:25 PM PDT 24
Peak memory 201616 kb
Host smart-5650c3ee-82cc-43c1-a2e7-d22068aca330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667949339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.3667949339
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.323329554
Short name T155
Test name
Test status
Simulation time 525414914874 ps
CPU time 512.67 seconds
Started Jun 05 05:26:20 PM PDT 24
Finished Jun 05 05:34:54 PM PDT 24
Peak memory 201788 kb
Host smart-1f5f5f33-9036-4b20-9043-68a2160d539b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323329554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all.
323329554
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.966417147
Short name T18
Test name
Test status
Simulation time 207001425062 ps
CPU time 131.05 seconds
Started Jun 05 05:26:14 PM PDT 24
Finished Jun 05 05:28:25 PM PDT 24
Peak memory 210116 kb
Host smart-54338b1f-774b-4ca7-bc09-c589b85588dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966417147 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.966417147
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.1262656496
Short name T486
Test name
Test status
Simulation time 450699969 ps
CPU time 1.19 seconds
Started Jun 05 05:26:18 PM PDT 24
Finished Jun 05 05:26:20 PM PDT 24
Peak memory 201508 kb
Host smart-858ec30e-67db-4371-b7d7-3e6caf00429d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262656496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.1262656496
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.3876929400
Short name T563
Test name
Test status
Simulation time 514913222441 ps
CPU time 635.75 seconds
Started Jun 05 05:26:13 PM PDT 24
Finished Jun 05 05:36:49 PM PDT 24
Peak memory 201992 kb
Host smart-3eebdb8e-00eb-4521-94a9-1535c5a960b0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876929400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.3876929400
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.1112803815
Short name T414
Test name
Test status
Simulation time 329841267949 ps
CPU time 225.65 seconds
Started Jun 05 05:26:17 PM PDT 24
Finished Jun 05 05:30:03 PM PDT 24
Peak memory 201824 kb
Host smart-89bc698d-6f56-4898-bf4d-bb1820b76455
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112803815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.1112803815
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.3762219080
Short name T128
Test name
Test status
Simulation time 162431592447 ps
CPU time 79.85 seconds
Started Jun 05 05:26:14 PM PDT 24
Finished Jun 05 05:27:34 PM PDT 24
Peak memory 201860 kb
Host smart-8f444b1f-cbba-4322-a4f4-862f7e78fb67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762219080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.3762219080
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.3197120978
Short name T125
Test name
Test status
Simulation time 331790233620 ps
CPU time 217.51 seconds
Started Jun 05 05:26:19 PM PDT 24
Finished Jun 05 05:29:57 PM PDT 24
Peak memory 201776 kb
Host smart-8bf26424-50d3-4337-8d5e-f1915ef6f389
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197120978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.3197120978
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.3579489030
Short name T281
Test name
Test status
Simulation time 170795327252 ps
CPU time 109.91 seconds
Started Jun 05 05:26:14 PM PDT 24
Finished Jun 05 05:28:04 PM PDT 24
Peak memory 201884 kb
Host smart-27ec78ac-3f37-4c0d-b3b3-0881a5cd4f62
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579489030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.3579489030
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.1594540879
Short name T650
Test name
Test status
Simulation time 412728977860 ps
CPU time 455.57 seconds
Started Jun 05 05:26:13 PM PDT 24
Finished Jun 05 05:33:49 PM PDT 24
Peak memory 201812 kb
Host smart-a3cafd9f-f7a3-43bb-bbce-a12b2fc7704a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594540879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.1594540879
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.1775466604
Short name T387
Test name
Test status
Simulation time 37220644506 ps
CPU time 23.46 seconds
Started Jun 05 05:26:17 PM PDT 24
Finished Jun 05 05:26:40 PM PDT 24
Peak memory 201600 kb
Host smart-7f710493-383b-41e2-9fc4-ad329b57ea3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775466604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.1775466604
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.1222647589
Short name T2
Test name
Test status
Simulation time 5779878743 ps
CPU time 10.21 seconds
Started Jun 05 05:26:19 PM PDT 24
Finished Jun 05 05:26:30 PM PDT 24
Peak memory 201624 kb
Host smart-27184d47-abe6-463f-83f7-8f450b87ab8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222647589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.1222647589
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.3814211016
Short name T179
Test name
Test status
Simulation time 6021012433 ps
CPU time 15.41 seconds
Started Jun 05 05:26:16 PM PDT 24
Finished Jun 05 05:26:32 PM PDT 24
Peak memory 201636 kb
Host smart-e6082d4f-08ee-46b6-9cd8-648ddf19de92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814211016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.3814211016
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.1158421535
Short name T39
Test name
Test status
Simulation time 207854308273 ps
CPU time 127.94 seconds
Started Jun 05 05:26:21 PM PDT 24
Finished Jun 05 05:28:29 PM PDT 24
Peak memory 201868 kb
Host smart-594a3f30-c95c-472f-b669-284bdc24e686
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158421535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.1158421535
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.1690959049
Short name T331
Test name
Test status
Simulation time 179397609118 ps
CPU time 85.14 seconds
Started Jun 05 05:26:22 PM PDT 24
Finished Jun 05 05:27:48 PM PDT 24
Peak memory 210112 kb
Host smart-4638461e-71fa-4771-b3e2-e0434003bc27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690959049 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.1690959049
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.2772901937
Short name T739
Test name
Test status
Simulation time 432017826 ps
CPU time 0.75 seconds
Started Jun 05 05:26:29 PM PDT 24
Finished Jun 05 05:26:30 PM PDT 24
Peak memory 201504 kb
Host smart-13e16f7d-9bd8-4af6-804c-45b7cd8415a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772901937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.2772901937
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.3424375327
Short name T217
Test name
Test status
Simulation time 358425697308 ps
CPU time 864.88 seconds
Started Jun 05 05:26:19 PM PDT 24
Finished Jun 05 05:40:44 PM PDT 24
Peak memory 201796 kb
Host smart-27cb47e1-269f-4349-b159-56444f47139b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424375327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.3424375327
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.1408630082
Short name T467
Test name
Test status
Simulation time 164167521012 ps
CPU time 183.58 seconds
Started Jun 05 05:26:21 PM PDT 24
Finished Jun 05 05:29:25 PM PDT 24
Peak memory 201776 kb
Host smart-9e18b783-7791-46be-96b7-45679ce765a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408630082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.1408630082
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.3570449461
Short name T464
Test name
Test status
Simulation time 331811317584 ps
CPU time 733.26 seconds
Started Jun 05 05:26:20 PM PDT 24
Finished Jun 05 05:38:34 PM PDT 24
Peak memory 201796 kb
Host smart-019b24f0-502e-4496-9c27-4683432baa67
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570449461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.3570449461
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.2987039169
Short name T335
Test name
Test status
Simulation time 325904187435 ps
CPU time 796.96 seconds
Started Jun 05 05:26:21 PM PDT 24
Finished Jun 05 05:39:39 PM PDT 24
Peak memory 201800 kb
Host smart-9067729c-5bc4-4894-82b4-274b939c2cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987039169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.2987039169
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.141935731
Short name T214
Test name
Test status
Simulation time 489324103209 ps
CPU time 291.11 seconds
Started Jun 05 05:26:19 PM PDT 24
Finished Jun 05 05:31:10 PM PDT 24
Peak memory 201820 kb
Host smart-600f8204-d0a7-4718-842a-0f2d66116d2f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=141935731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fixe
d.141935731
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.1432994921
Short name T665
Test name
Test status
Simulation time 542721199788 ps
CPU time 1190.13 seconds
Started Jun 05 05:26:21 PM PDT 24
Finished Jun 05 05:46:12 PM PDT 24
Peak memory 201760 kb
Host smart-d4c67530-1bb5-45c0-9a95-d34dda528708
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432994921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.1432994921
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.1631630606
Short name T542
Test name
Test status
Simulation time 393065338176 ps
CPU time 453.44 seconds
Started Jun 05 05:26:21 PM PDT 24
Finished Jun 05 05:33:55 PM PDT 24
Peak memory 201812 kb
Host smart-17e1f32d-9eba-4d7b-adae-8f8d508aef20
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631630606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.1631630606
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.2968733776
Short name T604
Test name
Test status
Simulation time 83943572849 ps
CPU time 381.18 seconds
Started Jun 05 05:26:27 PM PDT 24
Finished Jun 05 05:32:49 PM PDT 24
Peak memory 202160 kb
Host smart-e3dc5cab-a569-400b-8c7c-72c03ab38d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968733776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.2968733776
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.3319061591
Short name T180
Test name
Test status
Simulation time 38223016070 ps
CPU time 23.12 seconds
Started Jun 05 05:26:27 PM PDT 24
Finished Jun 05 05:26:50 PM PDT 24
Peak memory 201560 kb
Host smart-917f5b49-b6b7-4507-a78a-aeb2cbc3af75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319061591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.3319061591
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.1054523263
Short name T681
Test name
Test status
Simulation time 4521347834 ps
CPU time 1.69 seconds
Started Jun 05 05:26:20 PM PDT 24
Finished Jun 05 05:26:22 PM PDT 24
Peak memory 201604 kb
Host smart-4d7aeaac-e25c-421a-9588-5675a6a34c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054523263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.1054523263
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.883742757
Short name T5
Test name
Test status
Simulation time 5732998232 ps
CPU time 8.33 seconds
Started Jun 05 05:26:24 PM PDT 24
Finished Jun 05 05:26:33 PM PDT 24
Peak memory 201640 kb
Host smart-cf7f3f10-5ef9-4580-bc5a-548f121a2468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883742757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.883742757
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.121590291
Short name T294
Test name
Test status
Simulation time 233958264673 ps
CPU time 526.62 seconds
Started Jun 05 05:26:30 PM PDT 24
Finished Jun 05 05:35:17 PM PDT 24
Peak memory 201884 kb
Host smart-6d49e72f-ef5a-4df9-bc75-02789d498ba3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121590291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all.
121590291
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.2906502638
Short name T254
Test name
Test status
Simulation time 30872987612 ps
CPU time 55.96 seconds
Started Jun 05 05:26:27 PM PDT 24
Finished Jun 05 05:27:23 PM PDT 24
Peak memory 201920 kb
Host smart-70a6ffc3-781c-4bdc-8739-feb619377f0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906502638 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.2906502638
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.1834256063
Short name T756
Test name
Test status
Simulation time 395071149 ps
CPU time 0.77 seconds
Started Jun 05 05:26:36 PM PDT 24
Finished Jun 05 05:26:37 PM PDT 24
Peak memory 201512 kb
Host smart-aa2883ef-27ab-4ac4-b26e-3f27855d147c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834256063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.1834256063
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.3748346646
Short name T15
Test name
Test status
Simulation time 344515710560 ps
CPU time 714.28 seconds
Started Jun 05 05:26:35 PM PDT 24
Finished Jun 05 05:38:30 PM PDT 24
Peak memory 201852 kb
Host smart-9e3dd312-0a55-47c0-a457-bc0b9f2af6b8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748346646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.3748346646
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.3679552095
Short name T322
Test name
Test status
Simulation time 175348708304 ps
CPU time 287.82 seconds
Started Jun 05 05:26:35 PM PDT 24
Finished Jun 05 05:31:23 PM PDT 24
Peak memory 201808 kb
Host smart-5587efc7-7f5c-4550-8c98-bda76e2e8be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679552095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.3679552095
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.3672338745
Short name T472
Test name
Test status
Simulation time 334242020819 ps
CPU time 843.76 seconds
Started Jun 05 05:26:28 PM PDT 24
Finished Jun 05 05:40:33 PM PDT 24
Peak memory 201772 kb
Host smart-feb2199f-321a-4a13-963d-7a27655ac059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672338745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.3672338745
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.1120543589
Short name T559
Test name
Test status
Simulation time 326152694702 ps
CPU time 77.58 seconds
Started Jun 05 05:26:29 PM PDT 24
Finished Jun 05 05:27:47 PM PDT 24
Peak memory 201808 kb
Host smart-60807ade-3145-43a2-ab4b-e7ffd6ab31d2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120543589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.1120543589
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.3304120011
Short name T599
Test name
Test status
Simulation time 163644139547 ps
CPU time 397.84 seconds
Started Jun 05 05:26:26 PM PDT 24
Finished Jun 05 05:33:05 PM PDT 24
Peak memory 201812 kb
Host smart-aa2d33d3-e839-4a66-9255-5c15a2088e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304120011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.3304120011
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.3772915929
Short name T664
Test name
Test status
Simulation time 331825879713 ps
CPU time 220.84 seconds
Started Jun 05 05:26:28 PM PDT 24
Finished Jun 05 05:30:10 PM PDT 24
Peak memory 201768 kb
Host smart-712a38dd-db7e-4762-8bcf-00eb77bfeacd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772915929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.3772915929
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.1042405199
Short name T693
Test name
Test status
Simulation time 355352021545 ps
CPU time 875.9 seconds
Started Jun 05 05:26:35 PM PDT 24
Finished Jun 05 05:41:11 PM PDT 24
Peak memory 201880 kb
Host smart-cea92652-63b1-4972-bb55-e6618758a971
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042405199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.1042405199
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.3163330396
Short name T588
Test name
Test status
Simulation time 210310434489 ps
CPU time 133.34 seconds
Started Jun 05 05:26:36 PM PDT 24
Finished Jun 05 05:28:50 PM PDT 24
Peak memory 201796 kb
Host smart-bb9e433e-321d-4ec5-8329-bba4f18c4b5c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163330396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.3163330396
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.4090258834
Short name T640
Test name
Test status
Simulation time 22861672266 ps
CPU time 52.09 seconds
Started Jun 05 05:26:35 PM PDT 24
Finished Jun 05 05:27:28 PM PDT 24
Peak memory 201636 kb
Host smart-a5a260e9-6822-462b-900f-e888b27e07a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090258834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.4090258834
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.515185558
Short name T465
Test name
Test status
Simulation time 3800476314 ps
CPU time 5.56 seconds
Started Jun 05 05:26:43 PM PDT 24
Finished Jun 05 05:26:49 PM PDT 24
Peak memory 201620 kb
Host smart-d30cc8e9-dc08-4b04-8701-6559a274376d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515185558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.515185558
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.543142056
Short name T510
Test name
Test status
Simulation time 6043320363 ps
CPU time 2.69 seconds
Started Jun 05 05:26:28 PM PDT 24
Finished Jun 05 05:26:31 PM PDT 24
Peak memory 201636 kb
Host smart-2ee36164-ea1b-43b8-b626-bfc09f1df5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543142056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.543142056
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.597673566
Short name T491
Test name
Test status
Simulation time 273469095602 ps
CPU time 595.81 seconds
Started Jun 05 05:26:34 PM PDT 24
Finished Jun 05 05:36:31 PM PDT 24
Peak memory 201828 kb
Host smart-b92c8eea-9817-4c11-956f-fe154acf87fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597673566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all.
597673566
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.1409348672
Short name T760
Test name
Test status
Simulation time 52795615302 ps
CPU time 26.44 seconds
Started Jun 05 05:26:34 PM PDT 24
Finished Jun 05 05:27:01 PM PDT 24
Peak memory 202080 kb
Host smart-1d000a05-8825-4880-8eaf-4eddb67819d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409348672 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.1409348672
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.3470681062
Short name T541
Test name
Test status
Simulation time 338280090 ps
CPU time 1.16 seconds
Started Jun 05 05:26:51 PM PDT 24
Finished Jun 05 05:26:52 PM PDT 24
Peak memory 201504 kb
Host smart-a39156b7-1b38-4eb8-b453-b9b8be11f0cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470681062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.3470681062
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.756703917
Short name T298
Test name
Test status
Simulation time 493702432959 ps
CPU time 534.1 seconds
Started Jun 05 05:26:45 PM PDT 24
Finished Jun 05 05:35:39 PM PDT 24
Peak memory 201764 kb
Host smart-d235b537-0f40-42d1-a368-7e2af33194df
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756703917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gati
ng.756703917
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.3867928434
Short name T342
Test name
Test status
Simulation time 332108669931 ps
CPU time 402.58 seconds
Started Jun 05 05:26:43 PM PDT 24
Finished Jun 05 05:33:26 PM PDT 24
Peak memory 201804 kb
Host smart-58200d6e-47dc-4ec4-b458-efee5932d7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867928434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.3867928434
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.4074068726
Short name T728
Test name
Test status
Simulation time 493544789085 ps
CPU time 613.28 seconds
Started Jun 05 05:26:45 PM PDT 24
Finished Jun 05 05:36:59 PM PDT 24
Peak memory 201800 kb
Host smart-0625473e-b4a3-4b90-bd49-1112384841d3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074068726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.4074068726
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.976274173
Short name T201
Test name
Test status
Simulation time 325962432468 ps
CPU time 201.72 seconds
Started Jun 05 05:26:42 PM PDT 24
Finished Jun 05 05:30:04 PM PDT 24
Peak memory 201860 kb
Host smart-29754e4c-11c2-43b0-8991-5def4d9021d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976274173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.976274173
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.1001135344
Short name T369
Test name
Test status
Simulation time 165947727049 ps
CPU time 94.32 seconds
Started Jun 05 05:26:37 PM PDT 24
Finished Jun 05 05:28:12 PM PDT 24
Peak memory 201776 kb
Host smart-b1ef0389-2e6a-4a1a-b5d7-a9924969cc4c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001135344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.1001135344
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.3309249254
Short name T708
Test name
Test status
Simulation time 355546998256 ps
CPU time 416.85 seconds
Started Jun 05 05:26:42 PM PDT 24
Finished Jun 05 05:33:39 PM PDT 24
Peak memory 201820 kb
Host smart-73ae0eca-12ed-4d86-961f-f7dba57f713b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309249254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.3309249254
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.1732623783
Short name T736
Test name
Test status
Simulation time 393916916038 ps
CPU time 951.1 seconds
Started Jun 05 05:26:42 PM PDT 24
Finished Jun 05 05:42:33 PM PDT 24
Peak memory 201880 kb
Host smart-823792d6-f758-41be-9dbf-6a5aa46bc268
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732623783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.1732623783
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.1245016751
Short name T479
Test name
Test status
Simulation time 93706030509 ps
CPU time 333.61 seconds
Started Jun 05 05:26:43 PM PDT 24
Finished Jun 05 05:32:17 PM PDT 24
Peak memory 202108 kb
Host smart-8e8467c5-09b1-4730-8b1c-c3555a16bbda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245016751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.1245016751
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.773162543
Short name T560
Test name
Test status
Simulation time 34371687080 ps
CPU time 54.81 seconds
Started Jun 05 05:26:42 PM PDT 24
Finished Jun 05 05:27:37 PM PDT 24
Peak memory 201528 kb
Host smart-6fff8483-fb6a-44e3-ac57-bd0f09fa97e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773162543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.773162543
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.8236034
Short name T202
Test name
Test status
Simulation time 4983281059 ps
CPU time 12.07 seconds
Started Jun 05 05:26:42 PM PDT 24
Finished Jun 05 05:26:54 PM PDT 24
Peak memory 201608 kb
Host smart-dbab4236-f65b-4486-8731-523e6ab482e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8236034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.8236034
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.1585959131
Short name T457
Test name
Test status
Simulation time 5797425196 ps
CPU time 5 seconds
Started Jun 05 05:26:44 PM PDT 24
Finished Jun 05 05:26:49 PM PDT 24
Peak memory 201640 kb
Host smart-6b9db4fb-7861-4e54-99e5-e1bc464131ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585959131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.1585959131
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.1050593911
Short name T30
Test name
Test status
Simulation time 487965682510 ps
CPU time 578.68 seconds
Started Jun 05 05:26:51 PM PDT 24
Finished Jun 05 05:36:30 PM PDT 24
Peak memory 201808 kb
Host smart-c7a047e7-02db-4332-8b08-0a106d2ce8ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050593911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.1050593911
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.318286426
Short name T23
Test name
Test status
Simulation time 46547014505 ps
CPU time 104.7 seconds
Started Jun 05 05:26:50 PM PDT 24
Finished Jun 05 05:28:35 PM PDT 24
Peak memory 210188 kb
Host smart-08acf591-bdcb-415f-9de5-93e049780fba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318286426 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.318286426
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.1584615527
Short name T483
Test name
Test status
Simulation time 412121861 ps
CPU time 1.64 seconds
Started Jun 05 05:26:51 PM PDT 24
Finished Jun 05 05:26:53 PM PDT 24
Peak memory 201480 kb
Host smart-4daa79db-027e-47d4-ab6e-873df972ab8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584615527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.1584615527
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.1553590975
Short name T320
Test name
Test status
Simulation time 179086072329 ps
CPU time 245.35 seconds
Started Jun 05 05:26:50 PM PDT 24
Finished Jun 05 05:30:56 PM PDT 24
Peak memory 201820 kb
Host smart-f3fab939-8fc2-4407-bfec-98352ebfc40b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553590975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.1553590975
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.409339411
Short name T304
Test name
Test status
Simulation time 522367119797 ps
CPU time 1083.59 seconds
Started Jun 05 05:26:50 PM PDT 24
Finished Jun 05 05:44:55 PM PDT 24
Peak memory 201800 kb
Host smart-113cf20a-0d55-41aa-9c0e-000e65f0f191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409339411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.409339411
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.145326014
Short name T552
Test name
Test status
Simulation time 163049272586 ps
CPU time 74.71 seconds
Started Jun 05 05:26:51 PM PDT 24
Finished Jun 05 05:28:06 PM PDT 24
Peak memory 201880 kb
Host smart-94ca2f51-89ed-4da2-bc5a-7f0926829231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145326014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.145326014
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.1938675472
Short name T506
Test name
Test status
Simulation time 489424088015 ps
CPU time 285.32 seconds
Started Jun 05 05:26:50 PM PDT 24
Finished Jun 05 05:31:35 PM PDT 24
Peak memory 201812 kb
Host smart-7bd6af14-8afa-438e-a08f-9a17e8c27708
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938675472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.1938675472
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.2127815401
Short name T469
Test name
Test status
Simulation time 337411480316 ps
CPU time 218.22 seconds
Started Jun 05 05:26:49 PM PDT 24
Finished Jun 05 05:30:28 PM PDT 24
Peak memory 201792 kb
Host smart-a5d5f9a6-91a2-4c90-918d-b32c14b7ec66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127815401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.2127815401
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.1807140222
Short name T635
Test name
Test status
Simulation time 494989617720 ps
CPU time 559.48 seconds
Started Jun 05 05:26:52 PM PDT 24
Finished Jun 05 05:36:12 PM PDT 24
Peak memory 201784 kb
Host smart-bc049692-a5e8-40e7-a347-95fb845d0cfb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807140222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.1807140222
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.2646743340
Short name T786
Test name
Test status
Simulation time 677966106449 ps
CPU time 757.73 seconds
Started Jun 05 05:26:53 PM PDT 24
Finished Jun 05 05:39:31 PM PDT 24
Peak memory 201892 kb
Host smart-51a6cdfe-a772-4caf-b7b8-2e3f67816b7b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646743340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.2646743340
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.2666854542
Short name T386
Test name
Test status
Simulation time 197521004870 ps
CPU time 78.89 seconds
Started Jun 05 05:26:50 PM PDT 24
Finished Jun 05 05:28:09 PM PDT 24
Peak memory 201804 kb
Host smart-2b87dff9-35b1-4b9f-b462-acbe39bf7aff
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666854542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.2666854542
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.2434938300
Short name T377
Test name
Test status
Simulation time 46867475547 ps
CPU time 98.49 seconds
Started Jun 05 05:26:50 PM PDT 24
Finished Jun 05 05:28:29 PM PDT 24
Peak memory 201604 kb
Host smart-c58c9447-a99f-411a-be01-12e94337cddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434938300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.2434938300
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.1121944609
Short name T580
Test name
Test status
Simulation time 4954953586 ps
CPU time 3.8 seconds
Started Jun 05 05:26:50 PM PDT 24
Finished Jun 05 05:26:54 PM PDT 24
Peak memory 201628 kb
Host smart-044a5ecc-dd16-4677-ba65-989203d99c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121944609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.1121944609
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.1109853173
Short name T372
Test name
Test status
Simulation time 6025489954 ps
CPU time 4.09 seconds
Started Jun 05 05:26:53 PM PDT 24
Finished Jun 05 05:26:58 PM PDT 24
Peak memory 201628 kb
Host smart-ad2d9e8f-1f95-4a69-b04c-511046e48961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109853173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.1109853173
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.3085990637
Short name T49
Test name
Test status
Simulation time 322810708078 ps
CPU time 1827.48 seconds
Started Jun 05 05:26:52 PM PDT 24
Finished Jun 05 05:57:21 PM PDT 24
Peak memory 202096 kb
Host smart-bd4dc1dd-0c9f-44f0-8d27-b1bb7cddd747
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085990637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.3085990637
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.3521644693
Short name T711
Test name
Test status
Simulation time 122654136410 ps
CPU time 147.75 seconds
Started Jun 05 05:26:51 PM PDT 24
Finished Jun 05 05:29:19 PM PDT 24
Peak memory 210600 kb
Host smart-8ae4a753-7bf6-45a3-a242-14aeed4da347
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521644693 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.3521644693
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.3691948659
Short name T494
Test name
Test status
Simulation time 395349614 ps
CPU time 1.53 seconds
Started Jun 05 05:25:35 PM PDT 24
Finished Jun 05 05:25:37 PM PDT 24
Peak memory 201488 kb
Host smart-004e0972-6ce2-44d9-ac12-b8d1d6db52d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691948659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.3691948659
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.259433153
Short name T276
Test name
Test status
Simulation time 540733279455 ps
CPU time 192.78 seconds
Started Jun 05 05:25:38 PM PDT 24
Finished Jun 05 05:28:52 PM PDT 24
Peak memory 201808 kb
Host smart-21d7c128-ae40-4cc6-9136-66eaf67f870a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259433153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gatin
g.259433153
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.3998287127
Short name T267
Test name
Test status
Simulation time 493731181848 ps
CPU time 127.83 seconds
Started Jun 05 05:25:36 PM PDT 24
Finished Jun 05 05:27:44 PM PDT 24
Peak memory 201804 kb
Host smart-a67b5982-6288-4bb4-992d-18914c910cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998287127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.3998287127
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.1734676912
Short name T207
Test name
Test status
Simulation time 325528746238 ps
CPU time 202.7 seconds
Started Jun 05 05:25:43 PM PDT 24
Finished Jun 05 05:29:06 PM PDT 24
Peak memory 201880 kb
Host smart-b97f9f2c-268a-43bf-ae35-af86c1ee4e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734676912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.1734676912
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.799903282
Short name T722
Test name
Test status
Simulation time 488805577891 ps
CPU time 289.57 seconds
Started Jun 05 05:25:35 PM PDT 24
Finished Jun 05 05:30:25 PM PDT 24
Peak memory 201748 kb
Host smart-574c7509-4f57-46e5-ac24-a1ac8a208ecd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=799903282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt
_fixed.799903282
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.2949757572
Short name T648
Test name
Test status
Simulation time 493182148363 ps
CPU time 1168.2 seconds
Started Jun 05 05:25:38 PM PDT 24
Finished Jun 05 05:45:06 PM PDT 24
Peak memory 201808 kb
Host smart-7c8b1bcd-6208-43ed-8cc4-880bd4a9fb7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949757572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.2949757572
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.1408877758
Short name T376
Test name
Test status
Simulation time 492870337407 ps
CPU time 1155.54 seconds
Started Jun 05 05:25:35 PM PDT 24
Finished Jun 05 05:44:51 PM PDT 24
Peak memory 201804 kb
Host smart-cb1a135a-26c5-439f-a1ea-b48051e37ef3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408877758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.1408877758
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.2086640540
Short name T608
Test name
Test status
Simulation time 188656531613 ps
CPU time 108.63 seconds
Started Jun 05 05:25:44 PM PDT 24
Finished Jun 05 05:27:33 PM PDT 24
Peak memory 201816 kb
Host smart-3c4d2da6-b54a-43f5-a1de-456a92117307
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086640540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.2086640540
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.3114796078
Short name T50
Test name
Test status
Simulation time 112493390983 ps
CPU time 384.14 seconds
Started Jun 05 05:25:40 PM PDT 24
Finished Jun 05 05:32:05 PM PDT 24
Peak memory 202096 kb
Host smart-c7bec330-1707-4add-af0e-1a5a809eee25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114796078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.3114796078
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.452960266
Short name T751
Test name
Test status
Simulation time 35201681250 ps
CPU time 19.84 seconds
Started Jun 05 05:25:37 PM PDT 24
Finished Jun 05 05:25:57 PM PDT 24
Peak memory 201588 kb
Host smart-dca75436-6df7-4723-a317-b3ec302f03dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452960266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.452960266
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.13315461
Short name T56
Test name
Test status
Simulation time 4169927775 ps
CPU time 5.22 seconds
Started Jun 05 05:25:36 PM PDT 24
Finished Jun 05 05:25:42 PM PDT 24
Peak memory 201620 kb
Host smart-2698a3f8-b136-45f9-9ce9-a326d972918a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13315461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.13315461
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.3139867461
Short name T69
Test name
Test status
Simulation time 8334377784 ps
CPU time 17.76 seconds
Started Jun 05 05:25:36 PM PDT 24
Finished Jun 05 05:25:54 PM PDT 24
Peak memory 217376 kb
Host smart-fc1ab2fd-96ef-4397-95fc-27c83df57820
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139867461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.3139867461
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.2352524068
Short name T793
Test name
Test status
Simulation time 6085860848 ps
CPU time 1.58 seconds
Started Jun 05 05:25:39 PM PDT 24
Finished Jun 05 05:25:42 PM PDT 24
Peak memory 201648 kb
Host smart-dc2bfce6-747b-4197-9a53-1752a975ba46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352524068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.2352524068
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.2654905858
Short name T237
Test name
Test status
Simulation time 234841524373 ps
CPU time 461.64 seconds
Started Jun 05 05:25:35 PM PDT 24
Finished Jun 05 05:33:17 PM PDT 24
Peak memory 201860 kb
Host smart-f8705a49-5d5e-413d-830f-5c6003f11705
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654905858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
2654905858
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.1089798091
Short name T590
Test name
Test status
Simulation time 525635858 ps
CPU time 1.82 seconds
Started Jun 05 05:26:57 PM PDT 24
Finished Jun 05 05:26:59 PM PDT 24
Peak memory 201508 kb
Host smart-354e17f5-3e1e-49ad-8cf8-c9cd1c561d26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089798091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.1089798091
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.3084758067
Short name T61
Test name
Test status
Simulation time 360962048232 ps
CPU time 192.87 seconds
Started Jun 05 05:27:01 PM PDT 24
Finished Jun 05 05:30:15 PM PDT 24
Peak memory 201816 kb
Host smart-e7820795-041d-4949-aa4a-4344127c8b65
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084758067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.3084758067
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.2863281387
Short name T178
Test name
Test status
Simulation time 162861602538 ps
CPU time 65.28 seconds
Started Jun 05 05:26:59 PM PDT 24
Finished Jun 05 05:28:05 PM PDT 24
Peak memory 201804 kb
Host smart-438876f3-d5b5-447d-8d66-73756f1de9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863281387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.2863281387
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.1503298308
Short name T637
Test name
Test status
Simulation time 324579894716 ps
CPU time 789.14 seconds
Started Jun 05 05:26:59 PM PDT 24
Finished Jun 05 05:40:09 PM PDT 24
Peak memory 201812 kb
Host smart-9d7840b3-46ce-44be-b0d5-96ccd09f64a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503298308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.1503298308
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.3329161046
Short name T488
Test name
Test status
Simulation time 167108856037 ps
CPU time 364.64 seconds
Started Jun 05 05:26:59 PM PDT 24
Finished Jun 05 05:33:04 PM PDT 24
Peak memory 201812 kb
Host smart-4563ee7d-9393-487f-a6ec-3b6c16ff9fde
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329161046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.3329161046
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.836807430
Short name T768
Test name
Test status
Simulation time 502475471905 ps
CPU time 259.31 seconds
Started Jun 05 05:26:58 PM PDT 24
Finished Jun 05 05:31:18 PM PDT 24
Peak memory 201772 kb
Host smart-91e19bb2-876b-4ed7-bde4-4784c3200f74
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=836807430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fixe
d.836807430
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.3201884491
Short name T249
Test name
Test status
Simulation time 514770490895 ps
CPU time 357.17 seconds
Started Jun 05 05:27:00 PM PDT 24
Finished Jun 05 05:32:58 PM PDT 24
Peak memory 201864 kb
Host smart-6b191b7b-d228-4dbb-92db-8deb30c6e7ef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201884491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.3201884491
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.3903424419
Short name T520
Test name
Test status
Simulation time 396819185736 ps
CPU time 245.84 seconds
Started Jun 05 05:27:02 PM PDT 24
Finished Jun 05 05:31:08 PM PDT 24
Peak memory 201776 kb
Host smart-fee3f0bb-28e4-47b4-893c-3324245bfce3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903424419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.3903424419
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.1604555819
Short name T27
Test name
Test status
Simulation time 89290152343 ps
CPU time 272.41 seconds
Started Jun 05 05:26:59 PM PDT 24
Finished Jun 05 05:31:32 PM PDT 24
Peak memory 202148 kb
Host smart-50849bfb-cc3a-4af1-b435-44d07018e74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604555819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.1604555819
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.4107076471
Short name T700
Test name
Test status
Simulation time 41035572260 ps
CPU time 25.12 seconds
Started Jun 05 05:26:57 PM PDT 24
Finished Jun 05 05:27:23 PM PDT 24
Peak memory 201648 kb
Host smart-96a86a73-d721-42d5-bbbf-e3ae2fff80f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107076471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.4107076471
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.601604750
Short name T478
Test name
Test status
Simulation time 3303003135 ps
CPU time 8.83 seconds
Started Jun 05 05:26:58 PM PDT 24
Finished Jun 05 05:27:07 PM PDT 24
Peak memory 201576 kb
Host smart-5e71a13e-6718-4859-b97c-2b6912b6cde0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601604750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.601604750
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.3468528325
Short name T646
Test name
Test status
Simulation time 5795324292 ps
CPU time 13.35 seconds
Started Jun 05 05:26:59 PM PDT 24
Finished Jun 05 05:27:12 PM PDT 24
Peak memory 201628 kb
Host smart-28440a0e-1c66-44d2-8188-8f08a33e064d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468528325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.3468528325
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.4135999538
Short name T767
Test name
Test status
Simulation time 713869439162 ps
CPU time 117.59 seconds
Started Jun 05 05:27:02 PM PDT 24
Finished Jun 05 05:29:00 PM PDT 24
Peak memory 201876 kb
Host smart-dc66e90e-df84-4fc9-8981-5191224b741b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135999538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.4135999538
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.93198653
Short name T243
Test name
Test status
Simulation time 60916717624 ps
CPU time 20.54 seconds
Started Jun 05 05:26:59 PM PDT 24
Finished Jun 05 05:27:20 PM PDT 24
Peak memory 201888 kb
Host smart-554a7599-8cfa-421c-9380-416ab5bc872c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93198653 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.93198653
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.1017108439
Short name T396
Test name
Test status
Simulation time 331593447 ps
CPU time 0.72 seconds
Started Jun 05 05:27:12 PM PDT 24
Finished Jun 05 05:27:13 PM PDT 24
Peak memory 201504 kb
Host smart-76df022a-669c-4c9e-b05d-0b4b3eb26c25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017108439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.1017108439
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.2118586376
Short name T290
Test name
Test status
Simulation time 326276143117 ps
CPU time 764.51 seconds
Started Jun 05 05:27:03 PM PDT 24
Finished Jun 05 05:39:48 PM PDT 24
Peak memory 201748 kb
Host smart-1dea7cd6-632f-4579-bc7f-ddaa63c2d544
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118586376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.2118586376
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.2792572328
Short name T614
Test name
Test status
Simulation time 206897268249 ps
CPU time 236.5 seconds
Started Jun 05 05:27:06 PM PDT 24
Finished Jun 05 05:31:03 PM PDT 24
Peak memory 201884 kb
Host smart-dfa37a40-b125-45ac-90b6-bd1b237fac93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792572328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.2792572328
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.272127518
Short name T236
Test name
Test status
Simulation time 327554471682 ps
CPU time 724.61 seconds
Started Jun 05 05:27:05 PM PDT 24
Finished Jun 05 05:39:10 PM PDT 24
Peak memory 201808 kb
Host smart-b41df2b9-c2b0-4032-bc3a-9abbde56033b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272127518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.272127518
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.4096502259
Short name T407
Test name
Test status
Simulation time 321858235449 ps
CPU time 696.32 seconds
Started Jun 05 05:27:04 PM PDT 24
Finished Jun 05 05:38:41 PM PDT 24
Peak memory 201812 kb
Host smart-9bb5a8c8-2bf8-43a6-8115-a561df794408
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096502259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.4096502259
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.3127811344
Short name T92
Test name
Test status
Simulation time 492936761752 ps
CPU time 1174.91 seconds
Started Jun 05 05:27:04 PM PDT 24
Finished Jun 05 05:46:39 PM PDT 24
Peak memory 201836 kb
Host smart-779eda9f-fa64-4fd1-a316-5747ea245616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127811344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.3127811344
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.2982468819
Short name T709
Test name
Test status
Simulation time 327265019722 ps
CPU time 766.97 seconds
Started Jun 05 05:27:03 PM PDT 24
Finished Jun 05 05:39:51 PM PDT 24
Peak memory 201796 kb
Host smart-b4cb8e44-cb31-4efc-957a-5379f2343638
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982468819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.2982468819
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.1346635561
Short name T170
Test name
Test status
Simulation time 167099926121 ps
CPU time 371.74 seconds
Started Jun 05 05:27:02 PM PDT 24
Finished Jun 05 05:33:15 PM PDT 24
Peak memory 201832 kb
Host smart-c7ceb848-7e32-4f8f-a52f-ef9656283cc1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346635561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.1346635561
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.429518229
Short name T431
Test name
Test status
Simulation time 196518038640 ps
CPU time 125.01 seconds
Started Jun 05 05:27:03 PM PDT 24
Finished Jun 05 05:29:08 PM PDT 24
Peak memory 201808 kb
Host smart-e5e0d759-4dfa-403e-be83-0cb9500d7ab9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429518229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
adc_ctrl_filters_wakeup_fixed.429518229
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.961105993
Short name T442
Test name
Test status
Simulation time 123684230070 ps
CPU time 698.23 seconds
Started Jun 05 05:27:11 PM PDT 24
Finished Jun 05 05:38:50 PM PDT 24
Peak memory 202080 kb
Host smart-390df737-0e82-4861-8661-336c9756e814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961105993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.961105993
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.4128435538
Short name T673
Test name
Test status
Simulation time 39715613848 ps
CPU time 88.29 seconds
Started Jun 05 05:27:12 PM PDT 24
Finished Jun 05 05:28:41 PM PDT 24
Peak memory 201628 kb
Host smart-0365d70d-f326-4868-b2ce-1287e2c672bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128435538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.4128435538
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.235387156
Short name T752
Test name
Test status
Simulation time 4336236857 ps
CPU time 3.44 seconds
Started Jun 05 05:27:04 PM PDT 24
Finished Jun 05 05:27:08 PM PDT 24
Peak memory 201616 kb
Host smart-01e0d56f-3d86-47f9-b41e-947e1d762a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235387156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.235387156
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.3582552906
Short name T607
Test name
Test status
Simulation time 6183046393 ps
CPU time 15.97 seconds
Started Jun 05 05:27:02 PM PDT 24
Finished Jun 05 05:27:18 PM PDT 24
Peak memory 201644 kb
Host smart-79b2181f-e6d1-4513-a9e3-bfba4ee188ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582552906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.3582552906
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.2199873784
Short name T777
Test name
Test status
Simulation time 329770273391 ps
CPU time 651 seconds
Started Jun 05 05:27:12 PM PDT 24
Finished Jun 05 05:38:04 PM PDT 24
Peak memory 201796 kb
Host smart-f297fb09-eb34-45e8-a851-445faba2024b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199873784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.2199873784
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.499896730
Short name T497
Test name
Test status
Simulation time 615603892 ps
CPU time 0.69 seconds
Started Jun 05 05:27:27 PM PDT 24
Finished Jun 05 05:27:28 PM PDT 24
Peak memory 201496 kb
Host smart-2dfed59b-c921-41a3-92a3-4b882ae705e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499896730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.499896730
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.1430666615
Short name T344
Test name
Test status
Simulation time 518608390171 ps
CPU time 823.66 seconds
Started Jun 05 05:27:19 PM PDT 24
Finished Jun 05 05:41:04 PM PDT 24
Peak memory 201772 kb
Host smart-bf0abd53-4b63-449f-8033-cf36469dab5e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430666615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.1430666615
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.190820656
Short name T338
Test name
Test status
Simulation time 382359607876 ps
CPU time 676.63 seconds
Started Jun 05 05:27:18 PM PDT 24
Finished Jun 05 05:38:36 PM PDT 24
Peak memory 201788 kb
Host smart-7421277a-19a7-4a91-8cb1-00e91a4528a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190820656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.190820656
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.950224431
Short name T233
Test name
Test status
Simulation time 325629957707 ps
CPU time 189.95 seconds
Started Jun 05 05:27:13 PM PDT 24
Finished Jun 05 05:30:23 PM PDT 24
Peak memory 201892 kb
Host smart-273658cd-d8cd-4f60-bd4a-4960057d700f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950224431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.950224431
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.3519247842
Short name T471
Test name
Test status
Simulation time 479202573851 ps
CPU time 1137 seconds
Started Jun 05 05:27:11 PM PDT 24
Finished Jun 05 05:46:08 PM PDT 24
Peak memory 201860 kb
Host smart-6c5f041f-739c-4ba7-992e-05b12d90f880
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519247842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.3519247842
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.2679477249
Short name T100
Test name
Test status
Simulation time 333144969004 ps
CPU time 274.85 seconds
Started Jun 05 05:27:12 PM PDT 24
Finished Jun 05 05:31:47 PM PDT 24
Peak memory 201784 kb
Host smart-42c5925c-649a-4f70-b05f-bd02fb309653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679477249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.2679477249
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.632280040
Short name T502
Test name
Test status
Simulation time 159509546046 ps
CPU time 382.76 seconds
Started Jun 05 05:27:13 PM PDT 24
Finished Jun 05 05:33:36 PM PDT 24
Peak memory 201812 kb
Host smart-ac33ad46-0e43-4980-8bbd-d4aef8d27339
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=632280040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fixe
d.632280040
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.3170505027
Short name T489
Test name
Test status
Simulation time 402521395724 ps
CPU time 153.51 seconds
Started Jun 05 05:27:10 PM PDT 24
Finished Jun 05 05:29:44 PM PDT 24
Peak memory 201820 kb
Host smart-8a9e8b76-6200-4ec6-b16c-5495b3465699
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170505027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.3170505027
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.535156422
Short name T437
Test name
Test status
Simulation time 72887089986 ps
CPU time 374.62 seconds
Started Jun 05 05:27:27 PM PDT 24
Finished Jun 05 05:33:43 PM PDT 24
Peak memory 202168 kb
Host smart-44e0aa72-e233-4b30-9bb0-7db016b811df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535156422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.535156422
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.3796436564
Short name T573
Test name
Test status
Simulation time 26252858255 ps
CPU time 8.45 seconds
Started Jun 05 05:27:19 PM PDT 24
Finished Jun 05 05:27:28 PM PDT 24
Peak memory 201600 kb
Host smart-43c4fe3f-0273-4148-9545-53b75c0b3a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796436564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.3796436564
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.3027896361
Short name T740
Test name
Test status
Simulation time 5482489569 ps
CPU time 2.19 seconds
Started Jun 05 05:27:20 PM PDT 24
Finished Jun 05 05:27:23 PM PDT 24
Peak memory 201620 kb
Host smart-bd258377-3f01-4cfe-8661-b23e91f914b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027896361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.3027896361
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.3163644008
Short name T649
Test name
Test status
Simulation time 5992583967 ps
CPU time 6.1 seconds
Started Jun 05 05:27:11 PM PDT 24
Finished Jun 05 05:27:17 PM PDT 24
Peak memory 201620 kb
Host smart-acf998be-2f0f-4557-84a8-eb0aecd50dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163644008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.3163644008
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.1386377637
Short name T774
Test name
Test status
Simulation time 163617816002 ps
CPU time 333.16 seconds
Started Jun 05 05:27:24 PM PDT 24
Finished Jun 05 05:32:57 PM PDT 24
Peak memory 210324 kb
Host smart-9d4341a9-022c-4930-a660-4d92c7b72364
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386377637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.1386377637
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.4006263698
Short name T399
Test name
Test status
Simulation time 296824282 ps
CPU time 0.85 seconds
Started Jun 05 05:27:33 PM PDT 24
Finished Jun 05 05:27:35 PM PDT 24
Peak memory 201500 kb
Host smart-8108078a-02bd-4013-ad33-c735695b79c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006263698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.4006263698
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.3109902815
Short name T440
Test name
Test status
Simulation time 324187878581 ps
CPU time 588.86 seconds
Started Jun 05 05:27:34 PM PDT 24
Finished Jun 05 05:37:23 PM PDT 24
Peak memory 201816 kb
Host smart-a11503ef-3109-4362-83aa-ee604f74c10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109902815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.3109902815
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.2313759775
Short name T572
Test name
Test status
Simulation time 162431110467 ps
CPU time 374.32 seconds
Started Jun 05 05:27:27 PM PDT 24
Finished Jun 05 05:33:41 PM PDT 24
Peak memory 201804 kb
Host smart-aa5f79fd-e9b5-40c3-b692-696cf159e4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313759775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.2313759775
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.2616550667
Short name T224
Test name
Test status
Simulation time 329523864194 ps
CPU time 177.68 seconds
Started Jun 05 05:27:27 PM PDT 24
Finished Jun 05 05:30:25 PM PDT 24
Peak memory 201804 kb
Host smart-69754f4a-4961-4d4f-951a-34ab3da2ca6e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616550667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.2616550667
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.2315682408
Short name T154
Test name
Test status
Simulation time 489369942790 ps
CPU time 570.57 seconds
Started Jun 05 05:27:26 PM PDT 24
Finished Jun 05 05:36:57 PM PDT 24
Peak memory 201864 kb
Host smart-d87349af-2040-4a51-b4d6-bea969d2a1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315682408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.2315682408
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.943458412
Short name T518
Test name
Test status
Simulation time 484491939838 ps
CPU time 1056.6 seconds
Started Jun 05 05:27:28 PM PDT 24
Finished Jun 05 05:45:05 PM PDT 24
Peak memory 201812 kb
Host smart-60d4ab6a-13ef-477e-bd28-771ad2558de2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=943458412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fixe
d.943458412
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.1781681311
Short name T198
Test name
Test status
Simulation time 535932958916 ps
CPU time 122.82 seconds
Started Jun 05 05:27:27 PM PDT 24
Finished Jun 05 05:29:30 PM PDT 24
Peak memory 201816 kb
Host smart-0a80e4ad-eccf-48ad-a095-ca7f196880e9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781681311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.1781681311
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.3944606497
Short name T91
Test name
Test status
Simulation time 211576635890 ps
CPU time 245.72 seconds
Started Jun 05 05:27:32 PM PDT 24
Finished Jun 05 05:31:38 PM PDT 24
Peak memory 201816 kb
Host smart-76dada0e-63eb-48fc-ae4a-cc4802637759
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944606497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.3944606497
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.2106038742
Short name T794
Test name
Test status
Simulation time 45020317007 ps
CPU time 104.78 seconds
Started Jun 05 05:27:33 PM PDT 24
Finished Jun 05 05:29:18 PM PDT 24
Peak memory 201628 kb
Host smart-3c859566-9480-411e-a664-30b31688815c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106038742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.2106038742
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.3324465103
Short name T555
Test name
Test status
Simulation time 4374719715 ps
CPU time 3.13 seconds
Started Jun 05 05:27:33 PM PDT 24
Finished Jun 05 05:27:37 PM PDT 24
Peak memory 201580 kb
Host smart-f78c7946-da52-4bad-8b17-91e806a6b15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324465103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.3324465103
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.580125077
Short name T743
Test name
Test status
Simulation time 5875819726 ps
CPU time 5.95 seconds
Started Jun 05 05:27:27 PM PDT 24
Finished Jun 05 05:27:34 PM PDT 24
Peak memory 201640 kb
Host smart-5e796edd-a95e-47b0-a9df-4c554ef2630d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580125077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.580125077
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.3623953411
Short name T19
Test name
Test status
Simulation time 23016129969 ps
CPU time 52.62 seconds
Started Jun 05 05:27:32 PM PDT 24
Finished Jun 05 05:28:25 PM PDT 24
Peak memory 210128 kb
Host smart-c1971212-e6fc-497f-94b3-aa445dbb8c64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623953411 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.3623953411
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.2484985728
Short name T629
Test name
Test status
Simulation time 382742944 ps
CPU time 1.5 seconds
Started Jun 05 05:27:46 PM PDT 24
Finished Jun 05 05:27:48 PM PDT 24
Peak memory 201500 kb
Host smart-b9d1edf1-18b5-48d7-8a2d-1a28708dca7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484985728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.2484985728
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.2546002100
Short name T567
Test name
Test status
Simulation time 162325552288 ps
CPU time 193.13 seconds
Started Jun 05 05:27:39 PM PDT 24
Finished Jun 05 05:30:52 PM PDT 24
Peak memory 201820 kb
Host smart-612d375d-b053-41d2-9270-4fbcf0431629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546002100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.2546002100
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.2500634666
Short name T459
Test name
Test status
Simulation time 321209835258 ps
CPU time 198.72 seconds
Started Jun 05 05:27:40 PM PDT 24
Finished Jun 05 05:31:00 PM PDT 24
Peak memory 201804 kb
Host smart-0c034563-dc56-43d2-8b59-a5b8049fc81e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500634666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.2500634666
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.2396309122
Short name T647
Test name
Test status
Simulation time 333828903571 ps
CPU time 705.2 seconds
Started Jun 05 05:27:33 PM PDT 24
Finished Jun 05 05:39:19 PM PDT 24
Peak memory 201788 kb
Host smart-b4412df2-c61d-4b31-a30a-a1fd42829a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396309122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.2396309122
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.2139801327
Short name T610
Test name
Test status
Simulation time 166799677442 ps
CPU time 372.9 seconds
Started Jun 05 05:27:42 PM PDT 24
Finished Jun 05 05:33:55 PM PDT 24
Peak memory 201764 kb
Host smart-177699ad-747d-491a-9642-fc6edc073041
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139801327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.2139801327
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.2014525994
Short name T225
Test name
Test status
Simulation time 355893103472 ps
CPU time 221.85 seconds
Started Jun 05 05:27:41 PM PDT 24
Finished Jun 05 05:31:23 PM PDT 24
Peak memory 201820 kb
Host smart-51e53537-60de-4a8a-a603-1f8299b7f2e7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014525994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.2014525994
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.602643553
Short name T511
Test name
Test status
Simulation time 211220010146 ps
CPU time 515.7 seconds
Started Jun 05 05:27:41 PM PDT 24
Finished Jun 05 05:36:17 PM PDT 24
Peak memory 201944 kb
Host smart-15deb95c-7c39-4e2d-a319-0bfff24f828e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602643553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
adc_ctrl_filters_wakeup_fixed.602643553
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.821239886
Short name T394
Test name
Test status
Simulation time 81645508428 ps
CPU time 347.18 seconds
Started Jun 05 05:27:46 PM PDT 24
Finished Jun 05 05:33:34 PM PDT 24
Peak memory 202112 kb
Host smart-637e880a-4725-40db-bb1c-e7da4374c6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821239886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.821239886
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.1208643730
Short name T616
Test name
Test status
Simulation time 33751750671 ps
CPU time 24.94 seconds
Started Jun 05 05:27:40 PM PDT 24
Finished Jun 05 05:28:05 PM PDT 24
Peak memory 201636 kb
Host smart-f5a5ae78-513f-4954-87de-ad38206de067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208643730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.1208643730
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.419268563
Short name T535
Test name
Test status
Simulation time 4029253128 ps
CPU time 5.84 seconds
Started Jun 05 05:27:42 PM PDT 24
Finished Jun 05 05:27:49 PM PDT 24
Peak memory 201624 kb
Host smart-fd0f3ce7-17f6-4d35-a704-fda011035728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419268563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.419268563
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.452715381
Short name T84
Test name
Test status
Simulation time 5649603966 ps
CPU time 6.18 seconds
Started Jun 05 05:27:33 PM PDT 24
Finished Jun 05 05:27:40 PM PDT 24
Peak memory 201596 kb
Host smart-bc298fc7-5792-4617-955c-f55ead2277fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452715381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.452715381
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.2832911212
Short name T353
Test name
Test status
Simulation time 23126577093 ps
CPU time 53.99 seconds
Started Jun 05 05:27:47 PM PDT 24
Finished Jun 05 05:28:41 PM PDT 24
Peak memory 210412 kb
Host smart-51bef1b8-5ea4-40ad-8f8c-a6e0a6fad400
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832911212 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.2832911212
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.3546802560
Short name T795
Test name
Test status
Simulation time 352505471 ps
CPU time 0.82 seconds
Started Jun 05 05:28:03 PM PDT 24
Finished Jun 05 05:28:04 PM PDT 24
Peak memory 201520 kb
Host smart-cc0cebfd-5aa6-4175-b86a-83698acd9c06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546802560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.3546802560
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.3843278291
Short name T195
Test name
Test status
Simulation time 360135178038 ps
CPU time 136.65 seconds
Started Jun 05 05:27:56 PM PDT 24
Finished Jun 05 05:30:13 PM PDT 24
Peak memory 201808 kb
Host smart-31ae9e78-bac0-4ca0-90e0-0937cfa1ea96
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843278291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.3843278291
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.764571637
Short name T323
Test name
Test status
Simulation time 162089226286 ps
CPU time 190.7 seconds
Started Jun 05 05:27:48 PM PDT 24
Finished Jun 05 05:30:59 PM PDT 24
Peak memory 201748 kb
Host smart-299e918e-299c-470b-a8f3-03325b0dcb9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764571637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.764571637
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.324195811
Short name T409
Test name
Test status
Simulation time 319946282738 ps
CPU time 191 seconds
Started Jun 05 05:27:48 PM PDT 24
Finished Jun 05 05:31:00 PM PDT 24
Peak memory 201756 kb
Host smart-c0e9ac67-ea1f-4d95-bb3c-86ad0415633c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=324195811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrup
t_fixed.324195811
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.2570252134
Short name T771
Test name
Test status
Simulation time 168909483705 ps
CPU time 103.76 seconds
Started Jun 05 05:27:48 PM PDT 24
Finished Jun 05 05:29:33 PM PDT 24
Peak memory 201868 kb
Host smart-30dde84e-eaf0-4cb4-acaa-bfec57e96027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570252134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.2570252134
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.1875869902
Short name T624
Test name
Test status
Simulation time 162732274572 ps
CPU time 395.96 seconds
Started Jun 05 05:27:47 PM PDT 24
Finished Jun 05 05:34:24 PM PDT 24
Peak memory 201768 kb
Host smart-9c0a4b33-834a-439d-bf93-9a53cfeea878
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875869902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.1875869902
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.2466803418
Short name T329
Test name
Test status
Simulation time 564072129203 ps
CPU time 678.6 seconds
Started Jun 05 05:27:54 PM PDT 24
Finished Jun 05 05:39:13 PM PDT 24
Peak memory 201824 kb
Host smart-7a324b71-bb4b-430f-a0bc-d8be7622c9f9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466803418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.2466803418
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.1745045613
Short name T713
Test name
Test status
Simulation time 387960331182 ps
CPU time 895.39 seconds
Started Jun 05 05:27:56 PM PDT 24
Finished Jun 05 05:42:52 PM PDT 24
Peak memory 201768 kb
Host smart-e5f54798-1b14-486a-9baa-ea58b41a51f8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745045613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.1745045613
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.1732185959
Short name T54
Test name
Test status
Simulation time 127580584227 ps
CPU time 654.96 seconds
Started Jun 05 05:28:02 PM PDT 24
Finished Jun 05 05:38:58 PM PDT 24
Peak memory 202108 kb
Host smart-732260a6-16f0-4768-80ff-c1d7b6d822a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732185959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.1732185959
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.1970121065
Short name T602
Test name
Test status
Simulation time 30626901181 ps
CPU time 34.08 seconds
Started Jun 05 05:27:56 PM PDT 24
Finished Jun 05 05:28:31 PM PDT 24
Peak memory 201628 kb
Host smart-a0719b1e-554c-40cd-b90d-e5bd5a88dfd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970121065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.1970121065
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.3713798514
Short name T401
Test name
Test status
Simulation time 3960534211 ps
CPU time 1.34 seconds
Started Jun 05 05:27:54 PM PDT 24
Finished Jun 05 05:27:56 PM PDT 24
Peak memory 201620 kb
Host smart-2c0a926b-43bf-479a-a51a-6a5e84f915ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713798514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.3713798514
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.3797661785
Short name T389
Test name
Test status
Simulation time 6110487642 ps
CPU time 1.61 seconds
Started Jun 05 05:27:45 PM PDT 24
Finished Jun 05 05:27:47 PM PDT 24
Peak memory 201628 kb
Host smart-29370c8f-774d-490d-b07b-501f6321a489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797661785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.3797661785
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.547886593
Short name T400
Test name
Test status
Simulation time 166963516383 ps
CPU time 384.17 seconds
Started Jun 05 05:28:00 PM PDT 24
Finished Jun 05 05:34:25 PM PDT 24
Peak memory 201808 kb
Host smart-4328d0e6-0703-4742-929a-f6eba8048843
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547886593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all.
547886593
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.2698972694
Short name T45
Test name
Test status
Simulation time 127170905324 ps
CPU time 143.21 seconds
Started Jun 05 05:28:00 PM PDT 24
Finished Jun 05 05:30:24 PM PDT 24
Peak memory 210088 kb
Host smart-4519f7c4-c8e5-433d-be35-5a33b0333206
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698972694 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.2698972694
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.3210454202
Short name T79
Test name
Test status
Simulation time 429369848 ps
CPU time 0.79 seconds
Started Jun 05 05:28:09 PM PDT 24
Finished Jun 05 05:28:10 PM PDT 24
Peak memory 201460 kb
Host smart-e5070a6b-8695-42df-b13b-0a2c13e9d32f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210454202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.3210454202
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.539443920
Short name T317
Test name
Test status
Simulation time 352688809094 ps
CPU time 721.4 seconds
Started Jun 05 05:28:03 PM PDT 24
Finished Jun 05 05:40:06 PM PDT 24
Peak memory 201820 kb
Host smart-ab349f31-a4ba-4654-b477-675c1b58a2d9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539443920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gati
ng.539443920
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.2092644117
Short name T485
Test name
Test status
Simulation time 326379082697 ps
CPU time 192.53 seconds
Started Jun 05 05:28:05 PM PDT 24
Finished Jun 05 05:31:18 PM PDT 24
Peak memory 201816 kb
Host smart-22a2c1c4-f936-438b-93d9-10a8f033238b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092644117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.2092644117
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.3888168116
Short name T220
Test name
Test status
Simulation time 490375817091 ps
CPU time 257.5 seconds
Started Jun 05 05:28:05 PM PDT 24
Finished Jun 05 05:32:23 PM PDT 24
Peak memory 201856 kb
Host smart-56ec9039-71d2-4170-ae7e-e7f106a22f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888168116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.3888168116
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.631725520
Short name T416
Test name
Test status
Simulation time 323110035795 ps
CPU time 372.61 seconds
Started Jun 05 05:28:02 PM PDT 24
Finished Jun 05 05:34:15 PM PDT 24
Peak memory 201784 kb
Host smart-70e7c237-bb89-4a5a-b945-b54b560c2bc8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=631725520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fixe
d.631725520
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.300559364
Short name T699
Test name
Test status
Simulation time 343881403819 ps
CPU time 206.44 seconds
Started Jun 05 05:28:00 PM PDT 24
Finished Jun 05 05:31:27 PM PDT 24
Peak memory 201824 kb
Host smart-e8cfd30d-eb51-49cb-a80e-b04414becd58
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300559364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_
wakeup.300559364
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.1283279034
Short name T445
Test name
Test status
Simulation time 202139723003 ps
CPU time 307.07 seconds
Started Jun 05 05:28:03 PM PDT 24
Finished Jun 05 05:33:11 PM PDT 24
Peak memory 201880 kb
Host smart-9eb8b1b5-a965-44ca-9e15-221cbb08b177
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283279034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.1283279034
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.1133689579
Short name T487
Test name
Test status
Simulation time 111456195301 ps
CPU time 428.15 seconds
Started Jun 05 05:28:09 PM PDT 24
Finished Jun 05 05:35:17 PM PDT 24
Peak memory 202124 kb
Host smart-1ec33192-958f-400c-9b68-394b184a77f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133689579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.1133689579
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.4251366526
Short name T574
Test name
Test status
Simulation time 34986448705 ps
CPU time 19.26 seconds
Started Jun 05 05:28:09 PM PDT 24
Finished Jun 05 05:28:28 PM PDT 24
Peak memory 201612 kb
Host smart-6467179f-e26b-4ed7-8e3e-773177ffaed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251366526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.4251366526
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.1005672084
Short name T622
Test name
Test status
Simulation time 5531813905 ps
CPU time 7.02 seconds
Started Jun 05 05:28:05 PM PDT 24
Finished Jun 05 05:28:13 PM PDT 24
Peak memory 201632 kb
Host smart-587ba18f-1883-47fd-85d7-01db641120bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005672084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.1005672084
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.2508349334
Short name T395
Test name
Test status
Simulation time 5832261435 ps
CPU time 13.85 seconds
Started Jun 05 05:28:03 PM PDT 24
Finished Jun 05 05:28:17 PM PDT 24
Peak memory 201640 kb
Host smart-62feb15e-09bd-4465-9db8-63ca698f71eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508349334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.2508349334
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.3929952902
Short name T25
Test name
Test status
Simulation time 83377260176 ps
CPU time 153.9 seconds
Started Jun 05 05:28:07 PM PDT 24
Finished Jun 05 05:30:41 PM PDT 24
Peak memory 210404 kb
Host smart-b56e127a-8468-4753-887b-9b0f6bdfae9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929952902 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.3929952902
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.514737673
Short name T393
Test name
Test status
Simulation time 509696566 ps
CPU time 0.9 seconds
Started Jun 05 05:28:17 PM PDT 24
Finished Jun 05 05:28:18 PM PDT 24
Peak memory 201500 kb
Host smart-3407a9a5-a343-4e92-950c-daf39774c2d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514737673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.514737673
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.54063030
Short name T223
Test name
Test status
Simulation time 326990348640 ps
CPU time 799.7 seconds
Started Jun 05 05:28:08 PM PDT 24
Finished Jun 05 05:41:28 PM PDT 24
Peak memory 201732 kb
Host smart-92655088-b98f-4f2a-8c7c-c4655275d58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54063030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.54063030
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.2033025454
Short name T530
Test name
Test status
Simulation time 483395612083 ps
CPU time 1043.39 seconds
Started Jun 05 05:28:09 PM PDT 24
Finished Jun 05 05:45:33 PM PDT 24
Peak memory 201756 kb
Host smart-ceb3ea36-1794-43a0-a8b5-3a91668887d6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033025454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.2033025454
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.634023304
Short name T212
Test name
Test status
Simulation time 500512333568 ps
CPU time 317.05 seconds
Started Jun 05 05:28:10 PM PDT 24
Finished Jun 05 05:33:28 PM PDT 24
Peak memory 201800 kb
Host smart-b87e0af5-5301-4aa5-8142-4d5b8fc26908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634023304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.634023304
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.316683185
Short name T641
Test name
Test status
Simulation time 331327447910 ps
CPU time 790.85 seconds
Started Jun 05 05:28:09 PM PDT 24
Finished Jun 05 05:41:21 PM PDT 24
Peak memory 201788 kb
Host smart-1dda647b-b158-4e46-b3a5-b6a6ce19f522
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=316683185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fixe
d.316683185
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.1487577853
Short name T540
Test name
Test status
Simulation time 167856127527 ps
CPU time 192.37 seconds
Started Jun 05 05:28:09 PM PDT 24
Finished Jun 05 05:31:22 PM PDT 24
Peak memory 201760 kb
Host smart-f44c4bc4-c1d9-46fc-9eb6-e35eeaa0f0e0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487577853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.1487577853
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.2365917771
Short name T747
Test name
Test status
Simulation time 594968811412 ps
CPU time 143.06 seconds
Started Jun 05 05:28:11 PM PDT 24
Finished Jun 05 05:30:34 PM PDT 24
Peak memory 201808 kb
Host smart-820ca7e7-a960-4384-97d1-ad1b12aa44c9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365917771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.2365917771
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.2447127261
Short name T529
Test name
Test status
Simulation time 68881414401 ps
CPU time 394.5 seconds
Started Jun 05 05:28:19 PM PDT 24
Finished Jun 05 05:34:54 PM PDT 24
Peak memory 202160 kb
Host smart-383320bb-2746-461b-8c0f-b8069b9525d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447127261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.2447127261
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.964008348
Short name T374
Test name
Test status
Simulation time 34308401246 ps
CPU time 80.46 seconds
Started Jun 05 05:28:18 PM PDT 24
Finished Jun 05 05:29:40 PM PDT 24
Peak memory 201616 kb
Host smart-efb33ce4-eef5-47e7-8d33-1394a8f561e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964008348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.964008348
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.1078410011
Short name T509
Test name
Test status
Simulation time 5079341949 ps
CPU time 13.58 seconds
Started Jun 05 05:28:17 PM PDT 24
Finished Jun 05 05:28:31 PM PDT 24
Peak memory 201632 kb
Host smart-5a72cf98-b855-4483-960f-7a265dc9f7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078410011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.1078410011
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.489453373
Short name T688
Test name
Test status
Simulation time 5962102938 ps
CPU time 2.24 seconds
Started Jun 05 05:28:09 PM PDT 24
Finished Jun 05 05:28:12 PM PDT 24
Peak memory 201628 kb
Host smart-ee7417a5-3788-4210-b35c-a083d8b04ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489453373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.489453373
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.654254559
Short name T363
Test name
Test status
Simulation time 132553858161 ps
CPU time 700.6 seconds
Started Jun 05 05:28:18 PM PDT 24
Finished Jun 05 05:39:59 PM PDT 24
Peak memory 211528 kb
Host smart-6cf9d2f9-a8b7-44f1-9321-b2d8adc8865a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654254559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all.
654254559
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.3491412981
Short name T96
Test name
Test status
Simulation time 277100496225 ps
CPU time 113.41 seconds
Started Jun 05 05:28:18 PM PDT 24
Finished Jun 05 05:30:12 PM PDT 24
Peak memory 210440 kb
Host smart-6c32cbe4-89f6-4d81-960f-11bd05c42d21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491412981 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.3491412981
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.1138457889
Short name T418
Test name
Test status
Simulation time 502996732 ps
CPU time 1.68 seconds
Started Jun 05 05:28:22 PM PDT 24
Finished Jun 05 05:28:24 PM PDT 24
Peak memory 201508 kb
Host smart-2f06c625-bd7d-44e8-a8d4-a46180e1ad14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138457889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.1138457889
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.3678513790
Short name T326
Test name
Test status
Simulation time 183577378781 ps
CPU time 411.57 seconds
Started Jun 05 05:28:19 PM PDT 24
Finished Jun 05 05:35:11 PM PDT 24
Peak memory 201880 kb
Host smart-f597af9b-ca0e-4b9c-a293-b600f471a241
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678513790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.3678513790
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.111199598
Short name T410
Test name
Test status
Simulation time 158831590614 ps
CPU time 181.56 seconds
Started Jun 05 05:28:20 PM PDT 24
Finished Jun 05 05:31:22 PM PDT 24
Peak memory 201788 kb
Host smart-bc5dcffc-b60d-4ce7-a6c2-45a66499cebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111199598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.111199598
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.4269145248
Short name T583
Test name
Test status
Simulation time 167129714247 ps
CPU time 29.38 seconds
Started Jun 05 05:28:17 PM PDT 24
Finished Jun 05 05:28:47 PM PDT 24
Peak memory 201812 kb
Host smart-f84a19ce-c513-4e6a-a684-3388de9216f7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269145248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.4269145248
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.318077372
Short name T609
Test name
Test status
Simulation time 490509931736 ps
CPU time 436.59 seconds
Started Jun 05 05:28:18 PM PDT 24
Finished Jun 05 05:35:36 PM PDT 24
Peak memory 201804 kb
Host smart-2b0ddfce-946e-4d70-b019-fb25de21ec77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318077372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.318077372
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.1476595683
Short name T522
Test name
Test status
Simulation time 486929655777 ps
CPU time 283.23 seconds
Started Jun 05 05:28:19 PM PDT 24
Finished Jun 05 05:33:03 PM PDT 24
Peak memory 201748 kb
Host smart-7d993ded-ba67-4f76-8188-ab01047ea8bd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476595683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.1476595683
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.1691668519
Short name T189
Test name
Test status
Simulation time 384251556681 ps
CPU time 215.96 seconds
Started Jun 05 05:28:19 PM PDT 24
Finished Jun 05 05:31:56 PM PDT 24
Peak memory 201820 kb
Host smart-2df7f9ab-9410-45c0-9c51-fcf0ec4552a6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691668519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.1691668519
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.1815861226
Short name T392
Test name
Test status
Simulation time 594231027316 ps
CPU time 717.78 seconds
Started Jun 05 05:28:19 PM PDT 24
Finished Jun 05 05:40:17 PM PDT 24
Peak memory 201852 kb
Host smart-921c9ca7-7602-4dbc-bf2d-b789758abe43
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815861226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.1815861226
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.3187456971
Short name T725
Test name
Test status
Simulation time 131984861822 ps
CPU time 572.53 seconds
Started Jun 05 05:28:23 PM PDT 24
Finished Jun 05 05:37:56 PM PDT 24
Peak memory 202084 kb
Host smart-7c18c22b-696d-422c-99ef-67513fa9e0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187456971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.3187456971
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.849060293
Short name T651
Test name
Test status
Simulation time 25804692224 ps
CPU time 16.74 seconds
Started Jun 05 05:28:22 PM PDT 24
Finished Jun 05 05:28:39 PM PDT 24
Peak memory 201580 kb
Host smart-cf6b7c65-2324-4709-a0ea-75b39481ad33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849060293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.849060293
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.382660127
Short name T695
Test name
Test status
Simulation time 4665694783 ps
CPU time 6.89 seconds
Started Jun 05 05:28:23 PM PDT 24
Finished Jun 05 05:28:30 PM PDT 24
Peak memory 201612 kb
Host smart-4e09a4c7-6ac0-46ea-ad28-cb43229c9bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382660127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.382660127
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.974689228
Short name T456
Test name
Test status
Simulation time 5805734674 ps
CPU time 3.06 seconds
Started Jun 05 05:28:19 PM PDT 24
Finished Jun 05 05:28:23 PM PDT 24
Peak memory 201644 kb
Host smart-43251874-eb49-4fc0-bfff-9632aba7ad26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974689228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.974689228
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.2939708216
Short name T692
Test name
Test status
Simulation time 354983291832 ps
CPU time 268.89 seconds
Started Jun 05 05:28:23 PM PDT 24
Finished Jun 05 05:32:53 PM PDT 24
Peak memory 201760 kb
Host smart-317290ef-5266-420c-8cfb-71e09ccf2f72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939708216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.2939708216
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.1635312599
Short name T421
Test name
Test status
Simulation time 347311161 ps
CPU time 0.8 seconds
Started Jun 05 05:28:40 PM PDT 24
Finished Jun 05 05:28:41 PM PDT 24
Peak memory 201504 kb
Host smart-433d50ca-ca9a-40d5-bdd9-e284f4dd44fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635312599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.1635312599
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.1115920056
Short name T532
Test name
Test status
Simulation time 358050138454 ps
CPU time 829.03 seconds
Started Jun 05 05:28:27 PM PDT 24
Finished Jun 05 05:42:17 PM PDT 24
Peak memory 201868 kb
Host smart-e4f8627a-0c48-4b3c-9a05-daedb10dd7d0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115920056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.1115920056
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.3014346304
Short name T261
Test name
Test status
Simulation time 338250327604 ps
CPU time 838.42 seconds
Started Jun 05 05:28:30 PM PDT 24
Finished Jun 05 05:42:29 PM PDT 24
Peak memory 201796 kb
Host smart-be9ce21b-c449-4388-a3d9-e60696e25943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014346304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.3014346304
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.4206369534
Short name T263
Test name
Test status
Simulation time 163618837387 ps
CPU time 30.66 seconds
Started Jun 05 05:28:29 PM PDT 24
Finished Jun 05 05:29:00 PM PDT 24
Peak memory 201812 kb
Host smart-c7f748f0-54a3-4795-8a2c-847474a05c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206369534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.4206369534
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.25050322
Short name T733
Test name
Test status
Simulation time 158395012740 ps
CPU time 30.4 seconds
Started Jun 05 05:28:27 PM PDT 24
Finished Jun 05 05:28:58 PM PDT 24
Peak memory 201764 kb
Host smart-679d2704-95e8-4dfb-8269-8e59c4cd5730
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=25050322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt
_fixed.25050322
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.1547714417
Short name T776
Test name
Test status
Simulation time 162892883438 ps
CPU time 201.84 seconds
Started Jun 05 05:28:29 PM PDT 24
Finished Jun 05 05:31:52 PM PDT 24
Peak memory 201792 kb
Host smart-fc1d796e-f87b-4334-958d-ffdd6cc9859d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547714417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.1547714417
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.2072952983
Short name T659
Test name
Test status
Simulation time 326560064137 ps
CPU time 715.37 seconds
Started Jun 05 05:28:31 PM PDT 24
Finished Jun 05 05:40:27 PM PDT 24
Peak memory 201856 kb
Host smart-ed2cceb8-bcb0-4fd0-bb08-35c652c19b42
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072952983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.2072952983
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.1654653426
Short name T550
Test name
Test status
Simulation time 358570278734 ps
CPU time 150.57 seconds
Started Jun 05 05:28:31 PM PDT 24
Finished Jun 05 05:31:02 PM PDT 24
Peak memory 201892 kb
Host smart-1c95afe9-7f06-4ba5-8a97-5b4c8c9ea55d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654653426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.1654653426
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.1064279301
Short name T775
Test name
Test status
Simulation time 603406576120 ps
CPU time 1460.85 seconds
Started Jun 05 05:28:30 PM PDT 24
Finished Jun 05 05:52:51 PM PDT 24
Peak memory 201804 kb
Host smart-7554fab2-aca7-455e-aefe-34c6e7ee3b12
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064279301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.1064279301
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.3057848682
Short name T662
Test name
Test status
Simulation time 111627493379 ps
CPU time 429.97 seconds
Started Jun 05 05:28:28 PM PDT 24
Finished Jun 05 05:35:39 PM PDT 24
Peak memory 202164 kb
Host smart-38cf1a97-afe7-47b2-b0c8-826f6ceac592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057848682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.3057848682
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.669214207
Short name T443
Test name
Test status
Simulation time 27516202710 ps
CPU time 30.7 seconds
Started Jun 05 05:28:30 PM PDT 24
Finished Jun 05 05:29:02 PM PDT 24
Peak memory 201620 kb
Host smart-746908f1-8852-494a-ae47-9dcb6e27b2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669214207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.669214207
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.4279772444
Short name T382
Test name
Test status
Simulation time 4592463301 ps
CPU time 5.44 seconds
Started Jun 05 05:28:27 PM PDT 24
Finished Jun 05 05:28:33 PM PDT 24
Peak memory 201776 kb
Host smart-6d3bfa06-394c-43bb-9a48-0211c0610782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279772444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.4279772444
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.3810668265
Short name T749
Test name
Test status
Simulation time 5875686150 ps
CPU time 15.42 seconds
Started Jun 05 05:28:22 PM PDT 24
Finished Jun 05 05:28:38 PM PDT 24
Peak memory 201640 kb
Host smart-9dc8c8c6-89a1-4527-ab77-5a7a6f666d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810668265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.3810668265
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.3514962708
Short name T633
Test name
Test status
Simulation time 40629185038 ps
CPU time 117.25 seconds
Started Jun 05 05:28:30 PM PDT 24
Finished Jun 05 05:30:29 PM PDT 24
Peak memory 210408 kb
Host smart-d3c1212e-9e0e-4b47-badf-b84e8e2ef918
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514962708 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.3514962708
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.2865820249
Short name T513
Test name
Test status
Simulation time 474911327 ps
CPU time 1.74 seconds
Started Jun 05 05:25:43 PM PDT 24
Finished Jun 05 05:25:45 PM PDT 24
Peak memory 201504 kb
Host smart-961a73cf-8c79-47ea-b5e0-abfc4fcc0e85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865820249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.2865820249
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.841350260
Short name T11
Test name
Test status
Simulation time 163969953093 ps
CPU time 394.64 seconds
Started Jun 05 05:25:49 PM PDT 24
Finished Jun 05 05:32:25 PM PDT 24
Peak memory 201852 kb
Host smart-227ff502-391d-4fb8-81f6-0f3517b95fd7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=841350260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt
_fixed.841350260
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.1015325341
Short name T778
Test name
Test status
Simulation time 162213028469 ps
CPU time 370.99 seconds
Started Jun 05 05:25:36 PM PDT 24
Finished Jun 05 05:31:48 PM PDT 24
Peak memory 201788 kb
Host smart-ee847029-067d-4ce7-96d3-5f4ff1b1a887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015325341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.1015325341
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.114334187
Short name T585
Test name
Test status
Simulation time 166085047522 ps
CPU time 72.89 seconds
Started Jun 05 05:25:45 PM PDT 24
Finished Jun 05 05:26:59 PM PDT 24
Peak memory 201792 kb
Host smart-4fd647b3-1c5d-48be-a9ba-32f3ef5162c2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=114334187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixed
.114334187
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.4095392435
Short name T570
Test name
Test status
Simulation time 646947294458 ps
CPU time 366.95 seconds
Started Jun 05 05:25:45 PM PDT 24
Finished Jun 05 05:31:53 PM PDT 24
Peak memory 201908 kb
Host smart-aca49307-67ca-46b4-92b1-b06c318a466e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095392435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.4095392435
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.1422591624
Short name T384
Test name
Test status
Simulation time 424513590221 ps
CPU time 446.67 seconds
Started Jun 05 05:25:45 PM PDT 24
Finished Jun 05 05:33:12 PM PDT 24
Peak memory 201792 kb
Host smart-d55abf3d-7ac4-4e37-b3cc-9ad867f73701
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422591624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.1422591624
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.3633621809
Short name T351
Test name
Test status
Simulation time 127013458609 ps
CPU time 514.63 seconds
Started Jun 05 05:25:46 PM PDT 24
Finished Jun 05 05:34:21 PM PDT 24
Peak memory 202092 kb
Host smart-d619c2d7-5c98-4419-b1d8-2e1de18be9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633621809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.3633621809
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.2825908611
Short name T666
Test name
Test status
Simulation time 38974193711 ps
CPU time 23.67 seconds
Started Jun 05 05:25:42 PM PDT 24
Finished Jun 05 05:26:07 PM PDT 24
Peak memory 201620 kb
Host smart-77a26d2c-af9e-4766-a412-d9dac3e69f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825908611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.2825908611
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.3420680480
Short name T584
Test name
Test status
Simulation time 4645540748 ps
CPU time 6.47 seconds
Started Jun 05 05:25:49 PM PDT 24
Finished Jun 05 05:25:56 PM PDT 24
Peak memory 201604 kb
Host smart-d36769e7-ad3f-489e-abcb-7f459927dbd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420680480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.3420680480
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.1218366659
Short name T70
Test name
Test status
Simulation time 4144944500 ps
CPU time 5.46 seconds
Started Jun 05 05:25:42 PM PDT 24
Finished Jun 05 05:25:48 PM PDT 24
Peak memory 217464 kb
Host smart-8252fc66-166c-4596-b6b8-9dd4a9a6d0c0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218366659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.1218366659
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.1384166507
Short name T643
Test name
Test status
Simulation time 5827688099 ps
CPU time 4.15 seconds
Started Jun 05 05:25:44 PM PDT 24
Finished Jun 05 05:25:49 PM PDT 24
Peak memory 201632 kb
Host smart-a6dd7eb7-55de-4703-9bf5-4c454f0d23c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384166507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.1384166507
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.2208661849
Short name T265
Test name
Test status
Simulation time 1414026544787 ps
CPU time 779.15 seconds
Started Jun 05 05:25:52 PM PDT 24
Finished Jun 05 05:38:52 PM PDT 24
Peak memory 212640 kb
Host smart-ff880a88-b524-4502-8958-a86b02e25492
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208661849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
2208661849
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.278462238
Short name T706
Test name
Test status
Simulation time 88690807666 ps
CPU time 57.01 seconds
Started Jun 05 05:25:51 PM PDT 24
Finished Jun 05 05:26:48 PM PDT 24
Peak memory 210120 kb
Host smart-c8ffc65c-3f82-4f22-a01d-d5287d63e5cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278462238 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.278462238
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.3325946546
Short name T375
Test name
Test status
Simulation time 528572621 ps
CPU time 0.93 seconds
Started Jun 05 05:28:46 PM PDT 24
Finished Jun 05 05:28:47 PM PDT 24
Peak memory 201488 kb
Host smart-77e5a160-558b-419c-bd05-37d295d614e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325946546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.3325946546
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.4262374549
Short name T273
Test name
Test status
Simulation time 332464917889 ps
CPU time 794.63 seconds
Started Jun 05 05:28:38 PM PDT 24
Finished Jun 05 05:41:53 PM PDT 24
Peak memory 201892 kb
Host smart-329ce9d7-5b4e-4edd-bf2c-37ac9b36dc4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262374549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.4262374549
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.2077135364
Short name T14
Test name
Test status
Simulation time 164589893204 ps
CPU time 195.02 seconds
Started Jun 05 05:28:38 PM PDT 24
Finished Jun 05 05:31:53 PM PDT 24
Peak memory 201800 kb
Host smart-acaf7b8e-bd05-4e0a-8d82-1f5fc2e33be3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077135364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.2077135364
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.263360169
Short name T453
Test name
Test status
Simulation time 162849246435 ps
CPU time 353.57 seconds
Started Jun 05 05:28:40 PM PDT 24
Finished Jun 05 05:34:34 PM PDT 24
Peak memory 201792 kb
Host smart-8b546a30-ba94-427f-9d52-0e50bcdfbc19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263360169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.263360169
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.3753588772
Short name T575
Test name
Test status
Simulation time 501501539147 ps
CPU time 107.52 seconds
Started Jun 05 05:28:35 PM PDT 24
Finished Jun 05 05:30:23 PM PDT 24
Peak memory 201784 kb
Host smart-743d93c6-8da2-4b7e-a666-5117a0799ace
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753588772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.3753588772
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.2503849363
Short name T246
Test name
Test status
Simulation time 188382757401 ps
CPU time 116.31 seconds
Started Jun 05 05:28:36 PM PDT 24
Finished Jun 05 05:30:33 PM PDT 24
Peak memory 201800 kb
Host smart-e5f07877-a87e-40ae-aa54-b6419b0b008d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503849363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.2503849363
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.1218329677
Short name T621
Test name
Test status
Simulation time 196476484427 ps
CPU time 76.75 seconds
Started Jun 05 05:28:39 PM PDT 24
Finished Jun 05 05:29:57 PM PDT 24
Peak memory 201768 kb
Host smart-889f0bce-6875-4b1c-a966-38aedc6c3c63
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218329677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.1218329677
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.191803623
Short name T430
Test name
Test status
Simulation time 103167764699 ps
CPU time 357.45 seconds
Started Jun 05 05:28:44 PM PDT 24
Finished Jun 05 05:34:43 PM PDT 24
Peak memory 202184 kb
Host smart-20a17f21-8400-40eb-9bef-fb201933185a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191803623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.191803623
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.2495826208
Short name T764
Test name
Test status
Simulation time 39866003718 ps
CPU time 22.13 seconds
Started Jun 05 05:28:45 PM PDT 24
Finished Jun 05 05:29:07 PM PDT 24
Peak memory 201624 kb
Host smart-d09f1e6a-839c-4e85-9a82-99743de094b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495826208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.2495826208
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.510026567
Short name T667
Test name
Test status
Simulation time 4124729018 ps
CPU time 3.14 seconds
Started Jun 05 05:28:44 PM PDT 24
Finished Jun 05 05:28:48 PM PDT 24
Peak memory 201612 kb
Host smart-c1172cd7-1935-4322-8ae3-76fb93461199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510026567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.510026567
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.2438010250
Short name T380
Test name
Test status
Simulation time 5636925594 ps
CPU time 13.49 seconds
Started Jun 05 05:28:39 PM PDT 24
Finished Jun 05 05:28:53 PM PDT 24
Peak memory 201640 kb
Host smart-c338b9bd-f94c-4c51-9b89-194c83476157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438010250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.2438010250
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.2132516336
Short name T787
Test name
Test status
Simulation time 335207903493 ps
CPU time 399.3 seconds
Started Jun 05 05:28:42 PM PDT 24
Finished Jun 05 05:35:22 PM PDT 24
Peak memory 201828 kb
Host smart-102241b4-5f00-402e-bdac-0431afc7d8a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132516336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.2132516336
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.556634398
Short name T758
Test name
Test status
Simulation time 186686503525 ps
CPU time 211.73 seconds
Started Jun 05 05:28:45 PM PDT 24
Finished Jun 05 05:32:17 PM PDT 24
Peak memory 210396 kb
Host smart-b1925e40-1ca0-4329-9de3-90d5e6ac85b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556634398 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.556634398
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.351112428
Short name T710
Test name
Test status
Simulation time 550543113 ps
CPU time 0.96 seconds
Started Jun 05 05:29:01 PM PDT 24
Finished Jun 05 05:29:03 PM PDT 24
Peak memory 201504 kb
Host smart-242ebddd-da5e-489c-a048-97dd27756c49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351112428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.351112428
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.2398144440
Short name T124
Test name
Test status
Simulation time 161339753374 ps
CPU time 349.62 seconds
Started Jun 05 05:28:53 PM PDT 24
Finished Jun 05 05:34:43 PM PDT 24
Peak memory 201880 kb
Host smart-8dd664b8-712e-440b-826f-d75c48c093d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398144440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.2398144440
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.719107581
Short name T197
Test name
Test status
Simulation time 496335364662 ps
CPU time 211.31 seconds
Started Jun 05 05:28:53 PM PDT 24
Finished Jun 05 05:32:25 PM PDT 24
Peak memory 201804 kb
Host smart-c2d5d3b8-1fe2-430a-9d59-32dab9aec95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719107581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.719107581
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.2981096667
Short name T655
Test name
Test status
Simulation time 497229953720 ps
CPU time 348.68 seconds
Started Jun 05 05:28:53 PM PDT 24
Finished Jun 05 05:34:42 PM PDT 24
Peak memory 201796 kb
Host smart-4d35fb3c-e4f3-45e3-ae32-302197b7317d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981096667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.2981096667
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.1300624245
Short name T745
Test name
Test status
Simulation time 173884281710 ps
CPU time 339.24 seconds
Started Jun 05 05:28:45 PM PDT 24
Finished Jun 05 05:34:24 PM PDT 24
Peak memory 201872 kb
Host smart-c1cc168d-b3a5-4b19-ba19-cf46a0aeb52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300624245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.1300624245
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.3562224423
Short name T639
Test name
Test status
Simulation time 336722073163 ps
CPU time 219.81 seconds
Started Jun 05 05:28:47 PM PDT 24
Finished Jun 05 05:32:27 PM PDT 24
Peak memory 201780 kb
Host smart-66d786be-c605-45d5-81bb-79639ecfeff0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562224423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.3562224423
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.3577777136
Short name T477
Test name
Test status
Simulation time 343998759872 ps
CPU time 436.83 seconds
Started Jun 05 05:28:54 PM PDT 24
Finished Jun 05 05:36:11 PM PDT 24
Peak memory 201884 kb
Host smart-2a29006e-0968-4274-beb4-daa50a95ec00
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577777136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.3577777136
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.1950488784
Short name T663
Test name
Test status
Simulation time 404428657860 ps
CPU time 971.19 seconds
Started Jun 05 05:28:52 PM PDT 24
Finished Jun 05 05:45:04 PM PDT 24
Peak memory 201804 kb
Host smart-b45d1380-a079-40c9-9195-01b64032d0eb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950488784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.1950488784
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.2640290190
Short name T704
Test name
Test status
Simulation time 37993179540 ps
CPU time 21.23 seconds
Started Jun 05 05:28:51 PM PDT 24
Finished Jun 05 05:29:12 PM PDT 24
Peak memory 201596 kb
Host smart-131ba6c7-26f7-4ca5-b7db-71cb6c8955e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640290190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.2640290190
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.2986183179
Short name T630
Test name
Test status
Simulation time 3793412748 ps
CPU time 9.96 seconds
Started Jun 05 05:28:52 PM PDT 24
Finished Jun 05 05:29:03 PM PDT 24
Peak memory 201632 kb
Host smart-8baf32e8-79de-462d-b826-04f66a742637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986183179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.2986183179
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.4126116276
Short name T539
Test name
Test status
Simulation time 5636563792 ps
CPU time 4.76 seconds
Started Jun 05 05:28:45 PM PDT 24
Finished Jun 05 05:28:50 PM PDT 24
Peak memory 201644 kb
Host smart-726db9a8-7699-47fe-8c9f-27baa5108e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126116276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.4126116276
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.4009814221
Short name T28
Test name
Test status
Simulation time 367872345667 ps
CPU time 913.57 seconds
Started Jun 05 05:29:02 PM PDT 24
Finished Jun 05 05:44:16 PM PDT 24
Peak memory 201804 kb
Host smart-70da646b-1c1a-4552-b768-0d43534c17b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009814221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.4009814221
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.441566846
Short name T364
Test name
Test status
Simulation time 109798875864 ps
CPU time 70.85 seconds
Started Jun 05 05:28:54 PM PDT 24
Finished Jun 05 05:30:05 PM PDT 24
Peak memory 210176 kb
Host smart-c0b2f523-0307-44dc-b66c-4682365db167
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441566846 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.441566846
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.3260211280
Short name T403
Test name
Test status
Simulation time 323762922 ps
CPU time 0.82 seconds
Started Jun 05 05:29:13 PM PDT 24
Finished Jun 05 05:29:14 PM PDT 24
Peak memory 201504 kb
Host smart-5fbec1a5-c8c8-4570-9e04-16ffbfae364b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260211280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.3260211280
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.3206313377
Short name T250
Test name
Test status
Simulation time 347298791294 ps
CPU time 784.24 seconds
Started Jun 05 05:29:07 PM PDT 24
Finished Jun 05 05:42:11 PM PDT 24
Peak memory 201804 kb
Host smart-0886a11b-0da5-4c36-9f4a-af3036dc38e3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206313377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.3206313377
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.424987094
Short name T303
Test name
Test status
Simulation time 488634239565 ps
CPU time 622.55 seconds
Started Jun 05 05:29:06 PM PDT 24
Finished Jun 05 05:39:29 PM PDT 24
Peak memory 201808 kb
Host smart-91ac2d31-c3e4-436f-a27c-8c04db36a2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424987094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.424987094
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.280548959
Short name T211
Test name
Test status
Simulation time 164033317535 ps
CPU time 99.7 seconds
Started Jun 05 05:29:08 PM PDT 24
Finished Jun 05 05:30:48 PM PDT 24
Peak memory 201804 kb
Host smart-79f44c8d-deaa-4fbb-93a6-5c1c2cc91037
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=280548959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrup
t_fixed.280548959
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.2832457544
Short name T432
Test name
Test status
Simulation time 327896182686 ps
CPU time 760.99 seconds
Started Jun 05 05:29:01 PM PDT 24
Finished Jun 05 05:41:42 PM PDT 24
Peak memory 201788 kb
Host smart-1561357d-dc99-4734-a733-60ec832aff52
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832457544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.2832457544
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.1964263776
Short name T204
Test name
Test status
Simulation time 370504533540 ps
CPU time 234.95 seconds
Started Jun 05 05:29:07 PM PDT 24
Finished Jun 05 05:33:03 PM PDT 24
Peak memory 201896 kb
Host smart-38340527-1982-4e2a-95d7-b3a5ef8f2625
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964263776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.1964263776
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.3672892459
Short name T436
Test name
Test status
Simulation time 605382389411 ps
CPU time 1480.92 seconds
Started Jun 05 05:29:08 PM PDT 24
Finished Jun 05 05:53:49 PM PDT 24
Peak memory 201796 kb
Host smart-c74c1e9f-bd14-4c60-b571-aa6ac8475246
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672892459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.3672892459
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.4169099781
Short name T642
Test name
Test status
Simulation time 85005065943 ps
CPU time 339.1 seconds
Started Jun 05 05:29:08 PM PDT 24
Finished Jun 05 05:34:47 PM PDT 24
Peak memory 202124 kb
Host smart-83c3cea8-7d82-4520-a22f-c2bdd119417b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169099781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.4169099781
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.1875918234
Short name T723
Test name
Test status
Simulation time 24184608815 ps
CPU time 55.18 seconds
Started Jun 05 05:29:10 PM PDT 24
Finished Jun 05 05:30:06 PM PDT 24
Peak memory 201620 kb
Host smart-b818cec1-efd6-4cf1-8eaf-83252f843f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875918234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.1875918234
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.623251880
Short name T129
Test name
Test status
Simulation time 3267233524 ps
CPU time 1.5 seconds
Started Jun 05 05:29:08 PM PDT 24
Finished Jun 05 05:29:10 PM PDT 24
Peak memory 201628 kb
Host smart-e0053f07-d509-45d8-9a9c-db04c2c4142a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623251880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.623251880
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.3036148090
Short name T645
Test name
Test status
Simulation time 5803415535 ps
CPU time 3.93 seconds
Started Jun 05 05:29:02 PM PDT 24
Finished Jun 05 05:29:06 PM PDT 24
Peak memory 201640 kb
Host smart-ef4b42d6-6482-4e4a-9ae4-809705d75602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036148090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.3036148090
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.3083089146
Short name T653
Test name
Test status
Simulation time 689005287810 ps
CPU time 1599.45 seconds
Started Jun 05 05:29:15 PM PDT 24
Finished Jun 05 05:55:55 PM PDT 24
Peak memory 201836 kb
Host smart-593f06c3-83c7-421a-affa-99c46b209917
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083089146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.3083089146
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.2188690489
Short name T561
Test name
Test status
Simulation time 529776971 ps
CPU time 1.89 seconds
Started Jun 05 05:29:30 PM PDT 24
Finished Jun 05 05:29:32 PM PDT 24
Peak memory 201656 kb
Host smart-96217f92-d0ab-436f-95ef-9c52d79ceedb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188690489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.2188690489
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.3949420487
Short name T732
Test name
Test status
Simulation time 370158329648 ps
CPU time 918.73 seconds
Started Jun 05 05:29:21 PM PDT 24
Finished Jun 05 05:44:40 PM PDT 24
Peak memory 201812 kb
Host smart-bae7d3d9-c717-4837-8bd7-f3dd50fadf21
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949420487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.3949420487
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.1912241211
Short name T192
Test name
Test status
Simulation time 499918150447 ps
CPU time 610.46 seconds
Started Jun 05 05:29:22 PM PDT 24
Finished Jun 05 05:39:33 PM PDT 24
Peak memory 201776 kb
Host smart-6372ec6b-c755-4cf0-b6c7-bd912878eebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912241211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.1912241211
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.2289354012
Short name T171
Test name
Test status
Simulation time 332101428825 ps
CPU time 169.93 seconds
Started Jun 05 05:29:21 PM PDT 24
Finished Jun 05 05:32:11 PM PDT 24
Peak memory 201804 kb
Host smart-2faec1ac-bfa8-4da9-a8bf-e44ca45f2c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289354012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.2289354012
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.3057743295
Short name T379
Test name
Test status
Simulation time 493620382135 ps
CPU time 1060.82 seconds
Started Jun 05 05:29:22 PM PDT 24
Finished Jun 05 05:47:03 PM PDT 24
Peak memory 201820 kb
Host smart-56149a1f-7a34-482d-9a8b-d402e020a65c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057743295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.3057743295
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.4148995155
Short name T315
Test name
Test status
Simulation time 497280632581 ps
CPU time 558.71 seconds
Started Jun 05 05:29:17 PM PDT 24
Finished Jun 05 05:38:37 PM PDT 24
Peak memory 201796 kb
Host smart-7b1a4912-750b-466b-9db2-bfbaf90d30b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148995155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.4148995155
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.387134527
Short name T741
Test name
Test status
Simulation time 165159603815 ps
CPU time 400.18 seconds
Started Jun 05 05:29:15 PM PDT 24
Finished Jun 05 05:35:56 PM PDT 24
Peak memory 201880 kb
Host smart-f53c158a-3f53-46d8-ad70-69ca69744f7d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=387134527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fixe
d.387134527
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.2536525326
Short name T183
Test name
Test status
Simulation time 436957085145 ps
CPU time 106.21 seconds
Started Jun 05 05:29:20 PM PDT 24
Finished Jun 05 05:31:07 PM PDT 24
Peak memory 201884 kb
Host smart-e3bed3af-e286-4e71-812e-960b55af6909
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536525326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.2536525326
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.1514864205
Short name T126
Test name
Test status
Simulation time 202242429989 ps
CPU time 100.83 seconds
Started Jun 05 05:29:22 PM PDT 24
Finished Jun 05 05:31:04 PM PDT 24
Peak memory 201792 kb
Host smart-7574ebca-9742-41d6-9ffb-9813ad284602
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514864205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.1514864205
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.1054258004
Short name T354
Test name
Test status
Simulation time 123354873446 ps
CPU time 456.8 seconds
Started Jun 05 05:29:22 PM PDT 24
Finished Jun 05 05:36:59 PM PDT 24
Peak memory 202128 kb
Host smart-cbe8d271-ec75-4dcb-acf0-5f7b8bc1f75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054258004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.1054258004
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.4255693683
Short name T455
Test name
Test status
Simulation time 35055329976 ps
CPU time 43.69 seconds
Started Jun 05 05:29:21 PM PDT 24
Finished Jun 05 05:30:05 PM PDT 24
Peak memory 201772 kb
Host smart-541a73d5-5f0c-4975-9e45-6bd11237ef46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255693683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.4255693683
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.1715086702
Short name T618
Test name
Test status
Simulation time 3845572309 ps
CPU time 9.85 seconds
Started Jun 05 05:29:21 PM PDT 24
Finished Jun 05 05:29:31 PM PDT 24
Peak memory 201580 kb
Host smart-87eb7646-d4ea-44c6-a923-bfb7232a5497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715086702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.1715086702
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.3706557739
Short name T606
Test name
Test status
Simulation time 5731525748 ps
CPU time 4.28 seconds
Started Jun 05 05:29:15 PM PDT 24
Finished Jun 05 05:29:19 PM PDT 24
Peak memory 201628 kb
Host smart-e4d478a9-5dfe-416e-8bd5-8d4876979437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706557739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.3706557739
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.318365830
Short name T21
Test name
Test status
Simulation time 54323773651 ps
CPU time 173.65 seconds
Started Jun 05 05:29:22 PM PDT 24
Finished Jun 05 05:32:16 PM PDT 24
Peak memory 210580 kb
Host smart-16d6ce19-9889-48f5-a252-002b5fa61b5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318365830 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.318365830
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.3398081688
Short name T654
Test name
Test status
Simulation time 442494061 ps
CPU time 0.87 seconds
Started Jun 05 05:29:44 PM PDT 24
Finished Jun 05 05:29:45 PM PDT 24
Peak memory 201492 kb
Host smart-9f95a4ef-91a5-46f2-9be8-777f058e9f31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398081688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.3398081688
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.2263708782
Short name T773
Test name
Test status
Simulation time 181731268330 ps
CPU time 199.46 seconds
Started Jun 05 05:29:35 PM PDT 24
Finished Jun 05 05:32:54 PM PDT 24
Peak memory 201804 kb
Host smart-cd279de0-2d4b-4f65-9e4d-cef4f4d768cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263708782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.2263708782
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.200404784
Short name T307
Test name
Test status
Simulation time 162061598692 ps
CPU time 102.21 seconds
Started Jun 05 05:29:28 PM PDT 24
Finished Jun 05 05:31:10 PM PDT 24
Peak memory 201788 kb
Host smart-23a95af1-c7ee-46d8-84e3-fa7b4ec799af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200404784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.200404784
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.2237244193
Short name T405
Test name
Test status
Simulation time 331402156105 ps
CPU time 671.59 seconds
Started Jun 05 05:29:36 PM PDT 24
Finished Jun 05 05:40:48 PM PDT 24
Peak memory 201752 kb
Host smart-b1f298cb-176e-4b7b-a49e-3044027ee0cd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237244193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.2237244193
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.4041011091
Short name T789
Test name
Test status
Simulation time 332474719649 ps
CPU time 605.91 seconds
Started Jun 05 05:29:30 PM PDT 24
Finished Jun 05 05:39:37 PM PDT 24
Peak memory 201804 kb
Host smart-e80aa4e3-c7d5-471e-8cc3-253634b479f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041011091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.4041011091
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.1351431692
Short name T579
Test name
Test status
Simulation time 159778644620 ps
CPU time 356.47 seconds
Started Jun 05 05:29:28 PM PDT 24
Finished Jun 05 05:35:25 PM PDT 24
Peak memory 201848 kb
Host smart-e6aa317d-6d2a-4556-b0b4-a9b2deedf3c1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351431692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.1351431692
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.2585205434
Short name T346
Test name
Test status
Simulation time 178191248014 ps
CPU time 439.87 seconds
Started Jun 05 05:29:40 PM PDT 24
Finished Jun 05 05:37:01 PM PDT 24
Peak memory 201880 kb
Host smart-c33f9aac-7ea3-4097-ba7e-ff5676a0032c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585205434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.2585205434
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.2699703369
Short name T587
Test name
Test status
Simulation time 201569844242 ps
CPU time 462.69 seconds
Started Jun 05 05:29:36 PM PDT 24
Finished Jun 05 05:37:19 PM PDT 24
Peak memory 201808 kb
Host smart-906f10a1-7883-4173-aa1e-ff8199193601
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699703369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.2699703369
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.2096096941
Short name T350
Test name
Test status
Simulation time 130991592422 ps
CPU time 524.29 seconds
Started Jun 05 05:29:44 PM PDT 24
Finished Jun 05 05:38:28 PM PDT 24
Peak memory 202180 kb
Host smart-e53a92fd-8532-4a0f-b3eb-95295e62275b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096096941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.2096096941
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.81324336
Short name T404
Test name
Test status
Simulation time 46645653938 ps
CPU time 28.09 seconds
Started Jun 05 05:29:43 PM PDT 24
Finished Jun 05 05:30:12 PM PDT 24
Peak memory 201636 kb
Host smart-e38f6fa5-2d31-4e2f-85df-7e282fe62693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81324336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.81324336
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.4043714185
Short name T525
Test name
Test status
Simulation time 4527449020 ps
CPU time 11.19 seconds
Started Jun 05 05:29:39 PM PDT 24
Finished Jun 05 05:29:51 PM PDT 24
Peak memory 201620 kb
Host smart-dbd7ebe6-c899-41b3-aee0-ad749e404175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043714185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.4043714185
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.1814223906
Short name T122
Test name
Test status
Simulation time 5929760064 ps
CPU time 15.27 seconds
Started Jun 05 05:29:30 PM PDT 24
Finished Jun 05 05:29:46 PM PDT 24
Peak memory 201628 kb
Host smart-c4debb31-3f3f-41d1-90f0-c78583e3ee0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814223906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.1814223906
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.2561743564
Short name T157
Test name
Test status
Simulation time 629169911236 ps
CPU time 732.15 seconds
Started Jun 05 05:29:43 PM PDT 24
Finished Jun 05 05:41:56 PM PDT 24
Peak memory 201816 kb
Host smart-4ca19740-3e65-4900-be4c-69a352a72c9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561743564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.2561743564
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.4083837810
Short name T503
Test name
Test status
Simulation time 380599265 ps
CPU time 0.87 seconds
Started Jun 05 05:29:52 PM PDT 24
Finished Jun 05 05:29:53 PM PDT 24
Peak memory 201492 kb
Host smart-cb270aa3-5b4e-491a-a637-23613f05ad8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083837810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.4083837810
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.1800281204
Short name T731
Test name
Test status
Simulation time 346119484735 ps
CPU time 207.9 seconds
Started Jun 05 05:29:52 PM PDT 24
Finished Jun 05 05:33:21 PM PDT 24
Peak memory 201772 kb
Host smart-a8d54542-45f4-4aaa-85da-3e8f6bcc83fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800281204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.1800281204
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.115072699
Short name T785
Test name
Test status
Simulation time 331490817864 ps
CPU time 268.02 seconds
Started Jun 05 05:29:52 PM PDT 24
Finished Jun 05 05:34:20 PM PDT 24
Peak memory 201784 kb
Host smart-e8ac66fc-47f4-4051-9178-0f04e223974d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115072699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.115072699
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.2328017548
Short name T689
Test name
Test status
Simulation time 486422543369 ps
CPU time 239.55 seconds
Started Jun 05 05:29:51 PM PDT 24
Finished Jun 05 05:33:51 PM PDT 24
Peak memory 201816 kb
Host smart-b36ea6fe-9718-4f24-9dba-de1a01d5a663
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328017548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.2328017548
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.129386966
Short name T196
Test name
Test status
Simulation time 487906974136 ps
CPU time 177.01 seconds
Started Jun 05 05:29:44 PM PDT 24
Finished Jun 05 05:32:42 PM PDT 24
Peak memory 201844 kb
Host smart-158da368-a9e2-463d-897d-282bb976802c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129386966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.129386966
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.2248156074
Short name T546
Test name
Test status
Simulation time 162752891548 ps
CPU time 354.85 seconds
Started Jun 05 05:29:42 PM PDT 24
Finished Jun 05 05:35:37 PM PDT 24
Peak memory 201792 kb
Host smart-4f4ac2a9-c266-406d-8ec2-7e0422d1162c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248156074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.2248156074
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.2961034613
Short name T676
Test name
Test status
Simulation time 351164845586 ps
CPU time 388.86 seconds
Started Jun 05 05:29:51 PM PDT 24
Finished Jun 05 05:36:20 PM PDT 24
Peak memory 201880 kb
Host smart-d6994d7c-fab1-4502-871e-a1629bac350f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961034613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.2961034613
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.104895344
Short name T674
Test name
Test status
Simulation time 599172306465 ps
CPU time 1523.96 seconds
Started Jun 05 05:29:51 PM PDT 24
Finished Jun 05 05:55:16 PM PDT 24
Peak memory 201808 kb
Host smart-3b72afc9-2781-4b31-b5e3-3c81f4f1b2ea
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104895344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
adc_ctrl_filters_wakeup_fixed.104895344
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.819553870
Short name T358
Test name
Test status
Simulation time 124540884428 ps
CPU time 490.15 seconds
Started Jun 05 05:29:52 PM PDT 24
Finished Jun 05 05:38:02 PM PDT 24
Peak memory 202176 kb
Host smart-0a94a5bf-e0c1-40c1-bee8-e5f25353ea2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819553870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.819553870
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.1551514281
Short name T537
Test name
Test status
Simulation time 23954544397 ps
CPU time 16.35 seconds
Started Jun 05 05:29:52 PM PDT 24
Finished Jun 05 05:30:09 PM PDT 24
Peak memory 201632 kb
Host smart-0ee7461d-7b7b-49db-a9a7-4f0af26eec9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551514281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.1551514281
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.1823201259
Short name T577
Test name
Test status
Simulation time 3521276794 ps
CPU time 8.89 seconds
Started Jun 05 05:29:50 PM PDT 24
Finished Jun 05 05:30:00 PM PDT 24
Peak memory 201600 kb
Host smart-15e8b8f7-88d2-4ef1-a585-ca0ef75646b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823201259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.1823201259
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.2811837119
Short name T656
Test name
Test status
Simulation time 5622337475 ps
CPU time 13.89 seconds
Started Jun 05 05:29:43 PM PDT 24
Finished Jun 05 05:29:57 PM PDT 24
Peak memory 201656 kb
Host smart-b37f9679-e249-4875-a4b2-e8f748dc5a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811837119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.2811837119
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.3501433466
Short name T718
Test name
Test status
Simulation time 255075741154 ps
CPU time 489.16 seconds
Started Jun 05 05:29:52 PM PDT 24
Finished Jun 05 05:38:01 PM PDT 24
Peak memory 202112 kb
Host smart-57713ff8-3c96-4f5f-807d-bb8327c13efa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501433466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.3501433466
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.1543525120
Short name T333
Test name
Test status
Simulation time 39575360794 ps
CPU time 112.43 seconds
Started Jun 05 05:29:50 PM PDT 24
Finished Jun 05 05:31:43 PM PDT 24
Peak memory 210412 kb
Host smart-96ab81f3-09f3-4af7-aa22-3742024a2f7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543525120 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.1543525120
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.2053844369
Short name T425
Test name
Test status
Simulation time 495406354 ps
CPU time 1.76 seconds
Started Jun 05 05:30:06 PM PDT 24
Finished Jun 05 05:30:08 PM PDT 24
Peak memory 201504 kb
Host smart-3be67129-c55a-4003-8200-9a8585c0f057
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053844369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.2053844369
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.2445293621
Short name T293
Test name
Test status
Simulation time 326533575862 ps
CPU time 179.09 seconds
Started Jun 05 05:29:57 PM PDT 24
Finished Jun 05 05:32:56 PM PDT 24
Peak memory 201780 kb
Host smart-fcd17ccc-3b11-4279-ad48-a88911019b37
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445293621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.2445293621
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.3454545443
Short name T347
Test name
Test status
Simulation time 336943570350 ps
CPU time 805.69 seconds
Started Jun 05 05:29:59 PM PDT 24
Finished Jun 05 05:43:25 PM PDT 24
Peak memory 201864 kb
Host smart-ee8300ae-4910-4fe5-be2c-041f52c3575e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454545443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.3454545443
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.3137131640
Short name T283
Test name
Test status
Simulation time 327950761235 ps
CPU time 281.92 seconds
Started Jun 05 05:29:57 PM PDT 24
Finished Jun 05 05:34:39 PM PDT 24
Peak memory 201884 kb
Host smart-a343eb5f-056e-4204-9a60-d66cc64b6efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137131640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.3137131640
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.3737325142
Short name T473
Test name
Test status
Simulation time 326930236459 ps
CPU time 301.69 seconds
Started Jun 05 05:29:58 PM PDT 24
Finished Jun 05 05:35:00 PM PDT 24
Peak memory 201820 kb
Host smart-5e6e3ffd-132c-4471-8b35-882814bec1bc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737325142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.3737325142
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.710401641
Short name T163
Test name
Test status
Simulation time 163418799526 ps
CPU time 94.89 seconds
Started Jun 05 05:29:59 PM PDT 24
Finished Jun 05 05:31:34 PM PDT 24
Peak memory 201796 kb
Host smart-2d32deaa-73fc-497f-9180-dcd37e982a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710401641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.710401641
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.2571583202
Short name T433
Test name
Test status
Simulation time 159433518462 ps
CPU time 87.42 seconds
Started Jun 05 05:29:59 PM PDT 24
Finished Jun 05 05:31:27 PM PDT 24
Peak memory 201776 kb
Host smart-7dbac489-24ef-4c59-9a58-a8c4f025f497
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571583202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.2571583202
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.4235205591
Short name T219
Test name
Test status
Simulation time 515849182598 ps
CPU time 169.77 seconds
Started Jun 05 05:29:56 PM PDT 24
Finished Jun 05 05:32:46 PM PDT 24
Peak memory 201840 kb
Host smart-7607bae3-70c9-481a-85a3-3daa4bd530c3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235205591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.4235205591
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.3372874442
Short name T466
Test name
Test status
Simulation time 588610082750 ps
CPU time 91.45 seconds
Started Jun 05 05:29:58 PM PDT 24
Finished Jun 05 05:31:30 PM PDT 24
Peak memory 201876 kb
Host smart-83d8922c-6df2-4ebc-80f0-223b8e08f6cf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372874442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.3372874442
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.3373031811
Short name T355
Test name
Test status
Simulation time 131230289722 ps
CPU time 704.81 seconds
Started Jun 05 05:30:00 PM PDT 24
Finished Jun 05 05:41:45 PM PDT 24
Peak memory 202108 kb
Host smart-b588cd85-68aa-42ea-8fc3-3cd214b360d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373031811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.3373031811
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.4233054343
Short name T177
Test name
Test status
Simulation time 42972633242 ps
CPU time 22.95 seconds
Started Jun 05 05:29:57 PM PDT 24
Finished Jun 05 05:30:21 PM PDT 24
Peak memory 201632 kb
Host smart-7151fc8d-d00d-4738-86cc-9d4754f69838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233054343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.4233054343
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.3797553991
Short name T398
Test name
Test status
Simulation time 5640980041 ps
CPU time 3.66 seconds
Started Jun 05 05:29:58 PM PDT 24
Finished Jun 05 05:30:02 PM PDT 24
Peak memory 201600 kb
Host smart-5099cf57-4a8b-4beb-8cfb-59ecf6c68a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797553991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.3797553991
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.2918357907
Short name T730
Test name
Test status
Simulation time 5722018414 ps
CPU time 15.37 seconds
Started Jun 05 05:29:52 PM PDT 24
Finished Jun 05 05:30:07 PM PDT 24
Peak memory 201640 kb
Host smart-7a05b578-0a89-444d-b0f5-e41fb71bfa25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918357907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.2918357907
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.4159922262
Short name T734
Test name
Test status
Simulation time 8568749719 ps
CPU time 5.62 seconds
Started Jun 05 05:30:04 PM PDT 24
Finished Jun 05 05:30:10 PM PDT 24
Peak memory 201624 kb
Host smart-5f046ef2-06bf-4e65-a934-0e0c0fa8102c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159922262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.4159922262
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.767168589
Short name T24
Test name
Test status
Simulation time 229231942619 ps
CPU time 112.56 seconds
Started Jun 05 05:30:07 PM PDT 24
Finished Jun 05 05:32:00 PM PDT 24
Peak memory 212448 kb
Host smart-fc18fcc4-68b3-41cb-ac90-21ebda26dce2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767168589 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.767168589
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.3417660918
Short name T516
Test name
Test status
Simulation time 465725096 ps
CPU time 1.71 seconds
Started Jun 05 05:30:29 PM PDT 24
Finished Jun 05 05:30:31 PM PDT 24
Peak memory 201512 kb
Host smart-b980bb8f-cfdb-412a-a9b8-ed2e82baef0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417660918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.3417660918
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.2252166890
Short name T235
Test name
Test status
Simulation time 494725283791 ps
CPU time 1146.68 seconds
Started Jun 05 05:30:13 PM PDT 24
Finished Jun 05 05:49:21 PM PDT 24
Peak memory 201892 kb
Host smart-b00c25d2-ea17-4681-9d2d-dd77ba43f886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252166890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.2252166890
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.2163853419
Short name T441
Test name
Test status
Simulation time 322519391365 ps
CPU time 133.04 seconds
Started Jun 05 05:30:12 PM PDT 24
Finished Jun 05 05:32:26 PM PDT 24
Peak memory 201820 kb
Host smart-960d4450-5f76-48f8-bc60-3f3a35922cc9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163853419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.2163853419
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.3190509202
Short name T297
Test name
Test status
Simulation time 327903848282 ps
CPU time 770.86 seconds
Started Jun 05 05:30:13 PM PDT 24
Finished Jun 05 05:43:05 PM PDT 24
Peak memory 201752 kb
Host smart-9138d252-da0d-41ad-82fc-2c630d3164e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190509202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.3190509202
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.3509020780
Short name T8
Test name
Test status
Simulation time 485803101974 ps
CPU time 621.75 seconds
Started Jun 05 05:30:13 PM PDT 24
Finished Jun 05 05:40:36 PM PDT 24
Peak memory 201824 kb
Host smart-45edb045-9786-41fb-a630-3b9eded5881a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509020780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.3509020780
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.1720884188
Short name T512
Test name
Test status
Simulation time 529042172619 ps
CPU time 614.49 seconds
Started Jun 05 05:30:15 PM PDT 24
Finished Jun 05 05:40:30 PM PDT 24
Peak memory 201816 kb
Host smart-eae59d13-c038-43bd-92c0-2c705478045e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720884188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.1720884188
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.1895922584
Short name T556
Test name
Test status
Simulation time 601174957960 ps
CPU time 665.94 seconds
Started Jun 05 05:30:13 PM PDT 24
Finished Jun 05 05:41:19 PM PDT 24
Peak memory 201816 kb
Host smart-e24e5bd3-2951-4325-b861-e3df92264315
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895922584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.1895922584
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.565298658
Short name T366
Test name
Test status
Simulation time 80809396086 ps
CPU time 308.92 seconds
Started Jun 05 05:30:20 PM PDT 24
Finished Jun 05 05:35:29 PM PDT 24
Peak memory 202124 kb
Host smart-9f7482c0-ff49-4b98-aa50-a0e272721806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565298658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.565298658
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.1608846723
Short name T413
Test name
Test status
Simulation time 39438385253 ps
CPU time 98.18 seconds
Started Jun 05 05:30:22 PM PDT 24
Finished Jun 05 05:32:01 PM PDT 24
Peak memory 201624 kb
Host smart-7c43a94b-bf4b-48cb-bb45-334a7c4f5c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608846723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.1608846723
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.1425095050
Short name T26
Test name
Test status
Simulation time 4870637061 ps
CPU time 12.62 seconds
Started Jun 05 05:30:19 PM PDT 24
Finished Jun 05 05:30:33 PM PDT 24
Peak memory 201612 kb
Host smart-683d585f-dafd-4ca1-95f0-c592dc461bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425095050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.1425095050
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.167212291
Short name T9
Test name
Test status
Simulation time 5826152745 ps
CPU time 4.51 seconds
Started Jun 05 05:30:06 PM PDT 24
Finished Jun 05 05:30:11 PM PDT 24
Peak memory 201628 kb
Host smart-30b2c559-c90f-45ab-82d8-97beaa60e6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167212291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.167212291
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.4007599630
Short name T65
Test name
Test status
Simulation time 243161916347 ps
CPU time 201.16 seconds
Started Jun 05 05:30:21 PM PDT 24
Finished Jun 05 05:33:42 PM PDT 24
Peak memory 210508 kb
Host smart-ad7938a3-700d-4db6-9061-5c1bf5eae4e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007599630 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.4007599630
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.775308580
Short name T370
Test name
Test status
Simulation time 514880909 ps
CPU time 1.2 seconds
Started Jun 05 05:30:37 PM PDT 24
Finished Jun 05 05:30:39 PM PDT 24
Peak memory 201508 kb
Host smart-5aeb3904-c120-4d9b-82d3-240aa1885f24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775308580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.775308580
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.2645499778
Short name T288
Test name
Test status
Simulation time 370758673524 ps
CPU time 189.85 seconds
Started Jun 05 05:30:30 PM PDT 24
Finished Jun 05 05:33:40 PM PDT 24
Peak memory 201960 kb
Host smart-ed69178d-8d02-447b-b156-94198f6eb3f4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645499778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.2645499778
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.403421097
Short name T260
Test name
Test status
Simulation time 318574485447 ps
CPU time 178.44 seconds
Started Jun 05 05:30:28 PM PDT 24
Finished Jun 05 05:33:26 PM PDT 24
Peak memory 201808 kb
Host smart-ede21545-301f-4332-a9ca-6a9306461ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403421097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.403421097
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.1473879476
Short name T719
Test name
Test status
Simulation time 164760156081 ps
CPU time 373.83 seconds
Started Jun 05 05:30:29 PM PDT 24
Finished Jun 05 05:36:44 PM PDT 24
Peak memory 201808 kb
Host smart-bf36f928-3c86-4131-a52a-6417af439c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473879476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.1473879476
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.3810253369
Short name T701
Test name
Test status
Simulation time 492969158140 ps
CPU time 320.76 seconds
Started Jun 05 05:30:30 PM PDT 24
Finished Jun 05 05:35:51 PM PDT 24
Peak memory 201788 kb
Host smart-7c3bc57f-d163-4a2b-95d7-459dd4789e7e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810253369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.3810253369
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.21297054
Short name T190
Test name
Test status
Simulation time 488472009408 ps
CPU time 594.69 seconds
Started Jun 05 05:30:29 PM PDT 24
Finished Jun 05 05:40:24 PM PDT 24
Peak memory 201796 kb
Host smart-39dedbc7-c2b5-4ed7-9e26-6d2b75ae3aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21297054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.21297054
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.2551089515
Short name T670
Test name
Test status
Simulation time 175202210503 ps
CPU time 425.26 seconds
Started Jun 05 05:30:30 PM PDT 24
Finished Jun 05 05:37:36 PM PDT 24
Peak memory 201764 kb
Host smart-e4652e7d-eeae-48b1-89a5-66c85a78fee5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551089515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.2551089515
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.765414338
Short name T672
Test name
Test status
Simulation time 388322112560 ps
CPU time 1007.95 seconds
Started Jun 05 05:30:27 PM PDT 24
Finished Jun 05 05:47:16 PM PDT 24
Peak memory 201804 kb
Host smart-49fdd58b-a1ab-49fc-a6c3-b23e7b5e6a7f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765414338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_
wakeup.765414338
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.718318314
Short name T571
Test name
Test status
Simulation time 619460052187 ps
CPU time 364.33 seconds
Started Jun 05 05:30:30 PM PDT 24
Finished Jun 05 05:36:34 PM PDT 24
Peak memory 201876 kb
Host smart-8618720a-569c-4502-9e2d-0ed263a67726
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718318314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
adc_ctrl_filters_wakeup_fixed.718318314
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.4288943218
Short name T781
Test name
Test status
Simulation time 102853484422 ps
CPU time 366.41 seconds
Started Jun 05 05:30:35 PM PDT 24
Finished Jun 05 05:36:42 PM PDT 24
Peak memory 202120 kb
Host smart-4d493c22-3a79-4257-8a98-586206c4618b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288943218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.4288943218
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.372192530
Short name T123
Test name
Test status
Simulation time 32563384854 ps
CPU time 18.84 seconds
Started Jun 05 05:30:37 PM PDT 24
Finished Jun 05 05:30:56 PM PDT 24
Peak memory 201612 kb
Host smart-51cf2256-8cdb-4268-ac10-05b29c513f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372192530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.372192530
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.2587932168
Short name T116
Test name
Test status
Simulation time 3206755177 ps
CPU time 8.34 seconds
Started Jun 05 05:30:37 PM PDT 24
Finished Jun 05 05:30:46 PM PDT 24
Peak memory 201628 kb
Host smart-4dc888dc-5418-42c5-9dfa-c72a0943c6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587932168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.2587932168
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.297445407
Short name T620
Test name
Test status
Simulation time 5627713415 ps
CPU time 6.89 seconds
Started Jun 05 05:30:27 PM PDT 24
Finished Jun 05 05:30:34 PM PDT 24
Peak memory 201640 kb
Host smart-381d5acf-adb9-4916-b4b5-3de8f42f6065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297445407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.297445407
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.459075560
Short name T470
Test name
Test status
Simulation time 63820110254 ps
CPU time 280.29 seconds
Started Jun 05 05:30:34 PM PDT 24
Finished Jun 05 05:35:15 PM PDT 24
Peak memory 202180 kb
Host smart-ef9cfe3f-f9bf-48b7-8a28-b1f357fa31ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459075560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all.
459075560
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.3694409196
Short name T316
Test name
Test status
Simulation time 118016630981 ps
CPU time 120.72 seconds
Started Jun 05 05:30:36 PM PDT 24
Finished Jun 05 05:32:37 PM PDT 24
Peak memory 210400 kb
Host smart-30a8a815-7836-4a75-94a2-24eb8bb18400
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694409196 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.3694409196
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.1459479784
Short name T528
Test name
Test status
Simulation time 428349154 ps
CPU time 1.69 seconds
Started Jun 05 05:30:52 PM PDT 24
Finished Jun 05 05:30:54 PM PDT 24
Peak memory 201668 kb
Host smart-961f8947-55f3-4166-bdfb-e59d2ad0a5e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459479784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.1459479784
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.1964780340
Short name T209
Test name
Test status
Simulation time 349226570814 ps
CPU time 234.68 seconds
Started Jun 05 05:30:51 PM PDT 24
Finished Jun 05 05:34:46 PM PDT 24
Peak memory 201880 kb
Host smart-ddb085ed-c026-40b7-84d7-ecaeec33e8f5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964780340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.1964780340
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.681002309
Short name T240
Test name
Test status
Simulation time 323148436254 ps
CPU time 410.72 seconds
Started Jun 05 05:30:49 PM PDT 24
Finished Jun 05 05:37:40 PM PDT 24
Peak memory 201800 kb
Host smart-7288808a-2015-444a-a9d5-f3afce515cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681002309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.681002309
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.3162688003
Short name T266
Test name
Test status
Simulation time 167234116798 ps
CPU time 390.6 seconds
Started Jun 05 05:30:49 PM PDT 24
Finished Jun 05 05:37:20 PM PDT 24
Peak memory 201880 kb
Host smart-5c9f6f34-5fc0-40d4-aedb-3715d07c25b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162688003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.3162688003
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.2495615716
Short name T507
Test name
Test status
Simulation time 319620908507 ps
CPU time 206.65 seconds
Started Jun 05 05:30:49 PM PDT 24
Finished Jun 05 05:34:17 PM PDT 24
Peak memory 201816 kb
Host smart-0195f96e-39f2-4bad-9707-43e7bc4009b2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495615716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.2495615716
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.2259797722
Short name T160
Test name
Test status
Simulation time 488464378591 ps
CPU time 569 seconds
Started Jun 05 05:30:49 PM PDT 24
Finished Jun 05 05:40:19 PM PDT 24
Peak memory 201864 kb
Host smart-680e5512-51e9-44d5-8e46-89cfabdb779c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259797722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.2259797722
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.1152291693
Short name T447
Test name
Test status
Simulation time 502167032605 ps
CPU time 282.71 seconds
Started Jun 05 05:30:49 PM PDT 24
Finished Jun 05 05:35:32 PM PDT 24
Peak memory 201776 kb
Host smart-b6fedeba-9b46-46c3-8ed3-6fdffe44fa52
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152291693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.1152291693
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.2187642011
Short name T755
Test name
Test status
Simulation time 557346241823 ps
CPU time 369.11 seconds
Started Jun 05 05:30:49 PM PDT 24
Finished Jun 05 05:36:59 PM PDT 24
Peak memory 201896 kb
Host smart-e7772ac6-7851-493e-8efd-9bd9507d265f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187642011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.2187642011
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.3839118658
Short name T484
Test name
Test status
Simulation time 200892074729 ps
CPU time 467.43 seconds
Started Jun 05 05:30:50 PM PDT 24
Finished Jun 05 05:38:38 PM PDT 24
Peak memory 201872 kb
Host smart-0969e8aa-3496-47ef-bcce-bf2f07e3d1fd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839118658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.3839118658
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.629115540
Short name T543
Test name
Test status
Simulation time 84757636981 ps
CPU time 272.67 seconds
Started Jun 05 05:30:57 PM PDT 24
Finished Jun 05 05:35:30 PM PDT 24
Peak memory 202088 kb
Host smart-24e5e07f-182c-489f-a0ba-f71e62ab8c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629115540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.629115540
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.1404550159
Short name T480
Test name
Test status
Simulation time 44013842504 ps
CPU time 100.97 seconds
Started Jun 05 05:30:50 PM PDT 24
Finished Jun 05 05:32:32 PM PDT 24
Peak memory 201604 kb
Host smart-45026769-f035-4bdf-a722-1bdebb7c492c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404550159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.1404550159
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.3795889563
Short name T454
Test name
Test status
Simulation time 4988650503 ps
CPU time 12.71 seconds
Started Jun 05 05:30:57 PM PDT 24
Finished Jun 05 05:31:10 PM PDT 24
Peak memory 201600 kb
Host smart-3db7078d-e403-4c7a-a8b4-f77dc9aaf3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795889563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.3795889563
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.3756518414
Short name T698
Test name
Test status
Simulation time 6067021160 ps
CPU time 4.99 seconds
Started Jun 05 05:30:46 PM PDT 24
Finished Jun 05 05:30:51 PM PDT 24
Peak memory 201628 kb
Host smart-39d048c3-694d-4369-9eb3-c2f480bbe57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756518414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.3756518414
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.1128894474
Short name T166
Test name
Test status
Simulation time 194663677822 ps
CPU time 37.05 seconds
Started Jun 05 05:30:58 PM PDT 24
Finished Jun 05 05:31:36 PM PDT 24
Peak memory 201776 kb
Host smart-780967ce-9083-4a97-96db-91426f202934
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128894474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.1128894474
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.2109133666
Short name T17
Test name
Test status
Simulation time 235208892507 ps
CPU time 304.56 seconds
Started Jun 05 05:30:59 PM PDT 24
Finished Jun 05 05:36:04 PM PDT 24
Peak memory 210460 kb
Host smart-72e7d1b2-44ca-41a3-a75f-6ec94d3c2f4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109133666 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.2109133666
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.1203930157
Short name T668
Test name
Test status
Simulation time 423853317 ps
CPU time 0.88 seconds
Started Jun 05 05:25:47 PM PDT 24
Finished Jun 05 05:25:48 PM PDT 24
Peak memory 201496 kb
Host smart-90c33404-2e13-43e6-9104-4c770718a88c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203930157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.1203930157
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.835880336
Short name T564
Test name
Test status
Simulation time 183912251323 ps
CPU time 22.38 seconds
Started Jun 05 05:25:53 PM PDT 24
Finished Jun 05 05:26:16 PM PDT 24
Peak memory 201788 kb
Host smart-09b73243-6a44-4c79-9381-64c19cd9a81b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835880336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gatin
g.835880336
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.251246717
Short name T206
Test name
Test status
Simulation time 178164024541 ps
CPU time 94.75 seconds
Started Jun 05 05:25:44 PM PDT 24
Finished Jun 05 05:27:19 PM PDT 24
Peak memory 201772 kb
Host smart-b89c59dc-b016-4988-8966-76277ee5eba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251246717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.251246717
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.2232992529
Short name T253
Test name
Test status
Simulation time 496275778388 ps
CPU time 710.97 seconds
Started Jun 05 05:25:45 PM PDT 24
Finished Jun 05 05:37:36 PM PDT 24
Peak memory 201832 kb
Host smart-403a8fc4-4ba2-4874-83cd-84623d40e845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232992529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.2232992529
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.4024329615
Short name T226
Test name
Test status
Simulation time 162605678925 ps
CPU time 358.18 seconds
Started Jun 05 05:25:43 PM PDT 24
Finished Jun 05 05:31:42 PM PDT 24
Peak memory 201788 kb
Host smart-9b03bc4d-9cbb-4c10-bcd3-497c734c0d6e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024329615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.4024329615
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.202431462
Short name T652
Test name
Test status
Simulation time 491925731635 ps
CPU time 616.76 seconds
Started Jun 05 05:25:47 PM PDT 24
Finished Jun 05 05:36:04 PM PDT 24
Peak memory 201780 kb
Host smart-cb5a7ed1-28db-4e1c-a0a4-747eb5bb3d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202431462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.202431462
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.562665540
Short name T222
Test name
Test status
Simulation time 325317713108 ps
CPU time 100.76 seconds
Started Jun 05 05:25:44 PM PDT 24
Finished Jun 05 05:27:26 PM PDT 24
Peak memory 201816 kb
Host smart-5fa61595-da2a-44e1-b824-58bf69ae32a4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=562665540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixed
.562665540
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.4266941067
Short name T496
Test name
Test status
Simulation time 194144894130 ps
CPU time 113.82 seconds
Started Jun 05 05:25:43 PM PDT 24
Finished Jun 05 05:27:37 PM PDT 24
Peak memory 201800 kb
Host smart-278d5d6c-0b15-45d3-89d8-6e8b2dea103b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266941067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.4266941067
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.2117066437
Short name T352
Test name
Test status
Simulation time 114445489423 ps
CPU time 428.24 seconds
Started Jun 05 05:25:44 PM PDT 24
Finished Jun 05 05:32:53 PM PDT 24
Peak memory 202208 kb
Host smart-526cda89-4d62-4325-adbd-0b5fb82a3e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117066437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.2117066437
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.814558061
Short name T415
Test name
Test status
Simulation time 36808645619 ps
CPU time 40.68 seconds
Started Jun 05 05:25:47 PM PDT 24
Finished Jun 05 05:26:28 PM PDT 24
Peak memory 201616 kb
Host smart-ffc34ebf-dd3b-4c52-ad26-b69caa571320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814558061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.814558061
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.1306879377
Short name T498
Test name
Test status
Simulation time 4780274344 ps
CPU time 3.3 seconds
Started Jun 05 05:25:43 PM PDT 24
Finished Jun 05 05:25:47 PM PDT 24
Peak memory 201780 kb
Host smart-fa62e38f-e887-4096-93e9-b6383d0fa27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306879377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.1306879377
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.201295481
Short name T86
Test name
Test status
Simulation time 7817171216 ps
CPU time 10.18 seconds
Started Jun 05 05:25:47 PM PDT 24
Finished Jun 05 05:25:58 PM PDT 24
Peak memory 218436 kb
Host smart-17bd4f7c-ea1c-4127-81f1-19738c904be3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201295481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.201295481
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.3668471932
Short name T458
Test name
Test status
Simulation time 6069839244 ps
CPU time 16.14 seconds
Started Jun 05 05:25:51 PM PDT 24
Finished Jun 05 05:26:08 PM PDT 24
Peak memory 201636 kb
Host smart-fa4444bc-97ab-4ed1-9853-730dda1f80e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668471932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.3668471932
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.4221030987
Short name T241
Test name
Test status
Simulation time 338727610878 ps
CPU time 747.48 seconds
Started Jun 05 05:25:49 PM PDT 24
Finished Jun 05 05:38:17 PM PDT 24
Peak memory 201780 kb
Host smart-990ef43b-d218-4e9c-9f13-478c5d8d9baa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221030987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
4221030987
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.912198154
Short name T475
Test name
Test status
Simulation time 388526343 ps
CPU time 1.12 seconds
Started Jun 05 05:31:07 PM PDT 24
Finished Jun 05 05:31:09 PM PDT 24
Peak memory 201504 kb
Host smart-ea8a7c05-d96d-4144-a7ea-186a7d357a11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912198154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.912198154
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.2313285466
Short name T239
Test name
Test status
Simulation time 165839019359 ps
CPU time 109.26 seconds
Started Jun 05 05:30:58 PM PDT 24
Finished Jun 05 05:32:47 PM PDT 24
Peak memory 201884 kb
Host smart-fe92eb50-8ef7-4d90-9c3c-4aa4c030b5ed
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313285466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.2313285466
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.798447434
Short name T314
Test name
Test status
Simulation time 163437973336 ps
CPU time 91.6 seconds
Started Jun 05 05:30:58 PM PDT 24
Finished Jun 05 05:32:30 PM PDT 24
Peak memory 201796 kb
Host smart-d456a3c5-7e79-48ad-8a47-f0fb9da9d51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798447434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.798447434
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.1049491277
Short name T544
Test name
Test status
Simulation time 490340499310 ps
CPU time 1134.18 seconds
Started Jun 05 05:30:57 PM PDT 24
Finished Jun 05 05:49:52 PM PDT 24
Peak memory 201776 kb
Host smart-52a9d342-2772-44d4-aeba-c9a57c025d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049491277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.1049491277
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.730629215
Short name T589
Test name
Test status
Simulation time 162823623458 ps
CPU time 255.61 seconds
Started Jun 05 05:30:51 PM PDT 24
Finished Jun 05 05:35:07 PM PDT 24
Peak memory 201748 kb
Host smart-3607ebe8-87ee-4c64-9b0c-46412ad0c4b9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=730629215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrup
t_fixed.730629215
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.1503948674
Short name T439
Test name
Test status
Simulation time 160240055262 ps
CPU time 363.95 seconds
Started Jun 05 05:30:49 PM PDT 24
Finished Jun 05 05:36:54 PM PDT 24
Peak memory 201872 kb
Host smart-aa00c9f3-c8e9-43fa-9ba4-a9d5e914366e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503948674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.1503948674
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.2565592212
Short name T657
Test name
Test status
Simulation time 327695146350 ps
CPU time 202.92 seconds
Started Jun 05 05:30:52 PM PDT 24
Finished Jun 05 05:34:15 PM PDT 24
Peak memory 201784 kb
Host smart-916b8e34-379d-405e-8d8f-fd95a4597983
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565592212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.2565592212
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.3430590714
Short name T598
Test name
Test status
Simulation time 197511869212 ps
CPU time 109.88 seconds
Started Jun 05 05:30:56 PM PDT 24
Finished Jun 05 05:32:47 PM PDT 24
Peak memory 201812 kb
Host smart-f489706b-2bb7-44cc-9755-931115968ff7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430590714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.3430590714
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.258945147
Short name T378
Test name
Test status
Simulation time 78204699334 ps
CPU time 422.48 seconds
Started Jun 05 05:31:08 PM PDT 24
Finished Jun 05 05:38:11 PM PDT 24
Peak memory 202064 kb
Host smart-12fb3f78-1853-4096-955e-3b1f7f0ef672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258945147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.258945147
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.533332112
Short name T531
Test name
Test status
Simulation time 43135910215 ps
CPU time 106.74 seconds
Started Jun 05 05:31:07 PM PDT 24
Finished Jun 05 05:32:54 PM PDT 24
Peak memory 201628 kb
Host smart-b8dc53ef-b45b-42ca-87d4-4290f09ee5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533332112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.533332112
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.3454902127
Short name T381
Test name
Test status
Simulation time 5143334294 ps
CPU time 2.14 seconds
Started Jun 05 05:31:08 PM PDT 24
Finished Jun 05 05:31:10 PM PDT 24
Peak memory 201628 kb
Host smart-18efde72-6ae6-4d64-9561-fc3cb38fa786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454902127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.3454902127
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.3405965116
Short name T94
Test name
Test status
Simulation time 5839572745 ps
CPU time 16.11 seconds
Started Jun 05 05:30:48 PM PDT 24
Finished Jun 05 05:31:04 PM PDT 24
Peak memory 201636 kb
Host smart-bf043786-9c5c-4706-8f6a-493a5ee8ad87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405965116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.3405965116
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.230027699
Short name T36
Test name
Test status
Simulation time 198449502245 ps
CPU time 231.72 seconds
Started Jun 05 05:31:05 PM PDT 24
Finished Jun 05 05:34:57 PM PDT 24
Peak memory 201808 kb
Host smart-414ce377-2d08-406f-9ee3-b380c057653c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230027699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all.
230027699
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.2013990070
Short name T468
Test name
Test status
Simulation time 362994222 ps
CPU time 1.47 seconds
Started Jun 05 05:31:12 PM PDT 24
Finished Jun 05 05:31:13 PM PDT 24
Peak memory 201492 kb
Host smart-0b0de49d-d05a-4f61-9983-583fcb4e9ab2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013990070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.2013990070
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.1179757653
Short name T245
Test name
Test status
Simulation time 159770921565 ps
CPU time 190.31 seconds
Started Jun 05 05:31:14 PM PDT 24
Finished Jun 05 05:34:25 PM PDT 24
Peak memory 201884 kb
Host smart-d75d09bb-b370-40dc-8856-f43095a57d91
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179757653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.1179757653
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.629226658
Short name T746
Test name
Test status
Simulation time 164948803648 ps
CPU time 384.81 seconds
Started Jun 05 05:31:13 PM PDT 24
Finished Jun 05 05:37:39 PM PDT 24
Peak memory 201856 kb
Host smart-a14d66a4-9511-4528-ba25-d434d60ea1df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629226658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.629226658
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.1025762992
Short name T420
Test name
Test status
Simulation time 322029372906 ps
CPU time 825.16 seconds
Started Jun 05 05:31:14 PM PDT 24
Finished Jun 05 05:45:00 PM PDT 24
Peak memory 201820 kb
Host smart-d6d1ef7d-678c-41eb-a0fd-de2e36b61821
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025762992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.1025762992
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.433353714
Short name T438
Test name
Test status
Simulation time 158643384147 ps
CPU time 332.11 seconds
Started Jun 05 05:31:07 PM PDT 24
Finished Jun 05 05:36:39 PM PDT 24
Peak memory 201800 kb
Host smart-9a429c6f-71aa-40bd-a403-ba1e9a2ac0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433353714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.433353714
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.1267690133
Short name T406
Test name
Test status
Simulation time 488905233901 ps
CPU time 282.29 seconds
Started Jun 05 05:31:07 PM PDT 24
Finished Jun 05 05:35:50 PM PDT 24
Peak memory 201760 kb
Host smart-713dfc86-6c80-430d-916b-dd7e030352b2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267690133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.1267690133
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.130767076
Short name T336
Test name
Test status
Simulation time 175235280300 ps
CPU time 444.11 seconds
Started Jun 05 05:31:15 PM PDT 24
Finished Jun 05 05:38:40 PM PDT 24
Peak memory 201860 kb
Host smart-6435738f-16ff-4db9-8b78-e2ba4c9bff3e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130767076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_
wakeup.130767076
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.3726501320
Short name T32
Test name
Test status
Simulation time 197493748518 ps
CPU time 449.54 seconds
Started Jun 05 05:31:13 PM PDT 24
Finished Jun 05 05:38:43 PM PDT 24
Peak memory 201812 kb
Host smart-7b64bfdd-67be-4a48-8601-0036b2291843
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726501320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.3726501320
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.4132885605
Short name T680
Test name
Test status
Simulation time 108063726084 ps
CPU time 429.14 seconds
Started Jun 05 05:31:12 PM PDT 24
Finished Jun 05 05:38:22 PM PDT 24
Peak memory 202164 kb
Host smart-d70caf66-f8e5-4a17-923c-37915657949f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132885605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.4132885605
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.2800421950
Short name T127
Test name
Test status
Simulation time 33348111014 ps
CPU time 35.7 seconds
Started Jun 05 05:31:15 PM PDT 24
Finished Jun 05 05:31:51 PM PDT 24
Peak memory 201620 kb
Host smart-6408ff13-602d-49d4-888a-252db2aca575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800421950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.2800421950
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.4143562800
Short name T390
Test name
Test status
Simulation time 2878219660 ps
CPU time 3.8 seconds
Started Jun 05 05:31:14 PM PDT 24
Finished Jun 05 05:31:18 PM PDT 24
Peak memory 201596 kb
Host smart-4cdbc484-1ad9-477b-9231-2d0d980bd64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143562800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.4143562800
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.3787371300
Short name T744
Test name
Test status
Simulation time 5949749842 ps
CPU time 7.46 seconds
Started Jun 05 05:31:06 PM PDT 24
Finished Jun 05 05:31:14 PM PDT 24
Peak memory 201628 kb
Host smart-a336d8b2-3277-4400-af70-4ca049eb56b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787371300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.3787371300
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.1282689265
Short name T707
Test name
Test status
Simulation time 202445820452 ps
CPU time 122.99 seconds
Started Jun 05 05:31:14 PM PDT 24
Finished Jun 05 05:33:17 PM PDT 24
Peak memory 210120 kb
Host smart-0811e948-ec3d-4105-81db-aa5fa16663cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282689265 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.1282689265
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.2495055454
Short name T551
Test name
Test status
Simulation time 331146334 ps
CPU time 1.45 seconds
Started Jun 05 05:31:36 PM PDT 24
Finished Jun 05 05:31:38 PM PDT 24
Peak memory 201492 kb
Host smart-b4010ac1-db69-49e0-becb-adeb01836e7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495055454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.2495055454
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.3222470724
Short name T280
Test name
Test status
Simulation time 332001768610 ps
CPU time 63.16 seconds
Started Jun 05 05:31:20 PM PDT 24
Finished Jun 05 05:32:24 PM PDT 24
Peak memory 201792 kb
Host smart-1055a22e-abcb-4918-abea-e62f248a2239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222470724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.3222470724
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.1384039479
Short name T428
Test name
Test status
Simulation time 488127690531 ps
CPU time 610.97 seconds
Started Jun 05 05:31:21 PM PDT 24
Finished Jun 05 05:41:33 PM PDT 24
Peak memory 201972 kb
Host smart-af188f7b-e9bd-4cca-a585-f86dbc187da9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384039479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.1384039479
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.3494554487
Short name T269
Test name
Test status
Simulation time 488929344063 ps
CPU time 1161.28 seconds
Started Jun 05 05:31:23 PM PDT 24
Finished Jun 05 05:50:45 PM PDT 24
Peak memory 201768 kb
Host smart-17ef74e4-4f2f-4d86-b4e0-2eea2f33e8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494554487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.3494554487
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.4059310517
Short name T422
Test name
Test status
Simulation time 165215349257 ps
CPU time 108.66 seconds
Started Jun 05 05:31:19 PM PDT 24
Finished Jun 05 05:33:08 PM PDT 24
Peak memory 201796 kb
Host smart-929a2e33-99e4-4e24-8f93-b67e23c21a5a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059310517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.4059310517
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.1948080812
Short name T557
Test name
Test status
Simulation time 601543211769 ps
CPU time 332.7 seconds
Started Jun 05 05:31:19 PM PDT 24
Finished Jun 05 05:36:52 PM PDT 24
Peak memory 201820 kb
Host smart-e04cd2af-6fb6-4d46-84ea-5dbeca66dc8c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948080812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.1948080812
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.492244963
Short name T712
Test name
Test status
Simulation time 70172406174 ps
CPU time 430.32 seconds
Started Jun 05 05:31:35 PM PDT 24
Finished Jun 05 05:38:46 PM PDT 24
Peak memory 202272 kb
Host smart-4ba5c25a-f25c-451e-a493-d4e0c3481811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492244963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.492244963
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.3457533342
Short name T368
Test name
Test status
Simulation time 24516212388 ps
CPU time 27.64 seconds
Started Jun 05 05:31:30 PM PDT 24
Finished Jun 05 05:31:58 PM PDT 24
Peak memory 201828 kb
Host smart-678febf6-1825-4508-97d7-369d8b10c6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457533342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.3457533342
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.3479901729
Short name T519
Test name
Test status
Simulation time 3051297730 ps
CPU time 2.39 seconds
Started Jun 05 05:31:29 PM PDT 24
Finished Jun 05 05:31:32 PM PDT 24
Peak memory 201624 kb
Host smart-274baa70-7267-4851-afe5-03c5dd35c003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479901729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.3479901729
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.3534584842
Short name T153
Test name
Test status
Simulation time 6048575786 ps
CPU time 4.2 seconds
Started Jun 05 05:31:15 PM PDT 24
Finished Jun 05 05:31:20 PM PDT 24
Peak memory 201612 kb
Host smart-a609ef8a-95a3-4ee1-b3b3-10a86c413c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534584842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.3534584842
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.3147199076
Short name T318
Test name
Test status
Simulation time 250748225094 ps
CPU time 177.25 seconds
Started Jun 05 05:31:35 PM PDT 24
Finished Jun 05 05:34:33 PM PDT 24
Peak memory 201784 kb
Host smart-b9b81fa2-c42b-4230-8dc5-1a2e372d6b29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147199076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.3147199076
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.1086489595
Short name T632
Test name
Test status
Simulation time 25230353194 ps
CPU time 89.86 seconds
Started Jun 05 05:31:36 PM PDT 24
Finished Jun 05 05:33:06 PM PDT 24
Peak memory 210484 kb
Host smart-c244c9bd-66f7-4f99-a0ec-cc0c69c7373e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086489595 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.1086489595
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.3694084594
Short name T29
Test name
Test status
Simulation time 449163011 ps
CPU time 0.78 seconds
Started Jun 05 05:31:49 PM PDT 24
Finished Jun 05 05:31:50 PM PDT 24
Peak memory 201504 kb
Host smart-df1b9c35-2ef4-4da8-913b-5288bf62b445
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694084594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.3694084594
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.2643729603
Short name T625
Test name
Test status
Simulation time 161814662084 ps
CPU time 365.52 seconds
Started Jun 05 05:31:48 PM PDT 24
Finished Jun 05 05:37:55 PM PDT 24
Peak memory 201796 kb
Host smart-50642f26-0dcf-4731-a294-c86e0aaaa1c4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643729603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.2643729603
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.741442253
Short name T321
Test name
Test status
Simulation time 266906802483 ps
CPU time 167.1 seconds
Started Jun 05 05:31:49 PM PDT 24
Finished Jun 05 05:34:37 PM PDT 24
Peak memory 201884 kb
Host smart-a5db7a67-a69f-49ba-bed8-763a8033e4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741442253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.741442253
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.3806084498
Short name T671
Test name
Test status
Simulation time 166358158366 ps
CPU time 203.82 seconds
Started Jun 05 05:31:36 PM PDT 24
Finished Jun 05 05:35:00 PM PDT 24
Peak memory 201820 kb
Host smart-3057932d-1b6b-45bc-9281-9bfd4bcebc08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806084498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.3806084498
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.1263093821
Short name T504
Test name
Test status
Simulation time 331333447810 ps
CPU time 191.24 seconds
Started Jun 05 05:31:33 PM PDT 24
Finished Jun 05 05:34:45 PM PDT 24
Peak memory 201808 kb
Host smart-753050db-2f6b-43e4-9f05-e1c3ae77f0da
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263093821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.1263093821
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.20250256
Short name T617
Test name
Test status
Simulation time 168852716741 ps
CPU time 103.55 seconds
Started Jun 05 05:31:37 PM PDT 24
Finished Jun 05 05:33:21 PM PDT 24
Peak memory 201788 kb
Host smart-ba95985c-aa4e-48fd-b5e9-d81d9db91b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20250256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.20250256
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.1533258090
Short name T452
Test name
Test status
Simulation time 501848606061 ps
CPU time 1192.92 seconds
Started Jun 05 05:31:35 PM PDT 24
Finished Jun 05 05:51:29 PM PDT 24
Peak memory 201992 kb
Host smart-cada9ee3-03e0-4c4f-b1e7-89db67983819
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533258090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.1533258090
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.3313550966
Short name T90
Test name
Test status
Simulation time 178383733517 ps
CPU time 424.41 seconds
Started Jun 05 05:31:48 PM PDT 24
Finished Jun 05 05:38:53 PM PDT 24
Peak memory 201896 kb
Host smart-88af6e02-8835-4de4-9f84-4ede81367dd8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313550966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.3313550966
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.1877147085
Short name T461
Test name
Test status
Simulation time 392714911889 ps
CPU time 464.81 seconds
Started Jun 05 05:31:49 PM PDT 24
Finished Jun 05 05:39:34 PM PDT 24
Peak memory 201872 kb
Host smart-7bab24f7-d825-4409-9155-080ec594a852
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877147085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.1877147085
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.3592529923
Short name T683
Test name
Test status
Simulation time 113086208220 ps
CPU time 588.99 seconds
Started Jun 05 05:31:49 PM PDT 24
Finished Jun 05 05:41:39 PM PDT 24
Peak memory 202072 kb
Host smart-9cbc7bb4-cac1-4d28-94af-d2f88347233c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592529923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.3592529923
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.746404892
Short name T10
Test name
Test status
Simulation time 45223529469 ps
CPU time 107.49 seconds
Started Jun 05 05:31:48 PM PDT 24
Finished Jun 05 05:33:36 PM PDT 24
Peak memory 201624 kb
Host smart-defea051-c81f-4542-b553-b34441a72903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746404892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.746404892
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.4199996073
Short name T727
Test name
Test status
Simulation time 4355254501 ps
CPU time 3.2 seconds
Started Jun 05 05:31:48 PM PDT 24
Finished Jun 05 05:31:52 PM PDT 24
Peak memory 201568 kb
Host smart-d6f8ad1a-1355-4bc7-8baa-20155f7f3ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199996073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.4199996073
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.3808791851
Short name T790
Test name
Test status
Simulation time 6008366034 ps
CPU time 4.2 seconds
Started Jun 05 05:31:32 PM PDT 24
Finished Jun 05 05:31:37 PM PDT 24
Peak memory 201636 kb
Host smart-db1215df-b1a2-47fa-b19b-8bc564be4311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808791851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.3808791851
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.3483392811
Short name T37
Test name
Test status
Simulation time 226268338922 ps
CPU time 1235.37 seconds
Started Jun 05 05:31:49 PM PDT 24
Finished Jun 05 05:52:25 PM PDT 24
Peak memory 211116 kb
Host smart-c18834bd-dfa8-4f81-9088-c02cfb1ac8bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483392811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.3483392811
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.1141331960
Short name T119
Test name
Test status
Simulation time 55028627365 ps
CPU time 127.7 seconds
Started Jun 05 05:31:48 PM PDT 24
Finished Jun 05 05:33:56 PM PDT 24
Peak memory 210172 kb
Host smart-13948288-3bba-43cb-9f0b-63f189cf95aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141331960 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.1141331960
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.1664495030
Short name T402
Test name
Test status
Simulation time 331949883 ps
CPU time 1.41 seconds
Started Jun 05 05:31:55 PM PDT 24
Finished Jun 05 05:31:57 PM PDT 24
Peak memory 201492 kb
Host smart-88d0e6da-1c66-44fa-a1d2-1451098b9cef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664495030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.1664495030
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.1314130621
Short name T332
Test name
Test status
Simulation time 409697534351 ps
CPU time 439.42 seconds
Started Jun 05 05:31:50 PM PDT 24
Finished Jun 05 05:39:10 PM PDT 24
Peak memory 201816 kb
Host smart-3252b7fe-ff4b-4b0d-89f1-2be7a0a3d566
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314130621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.1314130621
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.2286073535
Short name T334
Test name
Test status
Simulation time 160220511408 ps
CPU time 35.96 seconds
Started Jun 05 05:31:50 PM PDT 24
Finished Jun 05 05:32:26 PM PDT 24
Peak memory 201796 kb
Host smart-d324a492-c648-42c7-95cd-bd1218f716c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286073535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.2286073535
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.325871037
Short name T165
Test name
Test status
Simulation time 158638829326 ps
CPU time 358.67 seconds
Started Jun 05 05:31:52 PM PDT 24
Finished Jun 05 05:37:52 PM PDT 24
Peak memory 201816 kb
Host smart-96ad4a2d-9566-400a-ab0f-9ba93ed0ee2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325871037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.325871037
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.3148916266
Short name T717
Test name
Test status
Simulation time 488474311270 ps
CPU time 1227.95 seconds
Started Jun 05 05:31:51 PM PDT 24
Finished Jun 05 05:52:20 PM PDT 24
Peak memory 201788 kb
Host smart-09b62bcb-03e2-4fb3-bd65-5caf4046724e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148916266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.3148916266
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.2617341364
Short name T13
Test name
Test status
Simulation time 326432553943 ps
CPU time 796.02 seconds
Started Jun 05 05:31:51 PM PDT 24
Finished Jun 05 05:45:08 PM PDT 24
Peak memory 201856 kb
Host smart-1284b533-d97f-48e2-8a10-ed77d230288a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617341364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.2617341364
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.2233714789
Short name T658
Test name
Test status
Simulation time 484509117913 ps
CPU time 1057.68 seconds
Started Jun 05 05:31:49 PM PDT 24
Finished Jun 05 05:49:27 PM PDT 24
Peak memory 201780 kb
Host smart-62199c0c-ba3b-4918-a6e2-e423b6983616
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233714789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.2233714789
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.378526446
Short name T601
Test name
Test status
Simulation time 345014746810 ps
CPU time 819.61 seconds
Started Jun 05 05:31:52 PM PDT 24
Finished Jun 05 05:45:33 PM PDT 24
Peak memory 201832 kb
Host smart-3c744eca-920c-4055-911b-bed69ca100ab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378526446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_
wakeup.378526446
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.1978381694
Short name T517
Test name
Test status
Simulation time 197983826153 ps
CPU time 123.07 seconds
Started Jun 05 05:31:52 PM PDT 24
Finished Jun 05 05:33:55 PM PDT 24
Peak memory 201760 kb
Host smart-f50f0889-6e0d-4b10-9694-f1878985fea2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978381694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.1978381694
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.920543173
Short name T450
Test name
Test status
Simulation time 111619121196 ps
CPU time 465.71 seconds
Started Jun 05 05:31:50 PM PDT 24
Finished Jun 05 05:39:36 PM PDT 24
Peak memory 202084 kb
Host smart-7648bd8f-60e5-468e-81d9-29a7fd0ae4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920543173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.920543173
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.2904973757
Short name T687
Test name
Test status
Simulation time 40548690083 ps
CPU time 12.43 seconds
Started Jun 05 05:31:51 PM PDT 24
Finished Jun 05 05:32:04 PM PDT 24
Peak memory 201640 kb
Host smart-4275bc22-4ae2-4d85-8cfd-b72c4d5cf9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904973757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.2904973757
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.10006953
Short name T426
Test name
Test status
Simulation time 3600449447 ps
CPU time 1.86 seconds
Started Jun 05 05:31:51 PM PDT 24
Finished Jun 05 05:31:54 PM PDT 24
Peak memory 201636 kb
Host smart-8e71f68c-e78f-4715-92d3-b465e718e5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10006953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.10006953
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.692370237
Short name T770
Test name
Test status
Simulation time 6124673675 ps
CPU time 14.85 seconds
Started Jun 05 05:31:49 PM PDT 24
Finished Jun 05 05:32:05 PM PDT 24
Peak memory 201640 kb
Host smart-16990fda-418b-4deb-989b-b9fd10225e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692370237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.692370237
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.858062840
Short name T167
Test name
Test status
Simulation time 419544442432 ps
CPU time 179.97 seconds
Started Jun 05 05:31:58 PM PDT 24
Finished Jun 05 05:34:58 PM PDT 24
Peak memory 201828 kb
Host smart-7141d971-94e2-490e-9953-9dd46314ff25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858062840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all.
858062840
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.2573020676
Short name T605
Test name
Test status
Simulation time 513480819 ps
CPU time 1.83 seconds
Started Jun 05 05:32:13 PM PDT 24
Finished Jun 05 05:32:15 PM PDT 24
Peak memory 201488 kb
Host smart-e4fcedd4-b732-4461-a691-209bcd1f08a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573020676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.2573020676
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.4106331303
Short name T274
Test name
Test status
Simulation time 494815002008 ps
CPU time 620.7 seconds
Started Jun 05 05:31:57 PM PDT 24
Finished Jun 05 05:42:18 PM PDT 24
Peak memory 201788 kb
Host smart-dc50c35b-d1f4-4607-9ebc-bbf3993e069d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106331303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.4106331303
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.3792467616
Short name T788
Test name
Test status
Simulation time 328297681248 ps
CPU time 386.46 seconds
Started Jun 05 05:32:04 PM PDT 24
Finished Jun 05 05:38:31 PM PDT 24
Peak memory 201804 kb
Host smart-3dcc85f1-6939-49d4-b070-ff8a945709b8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792467616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.3792467616
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.2700351112
Short name T227
Test name
Test status
Simulation time 164569929503 ps
CPU time 415.89 seconds
Started Jun 05 05:31:56 PM PDT 24
Finished Jun 05 05:38:53 PM PDT 24
Peak memory 201864 kb
Host smart-93441371-eedd-4e8c-b4bd-3e01b34286ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700351112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.2700351112
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.69747493
Short name T524
Test name
Test status
Simulation time 488646960201 ps
CPU time 1175.92 seconds
Started Jun 05 05:31:57 PM PDT 24
Finished Jun 05 05:51:33 PM PDT 24
Peak memory 201892 kb
Host smart-30173491-e5a8-44d2-b782-df363fdfa4ef
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=69747493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fixed
.69747493
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.1491534115
Short name T626
Test name
Test status
Simulation time 388077969752 ps
CPU time 956.45 seconds
Started Jun 05 05:32:04 PM PDT 24
Finished Jun 05 05:48:01 PM PDT 24
Peak memory 201804 kb
Host smart-657ae6a0-7aaa-4de2-80f8-e8f63dcfeee4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491534115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.1491534115
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.1102841623
Short name T42
Test name
Test status
Simulation time 100586207196 ps
CPU time 498.8 seconds
Started Jun 05 05:32:02 PM PDT 24
Finished Jun 05 05:40:21 PM PDT 24
Peak memory 202176 kb
Host smart-f7f98a6b-d71a-4886-b9c5-c709e3cbab79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102841623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.1102841623
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.3101083009
Short name T112
Test name
Test status
Simulation time 27040369545 ps
CPU time 14.14 seconds
Started Jun 05 05:32:04 PM PDT 24
Finished Jun 05 05:32:18 PM PDT 24
Peak memory 201568 kb
Host smart-a5dac051-c1e2-4f1d-8b6a-6677209e90e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101083009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.3101083009
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.3034719979
Short name T103
Test name
Test status
Simulation time 4877106918 ps
CPU time 11.91 seconds
Started Jun 05 05:32:05 PM PDT 24
Finished Jun 05 05:32:18 PM PDT 24
Peak memory 201624 kb
Host smart-dd1c6c4c-c14f-439e-9783-1c28ccd474bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034719979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.3034719979
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.2044664147
Short name T631
Test name
Test status
Simulation time 5642409698 ps
CPU time 10.83 seconds
Started Jun 05 05:31:58 PM PDT 24
Finished Jun 05 05:32:10 PM PDT 24
Peak memory 201616 kb
Host smart-518459ed-b18c-4605-8f83-c92435f66fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044664147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.2044664147
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.2048285240
Short name T367
Test name
Test status
Simulation time 159790210311 ps
CPU time 414.77 seconds
Started Jun 05 05:32:03 PM PDT 24
Finished Jun 05 05:38:58 PM PDT 24
Peak memory 211328 kb
Host smart-133eb2e7-2c5c-408a-8598-f6a450e40fdb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048285240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.2048285240
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.401408789
Short name T89
Test name
Test status
Simulation time 108290835171 ps
CPU time 64.02 seconds
Started Jun 05 05:32:03 PM PDT 24
Finished Jun 05 05:33:08 PM PDT 24
Peak memory 210116 kb
Host smart-50823907-42cf-4f6d-bc7e-b54aba73066e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401408789 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.401408789
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.1449661985
Short name T679
Test name
Test status
Simulation time 453104113 ps
CPU time 0.92 seconds
Started Jun 05 05:32:18 PM PDT 24
Finished Jun 05 05:32:19 PM PDT 24
Peak memory 201504 kb
Host smart-b6ed8a5c-4600-4775-94d6-850f7d218791
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449661985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.1449661985
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.462045567
Short name T750
Test name
Test status
Simulation time 171961322283 ps
CPU time 184.41 seconds
Started Jun 05 05:32:12 PM PDT 24
Finished Jun 05 05:35:16 PM PDT 24
Peak memory 201780 kb
Host smart-0d93cb73-8c60-4ce6-a4a7-b2fb9a215d44
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462045567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gati
ng.462045567
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.3374516046
Short name T120
Test name
Test status
Simulation time 499102543936 ps
CPU time 337.3 seconds
Started Jun 05 05:32:11 PM PDT 24
Finished Jun 05 05:37:49 PM PDT 24
Peak memory 201792 kb
Host smart-4af31e8f-2de1-41d5-9510-dceafecc2831
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374516046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.3374516046
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.3231837964
Short name T159
Test name
Test status
Simulation time 164353906723 ps
CPU time 376.97 seconds
Started Jun 05 05:32:12 PM PDT 24
Finished Jun 05 05:38:29 PM PDT 24
Peak memory 201860 kb
Host smart-aeb911e8-2982-4a02-977a-b52981435598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231837964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.3231837964
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.3936815408
Short name T476
Test name
Test status
Simulation time 497846298210 ps
CPU time 1081.5 seconds
Started Jun 05 05:32:12 PM PDT 24
Finished Jun 05 05:50:14 PM PDT 24
Peak memory 201736 kb
Host smart-313f9db4-6699-407a-a931-ebb4c5006a32
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936815408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.3936815408
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.855997579
Short name T305
Test name
Test status
Simulation time 372672429570 ps
CPU time 833.09 seconds
Started Jun 05 05:32:12 PM PDT 24
Finished Jun 05 05:46:05 PM PDT 24
Peak memory 201792 kb
Host smart-38cdd46e-b37f-4b68-a49a-f043e8f37a36
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855997579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_
wakeup.855997579
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.833612624
Short name T737
Test name
Test status
Simulation time 405420215284 ps
CPU time 473.38 seconds
Started Jun 05 05:32:11 PM PDT 24
Finished Jun 05 05:40:04 PM PDT 24
Peak memory 201820 kb
Host smart-70ef844f-16d1-48e3-9179-7738d7f69a9f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833612624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
adc_ctrl_filters_wakeup_fixed.833612624
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.3716536995
Short name T360
Test name
Test status
Simulation time 149101358509 ps
CPU time 704.35 seconds
Started Jun 05 05:32:12 PM PDT 24
Finished Jun 05 05:43:57 PM PDT 24
Peak memory 202176 kb
Host smart-15f58142-ef8a-4aee-94ce-370ebfa7eeb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716536995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.3716536995
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.2275854167
Short name T104
Test name
Test status
Simulation time 45699277233 ps
CPU time 16.78 seconds
Started Jun 05 05:32:12 PM PDT 24
Finished Jun 05 05:32:29 PM PDT 24
Peak memory 201632 kb
Host smart-261af989-75ea-457b-b07c-4d8495cb884d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275854167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.2275854167
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.1371753112
Short name T435
Test name
Test status
Simulation time 4297042056 ps
CPU time 10.68 seconds
Started Jun 05 05:32:11 PM PDT 24
Finished Jun 05 05:32:22 PM PDT 24
Peak memory 201548 kb
Host smart-ea11323f-ad59-4f42-a7d5-d5b99691151c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371753112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.1371753112
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.3223427099
Short name T523
Test name
Test status
Simulation time 6003617065 ps
CPU time 4.16 seconds
Started Jun 05 05:32:10 PM PDT 24
Finished Jun 05 05:32:15 PM PDT 24
Peak memory 201640 kb
Host smart-77423cb7-1669-4862-974c-27d0f3a33c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223427099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.3223427099
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.3063996910
Short name T417
Test name
Test status
Simulation time 433000122 ps
CPU time 1.28 seconds
Started Jun 05 05:32:25 PM PDT 24
Finished Jun 05 05:32:26 PM PDT 24
Peak memory 201504 kb
Host smart-6ec45d9a-e3e6-4010-a521-8ed7dd39bb8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063996910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.3063996910
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.2074253779
Short name T306
Test name
Test status
Simulation time 345854091902 ps
CPU time 741.49 seconds
Started Jun 05 05:32:23 PM PDT 24
Finished Jun 05 05:44:45 PM PDT 24
Peak memory 201868 kb
Host smart-c212982e-7705-4d02-beb4-9e5fcb25025a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074253779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.2074253779
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.3895256657
Short name T259
Test name
Test status
Simulation time 481531938453 ps
CPU time 1128.38 seconds
Started Jun 05 05:32:17 PM PDT 24
Finished Jun 05 05:51:06 PM PDT 24
Peak memory 201852 kb
Host smart-3346d269-1a2d-4043-bedf-2476131a8f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895256657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.3895256657
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.1178101696
Short name T187
Test name
Test status
Simulation time 496717176738 ps
CPU time 263.4 seconds
Started Jun 05 05:32:19 PM PDT 24
Finished Jun 05 05:36:43 PM PDT 24
Peak memory 201796 kb
Host smart-b838121d-5d0f-4784-9509-5cda49fc41b8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178101696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.1178101696
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.2095934895
Short name T611
Test name
Test status
Simulation time 329386690065 ps
CPU time 778.97 seconds
Started Jun 05 05:32:18 PM PDT 24
Finished Jun 05 05:45:18 PM PDT 24
Peak memory 201792 kb
Host smart-ad23a1d2-938d-45a2-95e9-bea69f8115d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095934895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.2095934895
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.1151175013
Short name T581
Test name
Test status
Simulation time 491629245624 ps
CPU time 305.81 seconds
Started Jun 05 05:32:17 PM PDT 24
Finished Jun 05 05:37:24 PM PDT 24
Peak memory 201764 kb
Host smart-ec285585-1b8c-4baf-9324-f46c4b390534
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151175013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.1151175013
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.1264810611
Short name T199
Test name
Test status
Simulation time 372219907998 ps
CPU time 69.4 seconds
Started Jun 05 05:32:19 PM PDT 24
Finished Jun 05 05:33:29 PM PDT 24
Peak memory 201812 kb
Host smart-bb6b526b-718a-4b1d-895f-520b6a3f9afb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264810611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.1264810611
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.2989007878
Short name T111
Test name
Test status
Simulation time 631843323377 ps
CPU time 279.11 seconds
Started Jun 05 05:32:19 PM PDT 24
Finished Jun 05 05:36:58 PM PDT 24
Peak memory 201888 kb
Host smart-802fd0cc-ceb6-40e9-9303-9f08d1162ebb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989007878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.2989007878
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.3648823512
Short name T596
Test name
Test status
Simulation time 29203408002 ps
CPU time 33.34 seconds
Started Jun 05 05:32:26 PM PDT 24
Finished Jun 05 05:33:00 PM PDT 24
Peak memory 201604 kb
Host smart-5ac47665-abdc-45e7-bb85-4d8d4a9ccf75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648823512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.3648823512
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.3914855056
Short name T705
Test name
Test status
Simulation time 4432060537 ps
CPU time 1.82 seconds
Started Jun 05 05:32:26 PM PDT 24
Finished Jun 05 05:32:28 PM PDT 24
Peak memory 201616 kb
Host smart-45740cba-c3c4-4da5-8e81-1724e52ea976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914855056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.3914855056
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.1348540835
Short name T763
Test name
Test status
Simulation time 5698179638 ps
CPU time 8.09 seconds
Started Jun 05 05:32:18 PM PDT 24
Finished Jun 05 05:32:27 PM PDT 24
Peak memory 201612 kb
Host smart-4ee5ac3f-8245-4bde-84dd-d07a5229e076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348540835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.1348540835
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.4113321936
Short name T41
Test name
Test status
Simulation time 26132544873 ps
CPU time 62.39 seconds
Started Jun 05 05:32:26 PM PDT 24
Finished Jun 05 05:33:29 PM PDT 24
Peak memory 210164 kb
Host smart-324d5c65-6e5a-4b6c-871a-8fee5e6d216e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113321936 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.4113321936
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.1108062028
Short name T78
Test name
Test status
Simulation time 518914130 ps
CPU time 0.89 seconds
Started Jun 05 05:32:40 PM PDT 24
Finished Jun 05 05:32:41 PM PDT 24
Peak memory 201484 kb
Host smart-771b9877-7ece-4a4d-ae53-dcccfbf252bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108062028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.1108062028
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.855050197
Short name T169
Test name
Test status
Simulation time 327308302139 ps
CPU time 154.59 seconds
Started Jun 05 05:32:34 PM PDT 24
Finished Jun 05 05:35:09 PM PDT 24
Peak memory 201896 kb
Host smart-fce0a971-dc4f-4cd0-afb0-79967f5eab14
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855050197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gati
ng.855050197
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.3822644434
Short name T685
Test name
Test status
Simulation time 170086175710 ps
CPU time 389.62 seconds
Started Jun 05 05:32:35 PM PDT 24
Finished Jun 05 05:39:05 PM PDT 24
Peak memory 201788 kb
Host smart-7d3d00a8-f157-451f-9b3b-8e47c578c866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822644434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.3822644434
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.479740386
Short name T312
Test name
Test status
Simulation time 320733961632 ps
CPU time 789.76 seconds
Started Jun 05 05:32:25 PM PDT 24
Finished Jun 05 05:45:35 PM PDT 24
Peak memory 201800 kb
Host smart-ce67c213-f283-481a-8fed-c1dcc0701e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479740386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.479740386
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.4092487112
Short name T792
Test name
Test status
Simulation time 325259416974 ps
CPU time 200.86 seconds
Started Jun 05 05:32:33 PM PDT 24
Finished Jun 05 05:35:54 PM PDT 24
Peak memory 201820 kb
Host smart-4528fa04-687e-4d4a-92a6-980db7694183
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092487112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.4092487112
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.1040069815
Short name T330
Test name
Test status
Simulation time 487679808583 ps
CPU time 1102.23 seconds
Started Jun 05 05:32:27 PM PDT 24
Finished Jun 05 05:50:50 PM PDT 24
Peak memory 201856 kb
Host smart-87a7eee2-2d5e-4daf-b7b1-fecf9bfa9d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040069815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.1040069815
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.3067166499
Short name T446
Test name
Test status
Simulation time 162855310425 ps
CPU time 384.11 seconds
Started Jun 05 05:32:25 PM PDT 24
Finished Jun 05 05:38:50 PM PDT 24
Peak memory 201788 kb
Host smart-8eeb9b80-54b6-4d4d-b8a3-5ea2282a9bae
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067166499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.3067166499
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.2041919613
Short name T644
Test name
Test status
Simulation time 208004661185 ps
CPU time 130.72 seconds
Started Jun 05 05:32:33 PM PDT 24
Finished Jun 05 05:34:45 PM PDT 24
Peak memory 201816 kb
Host smart-5a281076-9cc3-4d86-aa4e-d0b2d9c7862d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041919613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.2041919613
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.3783578393
Short name T429
Test name
Test status
Simulation time 207411301782 ps
CPU time 119.67 seconds
Started Jun 05 05:32:34 PM PDT 24
Finished Jun 05 05:34:34 PM PDT 24
Peak memory 201796 kb
Host smart-0e111a42-e32a-4dba-8be6-41ff4b688dd9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783578393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.3783578393
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.135481670
Short name T753
Test name
Test status
Simulation time 113370938695 ps
CPU time 495 seconds
Started Jun 05 05:32:34 PM PDT 24
Finished Jun 05 05:40:49 PM PDT 24
Peak memory 202048 kb
Host smart-73114f32-9377-462f-af8e-7930d4da4a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135481670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.135481670
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.1062692570
Short name T661
Test name
Test status
Simulation time 39290595875 ps
CPU time 43.74 seconds
Started Jun 05 05:32:33 PM PDT 24
Finished Jun 05 05:33:18 PM PDT 24
Peak memory 201624 kb
Host smart-806b67ce-fe6c-4e97-918b-1ed60227a4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062692570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.1062692570
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.1595006088
Short name T742
Test name
Test status
Simulation time 4107749335 ps
CPU time 2.99 seconds
Started Jun 05 05:32:33 PM PDT 24
Finished Jun 05 05:32:36 PM PDT 24
Peak memory 201620 kb
Host smart-8279b0be-e3ff-4b0e-a494-814eec46cb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595006088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.1595006088
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.1571394402
Short name T634
Test name
Test status
Simulation time 5843507472 ps
CPU time 4.11 seconds
Started Jun 05 05:32:25 PM PDT 24
Finished Jun 05 05:32:29 PM PDT 24
Peak memory 201640 kb
Host smart-1a57ad4b-34aa-474f-a8f1-a5bbaf1e7ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571394402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.1571394402
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.3175211532
Short name T716
Test name
Test status
Simulation time 79187494937 ps
CPU time 196.15 seconds
Started Jun 05 05:32:43 PM PDT 24
Finished Jun 05 05:36:00 PM PDT 24
Peak memory 201628 kb
Host smart-ef651e46-dc6d-491b-9dc0-c0d700d254c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175211532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.3175211532
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.3679834897
Short name T101
Test name
Test status
Simulation time 354393835 ps
CPU time 0.81 seconds
Started Jun 05 05:32:53 PM PDT 24
Finished Jun 05 05:32:55 PM PDT 24
Peak memory 201520 kb
Host smart-614d5e2a-1083-4849-aa11-0658313d0691
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679834897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.3679834897
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.2472573029
Short name T93
Test name
Test status
Simulation time 530651201385 ps
CPU time 1208.97 seconds
Started Jun 05 05:32:48 PM PDT 24
Finished Jun 05 05:52:58 PM PDT 24
Peak memory 201796 kb
Host smart-af82936d-1d12-42a7-9c04-a8638b3099be
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472573029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.2472573029
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.2468232125
Short name T117
Test name
Test status
Simulation time 164067156803 ps
CPU time 367.87 seconds
Started Jun 05 05:32:50 PM PDT 24
Finished Jun 05 05:38:58 PM PDT 24
Peak memory 201808 kb
Host smart-e65afba0-a062-4ef2-8a43-4eca11a3ee99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468232125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.2468232125
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.2033170094
Short name T182
Test name
Test status
Simulation time 327183697395 ps
CPU time 138.13 seconds
Started Jun 05 05:32:41 PM PDT 24
Finished Jun 05 05:35:00 PM PDT 24
Peak memory 201888 kb
Host smart-baa6a5f2-e857-483e-9059-c9873d6fe34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033170094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.2033170094
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.1875865206
Short name T385
Test name
Test status
Simulation time 165439852833 ps
CPU time 414.29 seconds
Started Jun 05 05:32:42 PM PDT 24
Finished Jun 05 05:39:36 PM PDT 24
Peak memory 201824 kb
Host smart-ae57cb1d-833c-4bfe-b5e2-b16a901e70c0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875865206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.1875865206
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.1570853836
Short name T412
Test name
Test status
Simulation time 329137520408 ps
CPU time 405.02 seconds
Started Jun 05 05:32:42 PM PDT 24
Finished Jun 05 05:39:28 PM PDT 24
Peak memory 201788 kb
Host smart-3eaa1b08-d42c-4bc0-9227-4a1a8d2ed494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570853836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.1570853836
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.3219147833
Short name T569
Test name
Test status
Simulation time 161780461617 ps
CPU time 158.72 seconds
Started Jun 05 05:32:41 PM PDT 24
Finished Jun 05 05:35:20 PM PDT 24
Peak memory 201764 kb
Host smart-453c0c9c-2b3f-4a67-a313-2b6d9fae2c4b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219147833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.3219147833
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.3424726773
Short name T172
Test name
Test status
Simulation time 538910243026 ps
CPU time 321 seconds
Started Jun 05 05:32:42 PM PDT 24
Finished Jun 05 05:38:04 PM PDT 24
Peak memory 201812 kb
Host smart-30f335ee-e51e-4e70-b989-a9dcf1529325
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424726773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.3424726773
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.1595287599
Short name T451
Test name
Test status
Simulation time 409284339300 ps
CPU time 220.99 seconds
Started Jun 05 05:32:42 PM PDT 24
Finished Jun 05 05:36:24 PM PDT 24
Peak memory 201828 kb
Host smart-5787ba2b-46fb-4ae0-82b4-f160c96282a1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595287599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.1595287599
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.3754681039
Short name T593
Test name
Test status
Simulation time 117237976910 ps
CPU time 493.76 seconds
Started Jun 05 05:32:48 PM PDT 24
Finished Jun 05 05:41:03 PM PDT 24
Peak memory 202116 kb
Host smart-c1eff2ba-0f86-48da-9836-7de02608d36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754681039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.3754681039
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.1324966734
Short name T373
Test name
Test status
Simulation time 27651650782 ps
CPU time 30.78 seconds
Started Jun 05 05:32:48 PM PDT 24
Finished Jun 05 05:33:19 PM PDT 24
Peak memory 201632 kb
Host smart-e0b02cf9-f0f6-485e-ac6f-0d3bfd5550a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324966734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.1324966734
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.1614109591
Short name T545
Test name
Test status
Simulation time 2937985528 ps
CPU time 2.52 seconds
Started Jun 05 05:32:47 PM PDT 24
Finished Jun 05 05:32:50 PM PDT 24
Peak memory 201628 kb
Host smart-0d9d555b-6a1f-46ca-82e1-b216f1d6e550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614109591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.1614109591
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.2657234585
Short name T527
Test name
Test status
Simulation time 5708491224 ps
CPU time 8.13 seconds
Started Jun 05 05:32:42 PM PDT 24
Finished Jun 05 05:32:51 PM PDT 24
Peak memory 201660 kb
Host smart-48435da4-65c7-48a1-a432-112800326691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657234585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.2657234585
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.3035449680
Short name T242
Test name
Test status
Simulation time 185938222555 ps
CPU time 111.82 seconds
Started Jun 05 05:32:49 PM PDT 24
Finished Jun 05 05:34:41 PM PDT 24
Peak memory 201992 kb
Host smart-5c7c8109-0898-4f87-9c40-c4dd546bee2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035449680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.3035449680
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.3226863097
Short name T562
Test name
Test status
Simulation time 523738259 ps
CPU time 1.31 seconds
Started Jun 05 05:25:48 PM PDT 24
Finished Jun 05 05:25:50 PM PDT 24
Peak memory 201488 kb
Host smart-4220d614-b2ef-4649-b187-b1510acec011
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226863097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.3226863097
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.1006257233
Short name T548
Test name
Test status
Simulation time 188203276930 ps
CPU time 102.91 seconds
Started Jun 05 05:25:50 PM PDT 24
Finished Jun 05 05:27:34 PM PDT 24
Peak memory 201808 kb
Host smart-28aaed3d-4799-4830-bf3c-de2ddc093c9d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006257233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.1006257233
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.2914648856
Short name T168
Test name
Test status
Simulation time 354334730968 ps
CPU time 216.21 seconds
Started Jun 05 05:25:54 PM PDT 24
Finished Jun 05 05:29:30 PM PDT 24
Peak memory 201776 kb
Host smart-37fc9a42-f17b-4835-ab21-20a14500139e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914648856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.2914648856
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.1084211181
Short name T591
Test name
Test status
Simulation time 486950020360 ps
CPU time 148.62 seconds
Started Jun 05 05:25:44 PM PDT 24
Finished Jun 05 05:28:13 PM PDT 24
Peak memory 201800 kb
Host smart-b40975e5-5749-43d8-85ce-fb79c47b19f6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084211181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.1084211181
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.1198529719
Short name T686
Test name
Test status
Simulation time 160513086752 ps
CPU time 23.57 seconds
Started Jun 05 05:25:45 PM PDT 24
Finished Jun 05 05:26:09 PM PDT 24
Peak memory 201868 kb
Host smart-09f42bd9-21b0-401b-9df6-3b3cb97c95c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198529719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.1198529719
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.3716626601
Short name T703
Test name
Test status
Simulation time 332022644659 ps
CPU time 830.97 seconds
Started Jun 05 05:25:44 PM PDT 24
Finished Jun 05 05:39:35 PM PDT 24
Peak memory 201808 kb
Host smart-e9cb2d77-6f42-4167-ac21-b99753ffc9ba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716626601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.3716626601
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.2591935693
Short name T221
Test name
Test status
Simulation time 201928632635 ps
CPU time 250.57 seconds
Started Jun 05 05:25:50 PM PDT 24
Finished Jun 05 05:30:02 PM PDT 24
Peak memory 201804 kb
Host smart-3b2842fc-1444-4416-99b2-d090dff5529c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591935693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.2591935693
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.4214466280
Short name T702
Test name
Test status
Simulation time 118221186987 ps
CPU time 448.59 seconds
Started Jun 05 05:25:51 PM PDT 24
Finished Jun 05 05:33:21 PM PDT 24
Peak memory 202316 kb
Host smart-d3af9ced-a4ab-488b-9733-6b8ecfe18115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214466280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.4214466280
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.3591030202
Short name T388
Test name
Test status
Simulation time 38564200026 ps
CPU time 95.71 seconds
Started Jun 05 05:25:51 PM PDT 24
Finished Jun 05 05:27:27 PM PDT 24
Peak memory 201564 kb
Host smart-0b74479c-07ba-455a-a132-d6c00cef3cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591030202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.3591030202
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.2896193754
Short name T411
Test name
Test status
Simulation time 3165643214 ps
CPU time 2.35 seconds
Started Jun 05 05:25:53 PM PDT 24
Finished Jun 05 05:25:56 PM PDT 24
Peak memory 201644 kb
Host smart-3dc978f8-a18e-46be-9c9d-0cbea7aea770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896193754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.2896193754
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.1018204424
Short name T4
Test name
Test status
Simulation time 5771104675 ps
CPU time 8.03 seconds
Started Jun 05 05:25:45 PM PDT 24
Finished Jun 05 05:25:54 PM PDT 24
Peak memory 201640 kb
Host smart-cb8390e5-f5ee-4f2b-bba1-b2790ab27985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018204424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.1018204424
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.2016924692
Short name T324
Test name
Test status
Simulation time 167406065559 ps
CPU time 117.97 seconds
Started Jun 05 05:25:51 PM PDT 24
Finished Jun 05 05:27:50 PM PDT 24
Peak memory 201968 kb
Host smart-b95abf0f-ad87-4ad7-8c20-094e784887a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016924692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
2016924692
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.2415340270
Short name T97
Test name
Test status
Simulation time 352306197101 ps
CPU time 492.61 seconds
Started Jun 05 05:25:59 PM PDT 24
Finished Jun 05 05:34:13 PM PDT 24
Peak memory 210424 kb
Host smart-380ab8ea-68fe-443b-8f88-022e375688ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415340270 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.2415340270
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.536910553
Short name T424
Test name
Test status
Simulation time 416485575 ps
CPU time 1.65 seconds
Started Jun 05 05:25:52 PM PDT 24
Finished Jun 05 05:25:54 PM PDT 24
Peak memory 201524 kb
Host smart-eb5c5c2b-6a5a-4e4a-b0c5-2acf47141dee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536910553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.536910553
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.1221103125
Short name T553
Test name
Test status
Simulation time 336273337878 ps
CPU time 353.63 seconds
Started Jun 05 05:25:51 PM PDT 24
Finished Jun 05 05:31:45 PM PDT 24
Peak memory 201808 kb
Host smart-308b3604-8859-4055-b892-6a217a5db3e8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221103125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.1221103125
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.4120493559
Short name T285
Test name
Test status
Simulation time 590200420961 ps
CPU time 410.16 seconds
Started Jun 05 05:25:52 PM PDT 24
Finished Jun 05 05:32:42 PM PDT 24
Peak memory 201792 kb
Host smart-e4940e4e-9007-4dcf-bebc-bb2caa0e140d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120493559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.4120493559
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.2981266261
Short name T780
Test name
Test status
Simulation time 489937427746 ps
CPU time 1156.1 seconds
Started Jun 05 05:25:54 PM PDT 24
Finished Jun 05 05:45:11 PM PDT 24
Peak memory 201800 kb
Host smart-274a3f07-0df3-4b31-ac2f-07b525fcdf9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981266261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.2981266261
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.2591655302
Short name T597
Test name
Test status
Simulation time 493169429462 ps
CPU time 294.66 seconds
Started Jun 05 05:25:59 PM PDT 24
Finished Jun 05 05:30:54 PM PDT 24
Peak memory 201808 kb
Host smart-211692d2-42ac-4734-bead-520b036f7bad
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591655302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.2591655302
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.2218027692
Short name T161
Test name
Test status
Simulation time 327250207293 ps
CPU time 200.72 seconds
Started Jun 05 05:25:53 PM PDT 24
Finished Jun 05 05:29:14 PM PDT 24
Peak memory 201872 kb
Host smart-deb2f967-b2aa-4535-97e7-d9819069372f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218027692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.2218027692
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.3511032077
Short name T759
Test name
Test status
Simulation time 480865100112 ps
CPU time 194.3 seconds
Started Jun 05 05:25:52 PM PDT 24
Finished Jun 05 05:29:07 PM PDT 24
Peak memory 201788 kb
Host smart-34bdad48-e509-43be-a639-b3740b4b0267
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511032077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.3511032077
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.349802017
Short name T107
Test name
Test status
Simulation time 162782280377 ps
CPU time 42.41 seconds
Started Jun 05 05:25:50 PM PDT 24
Finished Jun 05 05:26:33 PM PDT 24
Peak memory 201904 kb
Host smart-f4c1a01b-55b7-4259-af7d-b1d63bb2964a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349802017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_w
akeup.349802017
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.40307869
Short name T515
Test name
Test status
Simulation time 602648309827 ps
CPU time 363.99 seconds
Started Jun 05 05:25:51 PM PDT 24
Finished Jun 05 05:31:56 PM PDT 24
Peak memory 201776 kb
Host smart-b88b2b6e-23db-42f0-9780-ed30445cd821
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40307869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.ad
c_ctrl_filters_wakeup_fixed.40307869
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.791769255
Short name T52
Test name
Test status
Simulation time 132138030734 ps
CPU time 683.08 seconds
Started Jun 05 05:25:50 PM PDT 24
Finished Jun 05 05:37:14 PM PDT 24
Peak memory 202108 kb
Host smart-9df2beba-dcf4-4f05-995a-45b251c7def6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791769255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.791769255
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.2133888138
Short name T500
Test name
Test status
Simulation time 37838987966 ps
CPU time 77.83 seconds
Started Jun 05 05:25:51 PM PDT 24
Finished Jun 05 05:27:10 PM PDT 24
Peak memory 201620 kb
Host smart-f2f8438c-a258-4fd3-b44c-063ba61cf6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133888138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.2133888138
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.1329842832
Short name T613
Test name
Test status
Simulation time 5369675208 ps
CPU time 7.79 seconds
Started Jun 05 05:25:54 PM PDT 24
Finished Jun 05 05:26:02 PM PDT 24
Peak memory 201628 kb
Host smart-b771485e-f22a-4f0e-9284-e6ab2f4514b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329842832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.1329842832
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.2068918950
Short name T595
Test name
Test status
Simulation time 6012954313 ps
CPU time 14.42 seconds
Started Jun 05 05:25:50 PM PDT 24
Finished Jun 05 05:26:05 PM PDT 24
Peak memory 201644 kb
Host smart-9225411b-f942-4b56-bd0a-32ffbee2f07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068918950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.2068918950
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.4116352407
Short name T87
Test name
Test status
Simulation time 365476219627 ps
CPU time 443.52 seconds
Started Jun 05 05:25:50 PM PDT 24
Finished Jun 05 05:33:14 PM PDT 24
Peak memory 201756 kb
Host smart-e0d0e7c2-f868-4ba8-9f5d-a9037100e66e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116352407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
4116352407
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.735219882
Short name T791
Test name
Test status
Simulation time 45077912847 ps
CPU time 124.46 seconds
Started Jun 05 05:25:50 PM PDT 24
Finished Jun 05 05:27:55 PM PDT 24
Peak memory 210488 kb
Host smart-df06fe39-c8b4-4364-9a4e-ed0f5ac06d41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735219882 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.735219882
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.1874533140
Short name T696
Test name
Test status
Simulation time 510498586 ps
CPU time 1.27 seconds
Started Jun 05 05:25:51 PM PDT 24
Finished Jun 05 05:25:53 PM PDT 24
Peak memory 201492 kb
Host smart-80e8d664-dd85-4bf1-b8bc-b6c2f48ae12e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874533140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.1874533140
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.981696379
Short name T175
Test name
Test status
Simulation time 163608564642 ps
CPU time 93.07 seconds
Started Jun 05 05:25:50 PM PDT 24
Finished Jun 05 05:27:23 PM PDT 24
Peak memory 201876 kb
Host smart-b02f4428-7633-4625-9405-212b40d29ad8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981696379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gatin
g.981696379
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.2267183937
Short name T738
Test name
Test status
Simulation time 542287384726 ps
CPU time 1135.32 seconds
Started Jun 05 05:25:53 PM PDT 24
Finished Jun 05 05:44:49 PM PDT 24
Peak memory 201776 kb
Host smart-b90e0730-0f5a-46c6-9e1b-e613aa912097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267183937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.2267183937
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.857728353
Short name T677
Test name
Test status
Simulation time 495946285378 ps
CPU time 335.37 seconds
Started Jun 05 05:25:50 PM PDT 24
Finished Jun 05 05:31:26 PM PDT 24
Peak memory 201816 kb
Host smart-81e40ece-3277-4ae4-ad2f-08fd7eb1dfb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857728353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.857728353
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.91747820
Short name T565
Test name
Test status
Simulation time 166229251411 ps
CPU time 392.04 seconds
Started Jun 05 05:25:59 PM PDT 24
Finished Jun 05 05:32:31 PM PDT 24
Peak memory 201800 kb
Host smart-9dd14804-6983-4d71-8b0a-8d6a923b6f56
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=91747820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt_
fixed.91747820
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.3815698788
Short name T636
Test name
Test status
Simulation time 166609157958 ps
CPU time 219.18 seconds
Started Jun 05 05:25:54 PM PDT 24
Finished Jun 05 05:29:33 PM PDT 24
Peak memory 201800 kb
Host smart-c78c895c-d388-4ace-b34c-2b4280b46c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815698788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.3815698788
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.355930458
Short name T434
Test name
Test status
Simulation time 321672282461 ps
CPU time 383.3 seconds
Started Jun 05 05:25:49 PM PDT 24
Finished Jun 05 05:32:13 PM PDT 24
Peak memory 201900 kb
Host smart-7a10bbb8-3bc1-4012-ab33-14a7626f9121
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=355930458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixed
.355930458
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.2191010664
Short name T729
Test name
Test status
Simulation time 648167026760 ps
CPU time 126.55 seconds
Started Jun 05 05:25:52 PM PDT 24
Finished Jun 05 05:27:59 PM PDT 24
Peak memory 201804 kb
Host smart-ad3c5159-4146-4052-91c9-01f2d6f8982f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191010664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.2191010664
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.1062478100
Short name T769
Test name
Test status
Simulation time 410443927683 ps
CPU time 694.36 seconds
Started Jun 05 05:25:51 PM PDT 24
Finished Jun 05 05:37:26 PM PDT 24
Peak memory 201808 kb
Host smart-851dcfa5-8709-4e8b-8de8-04ce58abd539
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062478100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.1062478100
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.1725526615
Short name T766
Test name
Test status
Simulation time 129687220059 ps
CPU time 653.53 seconds
Started Jun 05 05:25:51 PM PDT 24
Finished Jun 05 05:36:45 PM PDT 24
Peak memory 202100 kb
Host smart-0951dea8-9b95-46c6-8114-f9492bed5e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725526615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.1725526615
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.4242953636
Short name T691
Test name
Test status
Simulation time 31621093732 ps
CPU time 7.33 seconds
Started Jun 05 05:25:49 PM PDT 24
Finished Jun 05 05:25:56 PM PDT 24
Peak memory 201492 kb
Host smart-010f240e-1504-4ab4-8dd1-da68ae3f715a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242953636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.4242953636
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.1586382703
Short name T423
Test name
Test status
Simulation time 3149100915 ps
CPU time 3.46 seconds
Started Jun 05 05:25:52 PM PDT 24
Finished Jun 05 05:25:57 PM PDT 24
Peak memory 201608 kb
Host smart-be5c3873-1db3-49ed-b8af-f053f3274f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586382703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.1586382703
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.1785659638
Short name T463
Test name
Test status
Simulation time 5979049884 ps
CPU time 15.68 seconds
Started Jun 05 05:25:49 PM PDT 24
Finished Jun 05 05:26:06 PM PDT 24
Peak memory 201644 kb
Host smart-153eabea-0c4a-4335-a159-8250201abda6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785659638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.1785659638
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.462483257
Short name T619
Test name
Test status
Simulation time 400124898 ps
CPU time 0.88 seconds
Started Jun 05 05:26:00 PM PDT 24
Finished Jun 05 05:26:02 PM PDT 24
Peak memory 201496 kb
Host smart-5c46199b-efa8-43bf-aae7-3b3870e7ea0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462483257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.462483257
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.2968687864
Short name T554
Test name
Test status
Simulation time 288000033818 ps
CPU time 566.3 seconds
Started Jun 05 05:25:57 PM PDT 24
Finished Jun 05 05:35:24 PM PDT 24
Peak memory 201824 kb
Host smart-1ccbae19-408f-479a-a680-9aa9b5b49260
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968687864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.2968687864
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.3149593521
Short name T278
Test name
Test status
Simulation time 188113985855 ps
CPU time 208.47 seconds
Started Jun 05 05:26:01 PM PDT 24
Finished Jun 05 05:29:30 PM PDT 24
Peak memory 201808 kb
Host smart-8fac91f9-123e-44de-836a-97e9db0a4e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149593521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.3149593521
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.621219191
Short name T627
Test name
Test status
Simulation time 491677151362 ps
CPU time 591.55 seconds
Started Jun 05 05:25:57 PM PDT 24
Finished Jun 05 05:35:49 PM PDT 24
Peak memory 201884 kb
Host smart-51a1d4f5-1823-40af-87b2-4e4dc24cc66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621219191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.621219191
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.639039419
Short name T114
Test name
Test status
Simulation time 166444319980 ps
CPU time 80.47 seconds
Started Jun 05 05:26:02 PM PDT 24
Finished Jun 05 05:27:23 PM PDT 24
Peak memory 201796 kb
Host smart-d112660a-1200-440a-bde8-2bfdb41eb7dc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=639039419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt
_fixed.639039419
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.3670451996
Short name T669
Test name
Test status
Simulation time 163760649717 ps
CPU time 97.69 seconds
Started Jun 05 05:25:50 PM PDT 24
Finished Jun 05 05:27:29 PM PDT 24
Peak memory 201712 kb
Host smart-ed769892-9f5a-4e13-8722-8f0cf7f7c614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670451996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.3670451996
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.2179826481
Short name T383
Test name
Test status
Simulation time 504312609411 ps
CPU time 1207.2 seconds
Started Jun 05 05:25:58 PM PDT 24
Finished Jun 05 05:46:06 PM PDT 24
Peak memory 201800 kb
Host smart-77e98168-b98f-4ae1-aa38-c5c31a09fdca
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179826481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.2179826481
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.4150575437
Short name T95
Test name
Test status
Simulation time 367886456688 ps
CPU time 828.28 seconds
Started Jun 05 05:25:59 PM PDT 24
Finished Jun 05 05:39:48 PM PDT 24
Peak memory 201868 kb
Host smart-c6c81e0c-4541-4faf-9af4-361ae5c13ece
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150575437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.4150575437
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.1366513254
Short name T490
Test name
Test status
Simulation time 598937727891 ps
CPU time 332.16 seconds
Started Jun 05 05:25:57 PM PDT 24
Finished Jun 05 05:31:30 PM PDT 24
Peak memory 201868 kb
Host smart-e3a6d095-894c-4732-8cd6-4683ce869296
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366513254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.1366513254
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.3443536203
Short name T757
Test name
Test status
Simulation time 64962112359 ps
CPU time 361.33 seconds
Started Jun 05 05:25:58 PM PDT 24
Finished Jun 05 05:32:00 PM PDT 24
Peak memory 202120 kb
Host smart-d07925fb-d2f4-48e0-a5a2-8631cc34bbcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443536203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.3443536203
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.3991942354
Short name T765
Test name
Test status
Simulation time 34288403845 ps
CPU time 20.64 seconds
Started Jun 05 05:25:58 PM PDT 24
Finished Jun 05 05:26:20 PM PDT 24
Peak memory 201640 kb
Host smart-f1a8020a-2070-4839-a496-9f64ce13e791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991942354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.3991942354
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.1345406662
Short name T113
Test name
Test status
Simulation time 4419370306 ps
CPU time 6.03 seconds
Started Jun 05 05:25:59 PM PDT 24
Finished Jun 05 05:26:06 PM PDT 24
Peak memory 201608 kb
Host smart-2c06f140-56b3-4d07-8c6a-21b10aec40d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345406662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.1345406662
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.1202992839
Short name T578
Test name
Test status
Simulation time 6024858559 ps
CPU time 4.6 seconds
Started Jun 05 05:25:52 PM PDT 24
Finished Jun 05 05:25:57 PM PDT 24
Peak memory 201628 kb
Host smart-998895b0-c184-4d3f-bddd-f6712a06648e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202992839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.1202992839
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.2932029593
Short name T761
Test name
Test status
Simulation time 483509198250 ps
CPU time 1522 seconds
Started Jun 05 05:26:01 PM PDT 24
Finished Jun 05 05:51:24 PM PDT 24
Peak memory 202120 kb
Host smart-3210bde8-c32f-432d-8158-4264cbce403d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932029593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
2932029593
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.3019445495
Short name T118
Test name
Test status
Simulation time 32261339696 ps
CPU time 123.15 seconds
Started Jun 05 05:26:01 PM PDT 24
Finished Jun 05 05:28:05 PM PDT 24
Peak memory 210464 kb
Host smart-a9d617c7-ea52-43e8-9110-baec3eaa163b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019445495 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.3019445495
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.1631471168
Short name T600
Test name
Test status
Simulation time 352339051 ps
CPU time 1.5 seconds
Started Jun 05 05:25:58 PM PDT 24
Finished Jun 05 05:26:00 PM PDT 24
Peak memory 201444 kb
Host smart-e135bfe7-cee0-45a7-876e-13afd62c558a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631471168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.1631471168
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.1667112850
Short name T231
Test name
Test status
Simulation time 162539465083 ps
CPU time 193.34 seconds
Started Jun 05 05:26:00 PM PDT 24
Finished Jun 05 05:29:14 PM PDT 24
Peak memory 201760 kb
Host smart-e171fa71-c8ac-4b97-aac7-9ae2aa74b3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667112850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.1667112850
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.4288395666
Short name T193
Test name
Test status
Simulation time 495002471151 ps
CPU time 81.54 seconds
Started Jun 05 05:25:58 PM PDT 24
Finished Jun 05 05:27:20 PM PDT 24
Peak memory 201884 kb
Host smart-e99e38be-b850-495c-8461-0f767d4d9d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288395666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.4288395666
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.1286940183
Short name T720
Test name
Test status
Simulation time 160176834300 ps
CPU time 100.15 seconds
Started Jun 05 05:26:02 PM PDT 24
Finished Jun 05 05:27:43 PM PDT 24
Peak memory 201772 kb
Host smart-bd9e8971-e048-40cd-858b-d4ed72502897
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286940183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.1286940183
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.160377688
Short name T782
Test name
Test status
Simulation time 161542214524 ps
CPU time 275.81 seconds
Started Jun 05 05:25:58 PM PDT 24
Finished Jun 05 05:30:34 PM PDT 24
Peak memory 201824 kb
Host smart-5a9718f7-6d09-4c84-a49c-3fc2697cf76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160377688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.160377688
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.3584744191
Short name T638
Test name
Test status
Simulation time 490744610671 ps
CPU time 579.58 seconds
Started Jun 05 05:25:59 PM PDT 24
Finished Jun 05 05:35:39 PM PDT 24
Peak memory 201724 kb
Host smart-f07d53d5-7234-4e70-8fda-b31edc7504a0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584744191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.3584744191
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.148095698
Short name T340
Test name
Test status
Simulation time 585368926674 ps
CPU time 618.03 seconds
Started Jun 05 05:25:59 PM PDT 24
Finished Jun 05 05:36:18 PM PDT 24
Peak memory 201812 kb
Host smart-3681e772-c874-436b-8b72-55bcc9194d0a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148095698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_w
akeup.148095698
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.73248332
Short name T482
Test name
Test status
Simulation time 592183992686 ps
CPU time 360.05 seconds
Started Jun 05 05:26:00 PM PDT 24
Finished Jun 05 05:32:01 PM PDT 24
Peak memory 201832 kb
Host smart-efeb6786-0f0d-426e-aa2f-c86416dbbc87
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73248332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.ad
c_ctrl_filters_wakeup_fixed.73248332
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.231457936
Short name T359
Test name
Test status
Simulation time 108138753172 ps
CPU time 582.21 seconds
Started Jun 05 05:26:02 PM PDT 24
Finished Jun 05 05:35:45 PM PDT 24
Peak memory 202116 kb
Host smart-c0bcb66c-2ac4-4793-9abd-86525569bc21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231457936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.231457936
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.742023713
Short name T566
Test name
Test status
Simulation time 40313287404 ps
CPU time 91.1 seconds
Started Jun 05 05:26:00 PM PDT 24
Finished Jun 05 05:27:32 PM PDT 24
Peak memory 201628 kb
Host smart-1b327081-4a00-4f4b-997f-eecf04de483d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742023713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.742023713
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.3325061513
Short name T678
Test name
Test status
Simulation time 3131139854 ps
CPU time 4.5 seconds
Started Jun 05 05:26:01 PM PDT 24
Finished Jun 05 05:26:06 PM PDT 24
Peak memory 201620 kb
Host smart-91b1af4e-e7fe-4654-a2ca-62ea36936d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325061513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.3325061513
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.1199096215
Short name T594
Test name
Test status
Simulation time 5709026198 ps
CPU time 2.19 seconds
Started Jun 05 05:26:00 PM PDT 24
Finished Jun 05 05:26:03 PM PDT 24
Peak memory 201640 kb
Host smart-c5772585-c1fc-4724-9f9a-4ded1a3d7f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199096215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.1199096215
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.3884215970
Short name T286
Test name
Test status
Simulation time 759180034180 ps
CPU time 484.28 seconds
Started Jun 05 05:25:57 PM PDT 24
Finished Jun 05 05:34:02 PM PDT 24
Peak memory 201808 kb
Host smart-ad7ccd9b-bcda-4ccc-8d9c-d8bb11748a8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884215970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
3884215970
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.159612697
Short name T108
Test name
Test status
Simulation time 115758556449 ps
CPU time 224.7 seconds
Started Jun 05 05:26:02 PM PDT 24
Finished Jun 05 05:29:48 PM PDT 24
Peak memory 210440 kb
Host smart-a5b1e458-79c3-4b99-92b5-969b64998c89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159612697 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.159612697
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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