Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6882	1			T6	51		T11	15		T12	20
testmodes[AdcCtrlTestmodeNormal]	5372	1			T1	3		T2	3		T3	3
testmodes[AdcCtrlTestmodeLowpower]	5681	1			T4	20		T5	1		T6	58
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3836	1			T6	19		T11	6		T12	19
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1688	1			T6	18		T11	8		T21	8
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1248	1			T6	14		T12	1		T21	2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1696	1			T6	16		T11	8		T21	7
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1959	1			T1	2		T2	2		T3	2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1385	1			T6	28		T9	1		T12	2
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1225	1			T6	16		T21	3		T24	17
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1393	1			T6	25		T12	3		T21	4
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2808	1			T4	19		T6	16		T7	13