Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26455

1

T1

3

T2

27

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22821

1

T1

1

T2

4

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3634

1

T1

2

T2

23

T3

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20403

1

T1

2

T2

14

T3

2

auto[1]

6052

1

T1

1

T2

13

T3

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22301

1

T1

3

T2

3

T3

3

auto[1]

4154

1

T2

24

T8

4

T9

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	14	1			T204	14		-	-		-	-
values[0]	4	1			T205	1		T206	1		T207	1
values[1]	801	1			T141	7		T133	5		T29	31
values[2]	754	1			T8	9		T11	1		T39	23
values[3]	555	1			T2	4		T21	13		T33	6
values[4]	484	1			T23	14		T133	24		T134	54
values[5]	2958	1			T3	1		T9	2		T10	2
values[6]	675	1			T2	10		T12	6		T23	3
values[7]	948	1			T1	1		T3	1		T136	39
values[8]	902	1			T1	1		T3	1		T12	1
values[9]	1351	1			T1	1		T2	13		T5	7
minimum	17009	1			T4	20		T6	179		T7	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	950	1			T39	23		T141	7		T133	5
values[1]	730	1			T8	9		T11	1		T33	6
values[2]	498	1			T21	13		T133	24		T134	25
values[3]	2951	1			T2	4		T10	2		T22	14
values[4]	539	1			T3	1		T9	2		T134	28
values[5]	867	1			T2	10		T3	1		T12	6
values[6]	933	1			T1	2		T12	1		T136	39
values[7]	724	1			T3	1		T9	24		T25	7
values[8]	995	1			T1	1		T5	7		T23	14
values[9]	222	1			T2	13		T34	12		T158	17
minimum	17046	1			T4	20		T6	179		T7	14

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22089

1

T1

3

T2

27

T3

3

auto[1]

4366

1

T5

6

T8

4

T9

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T39	13		T29	18		T159	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T141	7		T133	3		T137	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T8	5		T11	1		T33	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T141	10		T208	1		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T133	12		T134	13		T88	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T21	7		T137	12		T86	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1652	1			T2	1		T10	2		T22	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T209	1		T158	8		T179	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T9	1		T139	6		T86	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T3	1		T134	12		T137	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T23	3		T142	8		T35	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T2	1		T3	1		T12	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T136	17		T29	1		T140	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T1	2		T12	1		T139	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T3	1		T9	13		T39	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T25	1		T151	1		T72	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T1	1		T208	1		T84	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T5	7		T23	14		T210	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T37	6		T211	4		T212	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T2	1		T34	6		T158	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16860	1			T4	20		T6	179		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T186	14		T213	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T39	10		T29	13		T159	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T133	2		T208	9		T82	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T8	4		T136	4		T35	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T208	12		T143	12		T83	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T133	12		T134	12		T214	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T21	6		T86	12		T215	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	952	1			T2	3		T167	19		T134	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T209	2		T158	7		T183	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T9	1		T139	9		T86	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T134	16		T152	8		T209	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T35	10		T83	13		T197	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T2	9		T12	1		T25	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T136	22		T29	2		T140	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T160	10		T77	1		T161	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T9	11		T39	5		T82	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T25	6		T72	7		T216	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T208	9		T84	5		T76	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T152	6		T209	2		T13	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T37	3		T211	3		T217	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T2	12		T34	6		T158	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T33	2		T29	2		T13	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T186	12		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T204	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T206	1		T207	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T205	1		T218	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T29	18		T159	11		T78	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T141	7		T133	3		T137	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T8	5		T11	1		T39	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T208	1		T143	1		T83	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T2	1		T33	6		T136	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T21	7		T141	10		T86	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T23	14		T133	12		T134	28
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T137	12		T209	1		T158	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1660	1			T9	1		T10	2		T22	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T3	1		T134	12		T137	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T23	3		T142	8		T102	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T2	1		T12	5		T25	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T136	17		T29	1		T35	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T1	1		T3	1		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T3	1		T39	17		T111	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T1	1		T12	1		T25	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	363	1			T1	1		T9	13		T208	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	346	1			T2	1		T5	7		T23	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16860	1			T4	20		T6	179		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T204	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T29	13		T159	11		T78	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T133	2		T208	9		T82	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T8	4		T39	10		T38	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T208	12		T143	12		T83	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T2	3		T136	4		T35	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T21	6		T86	12		T219	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T133	12		T134	26		T36	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T209	2		T158	7		T183	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	965	1			T9	1		T167	19		T220	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T134	16		T152	8		T72	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T102	9		T107	8		T221	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T2	9		T12	1		T25	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T136	22		T29	2		T35	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T160	10		T89	3		T222	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T39	5		T140	8		T82	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T25	6		T77	1		T161	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	327	1			T9	11		T208	9		T158	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T2	12		T34	6		T152	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T33	2		T29	2		T13	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T39	11		T29	14		T159	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T141	1		T133	3		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T8	5		T11	1		T33	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T141	1		T208	13		T143	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T133	13		T134	13		T88	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T21	10		T137	1		T86	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1300	1			T2	4		T10	2		T22	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T209	3		T158	8		T179	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T9	2		T139	10		T86	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T3	1		T134	17		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T23	1		T142	1		T35	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T2	10		T3	1		T12	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T136	24		T29	3		T140	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T1	2		T12	1		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T3	1		T9	12		T39	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T25	7		T151	1		T72	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	313	1			T1	1		T208	10		T84	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T5	1		T23	1		T210	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T37	6		T211	6		T212	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T2	13		T34	8		T158	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17009	1			T4	20		T6	179		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T186	13		T213	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T39	12		T29	17		T159	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T141	6		T133	2		T137	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T8	4		T136	14		T38	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T141	9		T83	13		T170	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T133	11		T134	12		T214	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T21	3		T137	11		T86	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1304	1			T22	13		T23	13		T135	34
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T158	7		T179	6		T223	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T139	5		T86	2		T160	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T134	11		T137	12		T152	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T23	2		T142	7		T35	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T12	2		T152	4		T140	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T136	15		T140	10		T83	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T139	12		T160	11		T162	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T9	12		T39	15		T158	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T72	7		T216	1		T224	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T76	12		T159	10		T225	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T5	6		T23	13		T152	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T37	3		T211	1		T212	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T34	4		T158	8		T226	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T186	13		T213	10		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	8	40	83.33	8

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum , values[0]]	*	--	--	4
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T204	14		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T206	1		T207	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T205	1		T218	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T29	14		T159	12		T78	23
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T141	1		T133	3		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T8	5		T11	1		T39	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T208	13		T143	13		T83	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T2	4		T33	6		T136	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T21	10		T141	1		T86	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T23	1		T133	13		T134	28
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T137	1		T209	3		T158	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1307	1			T9	2		T10	2		T22	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T3	1		T134	17		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T23	1		T142	1		T102	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T2	10		T12	4		T25	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T136	24		T29	3		T35	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T1	1		T3	1		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T3	1		T39	7		T111	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T1	1		T12	1		T25	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	400	1			T1	1		T9	12		T208	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	383	1			T2	13		T5	1		T23	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17009	1			T4	20		T6	179		T7	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T29	17		T159	10		T78	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T141	6		T133	2		T137	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T8	4		T39	12		T38	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T83	13		T170	7		T148	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T136	14		T147	11		T227	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T21	3		T141	9		T86	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T23	13		T133	11		T134	26
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T137	11		T158	7		T179	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1318	1			T22	13		T135	34		T228	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T134	11		T137	12		T152	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T23	2		T142	7		T107	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T12	2		T152	4		T140	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T136	15		T35	9		T83	28
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T160	11		T162	15		T229	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T39	15		T140	10		T76	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T139	12		T216	1		T224	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T9	12		T158	9		T159	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T5	6		T23	13		T34	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22089

1

T1

3

T2

27

T3

3

auto[1]

auto[0]

4366

1

T5

6

T8

4

T9

12

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26455

1

T1

3

T2

27

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23152

1

T1

3

T2

23

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3303

1

T2

4

T9

26

T11

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20244

1

T1

2

T3

2

T4

20

auto[1]

6211

1

T1

1

T2

27

T3

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22301

1

T1

3

T2

3

T3

3

auto[1]

4154

1

T2

24

T8

4

T9

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	15	1			T227	15		-	-		-	-
values[0]	139	1			T141	7		T208	13		T13	1
values[1]	749	1			T3	1		T29	31		T152	14
values[2]	662	1			T1	1		T3	2		T9	2
values[3]	638	1			T2	4		T23	3		T25	7
values[4]	653	1			T1	2		T8	9		T111	1
values[5]	3052	1			T5	7		T10	2		T22	14
values[6]	812	1			T39	24		T34	12		T133	5
values[7]	773	1			T2	10		T12	1		T25	13
values[8]	624	1			T2	13		T21	13		T23	14
values[9]	1329	1			T9	24		T12	6		T39	21
minimum	17009	1			T4	20		T6	179		T7	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	997	1			T1	1		T11	1		T141	7
values[1]	676	1			T2	4		T3	3		T9	2
values[2]	733	1			T23	3		T25	7		T111	1
values[3]	2922	1			T1	1		T5	7		T8	9
values[4]	821	1			T1	1		T23	14		T39	1
values[5]	707	1			T2	10		T12	1		T25	13
values[6]	783	1			T2	13		T23	14		T141	10
values[7]	644	1			T39	21		T142	8		T83	28
values[8]	894	1			T9	24		T21	13		T29	3
values[9]	256	1			T12	6		T34	1		T133	24
minimum	17022	1			T4	20		T6	179		T7	14

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22089

1

T1

3

T2

27

T3

3

auto[1]

4366

1

T5

6

T8

4

T9

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	321	1			T1	1		T208	1		T139	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T11	1		T141	7		T29	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T3	3		T138	1		T209	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T2	1		T9	1		T33	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T23	3		T136	17		T209	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T25	1		T111	1		T137	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1604	1			T1	1		T5	7		T8	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T151	1		T134	15		T35	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T1	1		T23	14		T39	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T136	15		T134	13		T137	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T2	1		T25	1		T39	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T12	1		T13	3		T153	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T2	1		T23	14		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T141	10		T152	8		T84	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T142	8		T144	1		T160	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T39	16		T83	15		T158	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T21	7		T210	1		T208	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T9	13		T29	1		T208	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T12	5		T34	1		T137	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T133	12		T159	11		T145	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16861	1			T4	20		T6	179		T7	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T208	12		T159	8		T155	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T29	13		T152	6		T35	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T209	2		T86	7		T72	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T2	3		T9	1		T107	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T136	22		T209	2		T82	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T25	6		T143	12		T158	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	976	1			T8	4		T167	19		T220	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T134	14		T35	5		T84	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T152	10		T159	9		T230	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T136	4		T134	12		T160	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T2	9		T25	12		T39	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T13	1		T231	8		T232	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T2	12		T134	16		T140	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T152	8		T84	5		T233	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T160	3		T216	3		T174	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T39	5		T83	13		T158	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T21	6		T208	9		T158	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T9	11		T29	2		T208	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T12	1		T14	2		T221	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T133	12		T159	11		T145	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T33	2		T29	2		T13	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T227	6		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T208	1		T146	1		T234	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T141	7		T13	1		T174	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T3	1		T139	13		T159	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T29	18		T152	8		T35	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T1	1		T3	2		T209	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T9	1		T11	1		T33	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T23	3		T136	17		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T2	1		T25	1		T158	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T1	2		T8	5		T140	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T111	1		T151	1		T134	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1679	1			T5	7		T10	2		T22	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T136	15		T134	13		T137	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T39	14		T34	6		T133	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T147	22		T235	12		T236	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T2	1		T25	1		T134	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T12	1		T141	10		T13	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T2	1		T21	7		T23	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T152	8		T158	9		T179	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	359	1			T12	5		T34	1		T137	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	385	1			T9	13		T39	16		T133	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16860	1			T4	20		T6	179		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T227	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T208	12		T146	12		T234	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T174	12		T237	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T159	8		T155	1		T89	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T29	13		T152	6		T35	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T209	2		T37	3		T38	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T9	1		T183	9		T146	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T136	22		T209	2		T86	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T2	3		T25	6		T158	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T8	4		T140	8		T82	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T134	14		T143	12		T35	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1041	1			T167	19		T220	19		T150	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T136	4		T134	12		T160	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T39	10		T34	6		T133	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T231	8		T232	14		T238	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T2	9		T25	12		T134	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T13	1		T84	5		T233	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T2	12		T21	6		T72	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T152	8		T158	8		T230	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T12	1		T208	9		T158	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	347	1			T9	11		T39	5		T133	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T33	2		T29	2		T13	1