Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26455

1

T1

3

T2

27

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23122

1

T1

3

T2

23

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3333

1

T2

4

T9

2

T11

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20348

1

T1

1

T3

2

T4

20

auto[1]

6107

1

T1

2

T2

27

T3

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22301

1

T1

3

T2

3

T3

3

auto[1]

4154

1

T2

24

T8

4

T9

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	298	1			T34	1		T133	24		T210	1
values[0]	45	1			T208	13		T13	1		T234	13
values[1]	860	1			T3	1		T11	1		T141	7
values[2]	662	1			T1	1		T2	4		T3	2
values[3]	625	1			T25	7		T136	39		T137	12
values[4]	667	1			T1	1		T8	9		T23	3
values[5]	3048	1			T1	1		T5	7		T10	2
values[6]	798	1			T12	1		T39	24		T34	12
values[7]	812	1			T2	10		T25	13		T141	10
values[8]	595	1			T2	13		T23	14		T142	8
values[9]	1036	1			T9	24		T12	6		T21	13
minimum	17009	1			T4	20		T6	179		T7	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	798	1			T1	1		T3	1		T11	1
values[1]	643	1			T2	4		T3	2		T9	2
values[2]	729	1			T23	3		T25	7		T111	1
values[3]	2936	1			T1	1		T8	9		T10	2
values[4]	768	1			T1	1		T5	7		T23	14
values[5]	752	1			T2	10		T12	1		T25	13
values[6]	803	1			T2	13		T23	14		T141	10
values[7]	623	1			T39	21		T142	8		T151	1
values[8]	970	1			T9	24		T21	13		T29	3
values[9]	192	1			T12	6		T34	1		T133	24
minimum	17241	1			T4	20		T6	179		T7	14

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22089

1

T1

3

T2

27

T3

3

auto[1]

4366

1

T5

6

T8

4

T9

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T1	1		T3	1		T155	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T11	1		T152	8		T35	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T3	2		T138	1		T153	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T2	1		T9	1		T33	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T23	3		T111	1		T136	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T25	1		T137	12		T205	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1624	1			T1	1		T8	5		T10	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T151	1		T134	15		T35	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T1	1		T5	7		T23	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T136	15		T134	13		T137	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T2	1		T25	1		T39	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T12	1		T133	3		T13	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T2	1		T141	10		T134	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T23	14		T152	8		T233	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T142	8		T151	1		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T39	16		T83	15		T158	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T9	13		T21	7		T210	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T29	1		T208	1		T209	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T12	5		T34	1		T137	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T133	12		T145	1		T14	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16888	1			T4	20		T6	179		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T141	7		T29	18		T13	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T155	1		T78	10		T146	22
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T152	6		T35	10		T183	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T72	7		T37	3		T38	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T2	3		T9	1		T209	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T136	22		T143	12		T209	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T25	6		T158	7		T36	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	968	1			T8	4		T167	19		T220	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T134	14		T35	4		T188	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T152	10		T159	9		T230	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T136	4		T134	12		T84	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T2	9		T25	12		T39	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T133	2		T13	1		T170	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T2	12		T134	16		T140	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T152	8		T233	9		T230	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T160	3		T72	11		T216	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T39	5		T83	13		T158	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T9	11		T21	6		T208	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T29	2		T208	9		T209	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T12	1		T221	12		T282	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T133	12		T145	14		T14	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T33	2		T29	2		T208	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T29	13		T77	1		T298	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T34	1		T210	1		T208	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T133	12		T145	1		T168	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T208	1		T299	1		T300	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T13	1		T234	8		T301	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T3	1		T139	13		T159	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T11	1		T141	7		T29	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T1	1		T3	2		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T2	1		T9	1		T33	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T136	17		T138	1		T209	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T25	1		T137	12		T86	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T1	1		T8	5		T23	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T151	1		T134	15		T35	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1649	1			T1	1		T5	7		T10	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T136	15		T134	13		T137	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T39	14		T34	6		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T12	1		T133	3		T180	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T2	1		T25	1		T141	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T13	3		T233	1		T153	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T2	1		T142	8		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T23	14		T152	8		T158	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T9	13		T12	5		T21	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T39	16		T29	1		T208	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16860	1			T4	20		T6	179		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T208	9		T246	2		T239	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T133	12		T145	12		T227	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T208	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T234	5		T301	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T159	8		T155	1		T146	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T29	13		T152	6		T35	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T37	3		T38	2		T78	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T2	3		T9	1		T209	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T136	22		T209	2		T82	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T25	6		T86	7		T158	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T8	4		T143	12		T140	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T134	14		T35	4		T84	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1008	1			T167	19		T220	19		T150	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T136	4		T134	12		T160	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T39	10		T34	6		T152	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T133	2		T248	13		T170	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T2	9		T25	12		T134	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T13	1		T233	9		T38	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T2	12		T72	11		T223	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T152	8		T158	8		T230	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T9	11		T12	1		T21	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T39	5		T29	2		T208	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T33	2		T29	2		T13	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T1	1		T3	1		T155	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T11	1		T152	7		T35	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T3	2		T138	1		T153	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T2	4		T9	2		T33	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T23	1		T111	1		T136	24
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T25	7		T137	1		T205	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1311	1			T1	1		T8	5		T10	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T151	1		T134	15		T35	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T1	1		T5	1		T23	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T136	5		T134	13		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T2	10		T25	13		T39	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T12	1		T133	3		T13	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T2	13		T141	1		T134	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T23	1		T152	9		T233	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T142	1		T151	1		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T39	6		T83	14		T158	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T9	12		T21	10		T210	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T29	3		T208	10		T209	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T12	4		T34	1		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T133	13		T145	15		T14	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17062	1			T4	20		T6	179		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T141	1		T29	14		T13	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T155	1		T78	1		T229	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T152	7		T35	9		T72	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T72	7		T37	3		T38	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T86	2		T224	19		T302	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T23	2		T136	15		T168	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T137	11		T158	7		T36	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1281	1			T8	4		T22	13		T135	34
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T134	14		T35	7		T240	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T5	6		T23	13		T152	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T136	14		T134	12		T137	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T39	12		T34	4		T86	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T133	2		T170	6		T147	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T141	9		T134	11		T140	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T23	13		T152	7		T179	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T142	7		T160	13		T72	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T39	15		T83	14		T158	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T9	12		T21	3		T140	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T139	5		T158	9		T159	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T12	2		T137	5		T83	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T133	11		T14	2		T177	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T139	12		T159	7		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T141	6		T29	17		T298	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T34	1		T210	1		T208	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T133	13		T145	13		T168	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T208	13		T299	1		T300	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T13	1		T234	6		T301	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T3	1		T139	1		T159	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T11	1		T141	1		T29	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T1	1		T3	2		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T2	4		T9	2		T33	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T136	24		T138	1		T209	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T25	7		T137	1		T86	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T1	1		T8	5		T23	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T151	1		T134	15		T35	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1349	1			T1	1		T5	1		T10	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T136	5		T134	13		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T39	12		T34	8		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T12	1		T133	3		T180	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T2	10		T25	13		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T13	4		T233	10		T153	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T2	13		T142	1		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T23	1		T152	9		T158	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T9	12		T12	4		T21	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T39	6		T29	3		T208	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17009	1			T4	20		T6	179		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T14	1		T256	14		T212	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T133	11		T168	12		T227	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T234	7		T301	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T139	12		T159	7		T155	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T141	6		T29	17		T152	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T37	3		T38	3		T78	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T224	19		T303	8		T302	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T136	15		T72	7		T168	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T137	11		T86	2		T158	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T8	4		T23	2		T140	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T134	14		T35	7		T229	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1308	1			T5	6		T22	13		T23	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T136	14		T134	12		T137	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T39	12		T34	4		T152	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T133	2		T180	9		T248	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T141	9		T134	11		T140	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T38	1		T78	9		T244	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T142	7		T72	15		T223	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T23	13		T152	7		T158	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T9	12		T12	2		T21	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T39	15		T139	5		T83	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22089

1

T1

3

T2

27

T3

3

auto[1]

auto[0]

4366

1

T5

6

T8

4

T9

12