Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26455

1

T1

3

T2

27

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22574

1

T1

2

T2

13

T3

2

auto[ADC_CTRL_FILTER_COND_OUT]

3881

1

T1

1

T2

14

T3

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20277

1

T1

2

T2

4

T3

2

auto[1]

6178

1

T1

1

T2

23

T3

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22301

1

T1

3

T2

3

T3

3

auto[1]

4154

1

T2

24

T8

4

T9

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	248	1			T23	3		T29	31		T233	10
values[0]	14	1			T2	4		T304	9		T305	1
values[1]	732	1			T9	24		T111	1		T136	26
values[2]	706	1			T8	9		T21	13		T25	7
values[3]	825	1			T23	14		T72	27		T77	1
values[4]	770	1			T39	21		T34	1		T141	10
values[5]	742	1			T3	1		T12	6		T209	3
values[6]	697	1			T1	3		T2	10		T3	1
values[7]	782	1			T3	1		T12	1		T134	28
values[8]	2963	1			T2	13		T9	2		T10	2
values[9]	967	1			T39	23		T134	25		T137	13
minimum	17009	1			T4	20		T6	179		T7	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	751	1			T9	24		T136	26		T137	12
values[1]	724	1			T8	9		T21	13		T25	7
values[2]	760	1			T23	14		T39	21		T72	48
values[3]	843	1			T12	6		T34	1		T141	10
values[4]	580	1			T1	1		T3	1		T209	3
values[5]	928	1			T1	2		T2	10		T3	1
values[6]	2928	1			T2	13		T3	1		T10	2
values[7]	677	1			T9	2		T11	1		T23	14
values[8]	963	1			T23	3		T39	23		T134	25
values[9]	105	1			T29	31		T253	3		T255	9
minimum	17196	1			T2	4		T4	20		T6	179

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22089

1

T1

3

T2

27

T3

3

auto[1]

4366

1

T5

6

T8

4

T9

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T137	12		T138	1		T209	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T9	13		T136	14		T149	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T25	1		T136	3		T209	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T8	5		T21	7		T133	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T23	14		T39	16		T77	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T72	26		T159	8		T219	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T133	12		T111	1		T136	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T12	5		T34	1		T141	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T3	1		T160	14		T270	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T1	1		T209	1		T140	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T1	2		T5	7		T12	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	346	1			T2	1		T3	1		T134	27
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1602	1			T2	1		T3	1		T10	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T140	11		T219	1		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T9	1		T11	1		T23	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T33	6		T210	1		T152	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T23	3		T137	13		T152	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T39	13		T134	13		T13	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T253	2		T255	5		T232	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T29	18		T79	2		T277	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16925	1			T4	20		T6	179		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T2	1		T83	14		T197	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T209	2		T35	1		T230	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T9	11		T136	12		T183	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T25	6		T136	10		T209	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T8	4		T21	6		T133	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T39	5		T38	2		T170	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T72	22		T159	8		T219	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T133	12		T136	4		T84	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T12	1		T83	13		T86	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T160	3		T214	4		T161	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T209	2		T140	18		T158	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T25	12		T34	6		T219	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T2	9		T134	30		T208	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1042	1			T2	12		T167	19		T220	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T140	8		T145	12		T107	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T9	1		T29	2		T208	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T152	16		T160	10		T37	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T152	8		T143	12		T139	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T39	10		T134	12		T13	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T253	1		T255	4		T232	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T29	13		T79	1		T18	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T33	2		T29	2		T13	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T2	3		T83	13		T197	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T23	3		T270	1		T215	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T29	18		T233	1		T179	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T304	2		T305	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T2	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T111	1		T137	12		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T9	13		T136	14		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T25	1		T136	3		T209	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T8	5		T21	7		T133	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T23	14		T77	1		T270	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T72	16		T223	15		T219	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T39	16		T133	12		T111	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T34	1		T141	10		T83	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T3	1		T158	9		T153	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T12	5		T209	1		T140	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T1	2		T5	7		T25	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T1	1		T2	1		T3	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T3	1		T12	1		T137	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T134	12		T140	11		T145	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1604	1			T2	1		T9	1		T10	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T33	6		T152	13		T160	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T137	13		T138	1		T152	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T39	13		T134	13		T210	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16860	1			T4	20		T6	179		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T215	10		T253	1		T306	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T29	13		T233	9		T14	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T304	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T2	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T209	2		T230	5		T243	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T9	11		T136	12		T83	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T25	6		T136	10		T209	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T8	4		T21	6		T133	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T38	2		T188	8		T107	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T72	11		T223	12		T219	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T39	5		T133	12		T136	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T83	13		T86	19		T158	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T158	8		T160	3		T214	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T12	1		T209	2		T140	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T25	12		T34	6		T263	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T2	9		T134	14		T208	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T208	9		T219	10		T230	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T134	16		T140	8		T145	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1012	1			T2	12		T9	1		T167	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T152	16		T160	10		T89	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T152	8		T143	12		T139	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T39	10		T134	12		T13	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T33	2		T29	2		T13	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T137	1		T138	1		T209	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T9	12		T136	13		T149	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T25	7		T136	11		T209	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T8	5		T21	10		T133	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T23	1		T39	6		T77	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T72	24		T159	9		T219	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T133	13		T111	1		T136	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T12	4		T34	1		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T3	1		T160	4		T270	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T1	1		T209	3		T140	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T1	2		T5	1		T12	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T2	10		T3	1		T134	32
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1378	1			T2	13		T3	1		T10	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T140	9		T219	1		T145	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T9	2		T11	1		T23	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T33	6		T210	1		T152	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T23	1		T137	1		T152	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T39	11		T134	13		T13	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T253	2		T255	5		T232	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T29	14		T79	2		T277	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17068	1			T4	20		T6	179		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T2	4		T83	14		T197	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T137	11		T243	11		T168	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T9	12		T136	13		T76	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T136	2		T107	7		T222	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T8	4		T21	3		T133	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T23	13		T39	15		T38	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T72	24		T159	7		T248	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T133	11		T136	14		T158	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T12	2		T141	9		T83	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T160	13		T214	2		T262	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T140	19		T158	9		T180	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T5	6		T34	4		T141	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T134	25		T258	12		T78	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1266	1			T22	13		T135	34		T137	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T140	10		T107	17		T174	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T23	13		T139	12		T158	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T152	11		T83	14		T160	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T23	2		T137	12		T152	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T39	12		T134	12		T36	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T253	1		T255	4		T232	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T29	17		T79	1		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T235	11		T217	13		T304	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T83	13		T197	1		T186	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T23	1		T270	1		T215	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T29	14		T233	10		T179	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T304	8		T305	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T2	4		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T111	1		T137	1		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T9	12		T136	13		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T25	7		T136	11		T209	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T8	5		T21	10		T133	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T23	1		T77	1		T270	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T72	12		T223	13		T219	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T39	6		T133	13		T111	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T34	1		T141	1		T83	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T3	1		T158	9		T153	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T12	4		T209	3		T140	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T1	2		T5	1		T25	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T1	1		T2	10		T3	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T3	1		T12	1		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T134	17		T140	9		T145	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1352	1			T2	13		T9	2		T10	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T33	6		T152	18		T160	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T137	1		T138	1		T152	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T39	11		T134	13		T210	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17009	1			T4	20		T6	179		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T23	2		T169	11		T253	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T29	17		T179	6		T14	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T304	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T137	11		T243	11		T168	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T9	12		T136	13		T83	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T136	2		T216	1		T147	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T8	4		T21	3		T133	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T23	13		T38	3		T168	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T72	15		T223	14		T248	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T39	15		T133	11		T136	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T141	9		T83	14		T86	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T158	8		T160	13		T214	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T12	2		T140	19		T180	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T5	6		T34	4		T141	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T134	14		T258	12		T78	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T137	5		T168	7		T170	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T134	11		T140	10		T107	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1264	1			T22	13		T23	13		T135	34
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T152	11		T160	11		T258	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T137	12		T152	7		T139	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T39	12		T134	12		T83	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22089

1

T1

3

T2

27

T3

3

auto[1]

auto[0]

4366

1

T5

6

T8

4

T9

12