Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26455

1

T1

3

T2

27

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22705

1

T1

2

T2

27

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3750

1

T1

1

T3

2

T5

7

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19646

1

T1

3

T2

10

T4

20

auto[1]

6809

1

T2

17

T3

3

T5

7

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22301

1

T1

3

T2

3

T3

3

auto[1]

4154

1

T2

24

T8

4

T9

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	640	1			T6	10		T11	2		T21	4
values[0]	48	1			T279	16		T283	17		T20	15
values[1]	862	1			T25	7		T136	26		T137	6
values[2]	3151	1			T10	2		T12	1		T22	14
values[3]	632	1			T1	2		T3	1		T5	7
values[4]	786	1			T3	1		T11	1		T34	12
values[5]	716	1			T2	10		T9	24		T25	13
values[6]	675	1			T3	1		T8	9		T9	2
values[7]	743	1			T2	4		T23	3		T39	1
values[8]	725	1			T1	1		T2	13		T151	1
values[9]	848	1			T21	13		T141	10		T133	29
minimum	16629	1			T4	20		T6	169		T7	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	754	1			T25	7		T141	7		T136	26
values[1]	3141	1			T10	2		T12	1		T22	14
values[2]	669	1			T1	2		T3	1		T5	7
values[3]	791	1			T3	1		T9	24		T11	1
values[4]	645	1			T2	10		T3	1		T25	13
values[5]	734	1			T2	4		T8	9		T9	2
values[6]	744	1			T23	3		T39	1		T111	1
values[7]	686	1			T1	1		T2	13		T21	13
values[8]	890	1			T141	10		T133	29		T136	13
values[9]	74	1			T13	4		T160	17		T263	14
minimum	17327	1			T4	20		T6	179		T7	14

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22089

1

T1

3

T2

27

T3

3

auto[1]

4366

1

T5

6

T8

4

T9

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T141	7		T136	14		T137	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T25	1		T151	1		T143	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1645	1			T10	2		T12	1		T22	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T111	1		T142	8		T134	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T1	1		T3	1		T12	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T1	1		T5	7		T134	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T139	13		T82	1		T36	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T3	1		T9	13		T11	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T2	1		T138	1		T152	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T3	1		T25	1		T33	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T2	1		T8	5		T9	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T23	14		T86	3		T153	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T23	3		T111	1		T29	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T39	1		T137	12		T140	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T1	1		T2	1		T21	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T152	8		T84	1		T158	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T136	3		T210	1		T140	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T141	10		T133	15		T140	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T13	3		T160	14		T263	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T281	3		T305	1		T288	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16980	1			T4	20		T6	179		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T158	10		T219	1		T30	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T136	12		T152	6		T139	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T25	6		T143	12		T209	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1011	1			T39	15		T167	19		T220	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T134	14		T208	18		T76	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T12	1		T136	4		T29	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T134	12		T208	12		T248	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T82	7		T36	1		T37	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T9	11		T34	6		T35	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T2	9		T152	10		T35	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T25	12		T233	8		T161	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T2	3		T8	4		T9	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T86	7		T77	9		T230	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T29	13		T35	10		T183	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T140	8		T233	9		T72	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T2	12		T21	6		T134	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T152	8		T84	5		T158	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T136	10		T84	5		T86	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T133	14		T140	18		T233	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T13	1		T160	3		T263	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T281	6		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T33	2		T29	2		T209	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T158	8		T219	11		T30	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	481	1			T6	10		T11	2		T21	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T233	1		T168	13		T212	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T279	12		T283	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T20	9		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T136	14		T137	6		T152	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T25	1		T143	1		T158	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1676	1			T10	2		T12	1		T22	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T111	1		T142	8		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T1	1		T3	1		T12	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T1	1		T5	7		T134	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T139	13		T82	1		T270	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T3	1		T11	1		T34	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T2	1		T152	5		T13	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T9	13		T25	1		T34	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T8	5		T9	1		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T3	1		T23	14		T33	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T2	1		T23	3		T111	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T39	1		T137	12		T140	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T1	1		T2	1		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T152	8		T84	1		T230	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T21	7		T136	3		T210	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T141	10		T133	15		T140	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16480	1			T4	20		T6	169		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T13	1		T86	12		T174	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T233	12		T281	6		T307	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T279	4		T283	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T20	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T136	12		T152	6		T209	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T25	6		T143	12		T158	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1033	1			T39	15		T167	19		T220	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T134	14		T208	18		T209	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T12	1		T136	4		T29	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T134	12		T208	12		T38	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T82	7		T37	3		T211	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T34	6		T35	1		T83	26
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T2	9		T152	10		T35	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T9	11		T25	12		T233	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T8	4		T9	1		T209	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T86	7		T77	9		T230	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T2	3		T29	13		T35	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T140	8		T233	9		T72	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T2	12		T134	16		T82	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T152	8		T84	5		T230	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T21	6		T136	10		T84	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T133	14		T140	18		T158	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T33	2		T29	2		T13	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T141	1		T136	13		T137	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T25	7		T151	1		T143	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1346	1			T10	2		T12	1		T22	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T111	1		T142	1		T134	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T1	1		T3	1		T12	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T1	1		T5	1		T134	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T139	1		T82	8		T36	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T3	1		T9	12		T11	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T2	10		T138	1		T152	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T3	1		T25	13		T33	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T2	4		T8	5		T9	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T23	1		T86	8		T153	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T23	1		T111	1		T29	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T39	1		T137	1		T140	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T1	1		T2	13		T21	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T152	9		T84	6		T158	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T136	11		T210	1		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T141	1		T133	16		T140	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T13	4		T160	4		T263	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T281	7		T305	1		T288	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17085	1			T4	20		T6	179		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T158	9		T219	12		T30	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T141	6		T136	13		T137	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T216	1		T147	11		T244	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1310	1			T22	13		T23	13		T39	27
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T142	7		T134	14		T137	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T12	2		T136	14		T72	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T5	6		T134	12		T248	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T139	12		T36	1		T37	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T9	12		T34	4		T83	27
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T152	4		T35	7		T243	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T83	14		T258	12		T221	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T8	4		T158	8		T72	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T23	13		T86	2		T179	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T23	2		T29	17		T35	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T137	11		T140	10		T72	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T21	3		T134	11		T214	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T152	7		T158	7		T197	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T136	2		T140	5		T86	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T141	9		T133	13		T140	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T160	13		T263	6		T232	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T281	2		T288	3		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T159	20		T235	11		T217	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T158	9		T147	2		T245	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	456	1			T6	10		T11	2		T21	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T233	13		T168	1		T212	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T279	5		T283	7		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T20	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T136	13		T137	1		T152	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T25	7		T143	13		T158	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1374	1			T10	2		T12	1		T22	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T111	1		T142	1		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T1	1		T3	1		T12	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T1	1		T5	1		T134	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T139	1		T82	8		T270	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T3	1		T11	1		T34	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T2	10		T152	11		T13	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T9	12		T25	13		T34	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T8	5		T9	2		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T3	1		T23	1		T33	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T2	4		T23	1		T111	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T39	1		T137	1		T140	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T1	1		T2	13		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T152	9		T84	6		T230	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T21	10		T136	11		T210	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T141	1		T133	16		T140	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16629	1			T4	20		T6	169		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T86	13		T174	11		T263	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T168	12		T212	10		T281	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T279	11		T283	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T20	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T136	13		T137	5		T152	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T158	9		T216	1		T147	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1335	1			T22	13		T23	13		T39	27
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T142	7		T134	14		T137	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T12	2		T136	14		T72	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T5	6		T134	12		T38	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T139	12		T37	3		T211	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T34	4		T83	27		T240	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T152	4		T35	7		T36	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T9	12		T83	14		T223	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T8	4		T158	8		T72	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T23	13		T86	2		T179	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T23	2		T29	17		T35	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T137	11		T140	10		T72	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T134	11		T214	2		T107	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T152	7		T197	1		T266	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T21	3		T136	2		T140	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T141	9		T133	13		T140	19

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22089

1

T1

3

T2

27

T3

3

auto[1]

auto[0]

4366

1

T5

6

T8

4

T9

12