Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26455

1

T1

3

T2

27

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22781

1

T1

2

T2

23

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3674

1

T1

1

T2

4

T5

7

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20008

1

T1

1

T3

2

T4

20

auto[1]

6447

1

T1

2

T2

27

T3

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22301

1

T1

3

T2

3

T3

3

auto[1]

4154

1

T2

24

T8

4

T9

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	274	1			T23	14		T39	23		T34	12
values[0]	38	1			T163	1		T16	13		T297	24
values[1]	850	1			T11	1		T21	13		T23	3
values[2]	602	1			T1	1		T2	13		T12	6
values[3]	685	1			T3	2		T12	1		T39	1
values[4]	3102	1			T2	10		T5	7		T10	2
values[5]	573	1			T9	24		T111	1		T136	13
values[6]	575	1			T1	1		T3	1		T8	9
values[7]	646	1			T25	7		T141	7		T29	31
values[8]	896	1			T1	1		T2	4		T34	1
values[9]	1205	1			T9	2		T23	14		T25	13
minimum	17009	1			T4	20		T6	179		T7	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	787	1			T1	1		T33	6		T133	24
values[1]	737	1			T2	13		T12	6		T39	21
values[2]	571	1			T3	2		T12	1		T39	1
values[3]	3040	1			T2	10		T5	7		T10	2
values[4]	646	1			T9	24		T136	13		T134	28
values[5]	559	1			T1	1		T3	1		T8	9
values[6]	727	1			T2	4		T25	7		T34	1
values[7]	903	1			T1	1		T9	2		T134	29
values[8]	969	1			T23	14		T25	13		T136	19
values[9]	236	1			T23	14		T39	23		T34	12
minimum	17280	1			T4	20		T6	179		T7	14

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22089

1

T1

3

T2

27

T3

3

auto[1]

4366

1

T5

6

T8

4

T9

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T1	1		T138	1		T139	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T33	6		T133	12		T142	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T2	1		T12	5		T39	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T151	1		T233	1		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T3	2		T39	1		T133	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T12	1		T111	1		T29	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1643	1			T2	1		T10	2		T22	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T5	7		T111	1		T134	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T9	13		T134	12		T205	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T136	3		T137	6		T208	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T3	1		T8	5		T29	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T1	1		T138	1		T140	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T34	1		T208	1		T209	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T2	1		T25	1		T141	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T1	1		T9	1		T134	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T209	1		T35	11		T84	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	330	1			T209	1		T13	1		T84	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T23	14		T25	1		T136	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T83	15		T247	1		T256	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T23	14		T39	13		T34	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16915	1			T4	20		T6	179		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T11	1		T21	7		T169	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T139	9		T35	4		T83	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T133	12		T72	11		T145	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T2	12		T12	1		T39	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T233	12		T161	19		T89	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T133	2		T36	1		T38	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T29	2		T208	9		T35	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1010	1			T2	9		T167	19		T220	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T134	12		T82	2		T233	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T9	11		T134	16		T76	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T136	10		T208	9		T86	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T8	4		T29	13		T143	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T159	9		T248	13		T146	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T208	12		T209	2		T158	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T2	3		T25	6		T136	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T9	1		T134	14		T140	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T209	15		T35	10		T84	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T209	2		T84	5		T160	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T25	12		T136	4		T152	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T83	13		T308	15		T287	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T39	10		T34	6		T95	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T33	2		T29	2		T13	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T21	6		T244	8		T254	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T209	1		T83	15		T160	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T23	14		T39	13		T34	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T16	5		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T163	1		T297	16		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T23	3		T210	1		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T11	1		T21	7		T33	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T1	1		T2	1		T12	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T151	1		T233	1		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T3	2		T39	1		T133	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T12	1		T111	1		T29	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1622	1			T2	1		T10	2		T22	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T5	7		T134	13		T137	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T9	13		T134	12		T88	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T111	1		T136	3		T137	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T3	1		T8	5		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T1	1		T138	1		T140	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T29	18		T208	1		T209	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T25	1		T141	7		T139	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T1	1		T34	1		T140	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T2	1		T136	14		T209	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	403	1			T9	1		T134	15		T13	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T23	14		T25	1		T136	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16860	1			T4	20		T6	179		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T209	2		T83	13		T160	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T39	10		T34	6		T95	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T16	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T297	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T139	9		T35	4		T83	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T21	6		T133	12		T72	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T2	12		T12	1		T39	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T233	12		T295	5		T156	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T133	2		T152	10		T36	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T29	2		T35	1		T86	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	980	1			T2	9		T167	19		T220	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T134	12		T208	9		T82	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T9	11		T134	16		T214	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T136	10		T208	9		T86	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T8	4		T143	12		T82	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T158	8		T159	9		T146	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T29	13		T208	12		T209	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T25	6		T248	13		T263	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T140	8		T13	1		T158	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T2	3		T136	12		T209	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T9	1		T134	14		T84	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T25	12		T136	4		T152	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T33	2		T29	2		T13	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T1	1		T138	1		T139	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T33	6		T133	13		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T2	13		T12	4		T39	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T151	1		T233	13		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T3	2		T39	1		T133	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T12	1		T111	1		T29	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1350	1			T2	10		T10	2		T22	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T5	1		T111	1		T134	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T9	12		T134	17		T205	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T136	11		T137	1		T208	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T3	1		T8	5		T29	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T1	1		T138	1		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T34	1		T208	13		T209	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T2	4		T25	7		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T1	1		T9	2		T134	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T209	16		T35	12		T84	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T209	3		T13	1		T84	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T23	1		T25	13		T136	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T83	14		T247	1		T256	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T23	1		T39	11		T34	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17096	1			T4	20		T6	179		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T11	1		T21	10		T169	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T139	5		T35	7		T83	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T133	11		T142	7		T72	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T12	2		T39	15		T141	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T168	12		T229	15		T89	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T133	2		T36	1		T38	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T137	11		T86	13		T14	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1303	1			T22	13		T135	34		T228	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T5	6		T134	12		T137	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T9	12		T134	11		T179	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T136	2		T137	5		T86	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T8	4		T29	17		T243	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T140	5		T83	14		T159	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T158	7		T180	9		T77	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T141	6		T136	13		T139	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T134	14		T140	10		T158	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T35	9		T159	10		T240	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T160	11		T225	11		T266	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T23	13		T136	14		T152	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T83	14		T256	7		T308	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T23	13		T39	12		T34	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T23	2		T245	10		T253	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T21	3		T169	11		T244	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T209	3		T83	14		T160	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T23	1		T39	11		T34	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T16	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T163	1		T297	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T23	1		T210	1		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T11	1		T21	10		T33	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T1	1		T2	13		T12	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T151	1		T233	13		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T3	2		T39	1		T133	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T12	1		T111	1		T29	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1320	1			T2	10		T10	2		T22	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T5	1		T134	13		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T9	12		T134	17		T88	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T111	1		T136	11		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T3	1		T8	5		T143	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T1	1		T138	1		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T29	14		T208	13		T209	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T25	7		T141	1		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T1	1		T34	1		T140	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T2	4		T136	13		T209	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	370	1			T9	2		T134	15		T13	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T23	1		T25	13		T136	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17009	1			T4	20		T6	179		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T83	14		T160	11		T256	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T23	13		T39	12		T34	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T16	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T297	15		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T23	2		T139	5		T35	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T21	3		T133	11		T142	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T12	2		T39	15		T141	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T168	12		T229	15		T156	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T133	2		T152	4		T36	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T137	11		T86	13		T14	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1282	1			T22	13		T135	34		T228	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T5	6		T134	12		T137	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T9	12		T134	11		T179	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T136	2		T137	5		T86	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T8	4		T76	12		T77	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T140	5		T83	14		T158	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T29	17		T158	7		T180	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T141	6		T139	12		T258	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T140	10		T158	9		T160	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T136	13		T35	9		T159	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	315	1			T134	14		T225	11		T107	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T23	13		T136	14		T152	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22089

1

T1

3

T2

27

T3

3

auto[1]

auto[0]

4366

1

T5

6

T8

4

T9

12