Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26455

1

T1

3

T2

27

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22951

1

T1

1

T2

4

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3504

1

T1

2

T2

23

T3

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20394

1

T1

2

T2

4

T3

1

auto[1]

6061

1

T1

1

T2

23

T3

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22301

1

T1

3

T2

3

T3

3

auto[1]

4154

1

T2

24

T8

4

T9

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	211	1			T25	7		T86	26		T159	16
values[0]	49	1			T84	6		T261	28		T309	4
values[1]	797	1			T1	1		T2	4		T34	1
values[2]	2950	1			T10	2		T11	1		T22	14
values[3]	654	1			T2	13		T9	2		T39	1
values[4]	745	1			T9	24		T23	28		T140	6
values[5]	736	1			T3	1		T8	9		T33	6
values[6]	810	1			T1	1		T23	3		T141	7
values[7]	712	1			T2	10		T3	1		T21	13
values[8]	579	1			T3	1		T5	7		T12	6
values[9]	1203	1			T1	1		T12	1		T25	13
minimum	17009	1			T4	20		T6	179		T7	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	746	1			T1	1		T2	4		T136	26
values[1]	2978	1			T2	13		T10	2		T11	1
values[2]	668	1			T9	2		T23	28		T34	12
values[3]	668	1			T9	24		T33	6		T151	1
values[4]	714	1			T3	1		T8	9		T23	3
values[5]	895	1			T1	1		T3	1		T39	44
values[6]	674	1			T2	10		T5	7		T21	13
values[7]	680	1			T3	1		T12	6		T137	12
values[8]	979	1			T1	1		T12	1		T25	20
values[9]	174	1			T215	11		T262	10		T229	10
minimum	17279	1			T4	20		T6	179		T7	14

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22089

1

T1

3

T2

27

T3

3

auto[1]

4366

1

T5

6

T8

4

T9

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T2	1		T136	14		T209	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T1	1		T139	6		T13	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1684	1			T10	2		T22	14		T39	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T2	1		T11	1		T210	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T9	1		T23	14		T34	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T23	14		T29	18		T208	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T9	13		T214	3		T170	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T33	6		T151	1		T140	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T8	5		T23	3		T133	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T3	1		T111	1		T134	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T39	29		T141	7		T111	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T1	1		T3	1		T142	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T5	7		T140	11		T13	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T2	1		T21	7		T136	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T3	1		T154	1		T77	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T12	5		T137	12		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T1	1		T12	1		T141	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	346	1			T25	2		T137	6		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T262	10		T229	10		T263	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T215	1		T256	6		T176	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16900	1			T4	20		T6	179		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T134	13		T244	13		T295	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T2	3		T136	12		T209	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T139	9		T13	1		T35	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1039	1			T167	19		T133	2		T29	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T2	12		T152	10		T36	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T9	1		T34	6		T35	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T29	13		T208	9		T158	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T9	11		T214	4		T170	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T219	11		T38	2		T107	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T8	4		T133	12		T86	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T134	14		T152	8		T233	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T39	15		T136	4		T134	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T35	10		T160	10		T72	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T140	8		T84	5		T158	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T2	9		T21	6		T136	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T77	1		T146	9		T156	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T12	1		T208	12		T140	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T152	6		T107	8		T162	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T25	18		T86	12		T233	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T263	7		T264	9		T301	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T215	10		T176	14		T310	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T33	2		T29	2		T209	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T134	12		T244	11		T295	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T206	1		T262	10		T229	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T25	1		T86	14		T159	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T84	1		T261	15		T18	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T309	1		T265	8		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T2	1		T34	1		T136	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T1	1		T134	13		T139	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1663	1			T10	2		T22	14		T167	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T11	1		T152	5		T36	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T9	1		T39	1		T34	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T2	1		T29	18		T210	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T9	13		T23	14		T83	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T23	14		T140	6		T219	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T8	5		T133	12		T137	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T3	1		T33	6		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T23	3		T141	7		T111	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T1	1		T111	1		T142	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T39	29		T139	13		T140	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T2	1		T3	1		T21	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T3	1		T5	7		T84	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T12	5		T137	12		T138	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T1	1		T12	1		T141	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	360	1			T25	1		T137	6		T140	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16860	1			T4	20		T6	179		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T311	9		T312	11		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T25	6		T86	12		T159	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T84	5		T261	13		T18	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T309	3		T265	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T2	3		T136	12		T209	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T134	12		T139	9		T13	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1018	1			T167	19		T133	2		T29	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T152	10		T36	1		T146	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T9	1		T34	6		T209	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T2	12		T29	13		T208	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T9	11		T83	13		T214	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T219	11		T281	11		T313	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T8	4		T133	12		T86	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T134	14		T152	8		T38	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T136	4		T134	16		T158	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T35	10		T233	12		T72	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T39	15		T140	8		T158	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T2	9		T21	6		T136	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T84	5		T77	1		T156	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T12	1		T208	12		T233	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T152	6		T107	8		T162	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T25	12		T140	18		T82	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T33	2		T29	2		T13	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T2	4		T136	13		T209	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T1	1		T139	10		T13	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1384	1			T10	2		T22	1		T39	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T2	13		T11	1		T210	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T9	2		T23	1		T34	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T23	1		T29	14		T208	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T9	12		T214	5		T170	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T33	6		T151	1		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T8	5		T23	1		T133	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T3	1		T111	1		T134	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T39	17		T141	1		T111	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T1	1		T3	1		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T5	1		T140	9		T13	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T2	10		T21	10		T136	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T3	1		T154	1		T77	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T12	4		T137	1		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T1	1		T12	1		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	373	1			T25	20		T137	1		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T262	1		T229	1		T263	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T215	11		T256	1		T176	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17089	1			T4	20		T6	179		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T134	13		T244	12		T295	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T136	13		T72	15		T77	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T139	5		T35	7		T146	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1339	1			T22	13		T135	34		T133	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T152	4		T36	1		T78	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T23	13		T34	4		T83	27
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T23	13		T29	17		T158	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T9	12		T214	2		T170	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T140	5		T38	3		T107	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T8	4		T23	2		T133	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T134	14		T152	7		T211	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T39	27		T141	6		T136	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T142	7		T35	9		T160	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T5	6		T140	10		T158	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T21	3		T136	2		T78	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T168	12		T146	10		T267	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T12	2		T137	11		T140	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T141	9		T152	7		T107	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T137	5		T86	13		T160	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T262	9		T229	9		T263	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T256	5		T176	16		T310	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T261	14		T231	2		T16	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T134	12		T244	12		T260	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T206	1		T262	1		T229	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T25	7		T86	13		T159	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T84	6		T261	14		T18	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T309	4		T265	5		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T2	4		T34	1		T136	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T1	1		T134	13		T139	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1360	1			T10	2		T22	1		T167	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T11	1		T152	11		T36	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T9	2		T39	1		T34	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T2	13		T29	14		T210	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T9	12		T23	1		T83	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T23	1		T140	1		T219	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T8	5		T133	13		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T3	1		T33	6		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T23	1		T141	1		T111	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T1	1		T111	1		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T39	17		T139	1		T140	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T2	10		T3	1		T21	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T3	1		T5	1		T84	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T12	4		T137	1		T138	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T1	1		T12	1		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	407	1			T25	13		T137	1		T140	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17009	1			T4	20		T6	179		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T262	9		T229	9		T311	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T86	13		T159	7		T155	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T261	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T265	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T136	13		T72	15		T77	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T134	12		T139	5		T35	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1321	1			T22	13		T135	34		T133	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T152	4		T36	1		T240	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T34	4		T83	14		T223	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T29	17		T158	8		T78	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T9	12		T23	13		T83	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T23	13		T140	5		T162	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T8	4		T133	11		T137	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T134	14		T152	7		T38	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T23	2		T141	6		T136	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T142	7		T35	9		T72	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T39	27		T139	12		T140	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T21	3		T136	2		T160	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T5	6		T168	12		T267	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T12	2		T137	11		T180	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T141	9		T152	7		T107	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T137	5		T140	19		T160	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22089

1

T1

3

T2

27

T3

3

auto[1]

auto[0]

4366

1

T5

6

T8

4

T9

12