Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26455

1

T1

3

T2

27

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20546

1

T1

2

T2

13

T3

2

auto[ADC_CTRL_FILTER_COND_OUT]

5909

1

T1

1

T2

14

T3

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20016

1

T1

2

T2

13

T3

1

auto[1]

6439

1

T1

1

T2

14

T3

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22301

1

T1

3

T2

3

T3

3

auto[1]

4154

1

T2

24

T8

4

T9

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	248	1			T11	1		T141	10		T136	19
values[0]	66	1			T244	24		T306	9		T314	13
values[1]	653	1			T1	1		T2	13		T3	1
values[2]	801	1			T9	2		T12	6		T142	8
values[3]	606	1			T1	1		T209	3		T140	6
values[4]	735	1			T3	1		T12	1		T23	14
values[5]	719	1			T1	1		T21	13		T23	14
values[6]	573	1			T25	7		T34	12		T137	12
values[7]	745	1			T2	14		T8	9		T34	1
values[8]	728	1			T3	1		T9	24		T39	21
values[9]	3572	1			T5	7		T10	2		T22	14
minimum	17009	1			T4	20		T6	179		T7	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	644	1			T1	1		T2	13		T25	13
values[1]	3023	1			T9	2		T10	2		T12	6
values[2]	640	1			T1	1		T3	1		T209	3
values[3]	822	1			T12	1		T23	14		T141	7
values[4]	528	1			T1	1		T21	13		T23	14
values[5]	640	1			T2	10		T25	7		T137	12
values[6]	807	1			T2	4		T8	9		T34	1
values[7]	779	1			T3	1		T9	24		T39	21
values[8]	1156	1			T5	7		T23	3		T141	10
values[9]	102	1			T11	1		T258	13		T107	16
minimum	17314	1			T3	1		T4	20		T6	179

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22089

1

T1

3

T2

27

T3

3

auto[1]

4366

1

T5

6

T8

4

T9

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T2	1		T39	1		T139	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T1	1		T25	1		T144	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T9	1		T142	8		T140	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1637	1			T10	2		T12	5		T22	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T1	1		T3	1		T209	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T36	4		T243	12		T89	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T111	1		T210	1		T140	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T12	1		T23	14		T141	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T1	1		T23	14		T33	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T21	7		T134	12		T88	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T25	1		T35	1		T154	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T2	1		T137	12		T208	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T8	5		T151	2		T158	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T2	1		T34	1		T133	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T3	1		T39	16		T29	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T9	13		T111	1		T137	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	356	1			T5	7		T23	3		T141	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T133	12		T134	15		T209	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T11	1		T258	13		T186	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T107	1		T298	5		T315	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16950	1			T4	20		T6	179		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T3	1		T39	13		T208	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T2	12		T139	9		T233	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T25	12		T102	12		T146	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T9	1		T35	10		T86	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1022	1			T12	1		T167	19		T136	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T209	2		T160	3		T38	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T36	1		T243	4		T89	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T140	18		T183	9		T78	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T29	13		T72	7		T219	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T34	6		T159	9		T162	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T21	6		T134	16		T233	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T25	6		T35	1		T219	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T2	9		T208	12		T13	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T8	4		T158	7		T72	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T2	3		T133	2		T143	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T39	5		T29	2		T152	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T9	11		T209	2		T230	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T136	16		T152	18		T208	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T133	12		T134	14		T209	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T186	16		T316	2		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T107	15		T298	9		T317	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T33	2		T134	12		T29	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T39	10		T208	9		T290	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T11	1		T141	10		T136	15
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T107	1		T298	5		T303	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T244	13		T306	5		T292	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T314	1		T318	1		T17	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T2	1		T39	1		T134	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T1	1		T3	1		T25	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T9	1		T142	8		T86	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T12	5		T136	3		T139	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T1	1		T209	1		T140	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T36	4		T214	3		T243	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T3	1		T111	1		T210	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T12	1		T23	14		T29	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T1	1		T23	14		T33	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T21	7		T141	7		T134	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T25	1		T34	6		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T137	12		T13	4		T205	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T8	5		T151	1		T35	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T2	2		T34	1		T133	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T3	1		T39	16		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T9	13		T111	1		T209	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	361	1			T5	7		T23	3		T136	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1768	1			T10	2		T22	14		T167	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16860	1			T4	20		T6	179		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T136	4		T208	9		T197	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T107	15		T298	9		T303	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T244	11		T306	4		T292	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T314	12		T17	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T2	12		T134	12		T139	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T25	12		T39	10		T208	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T9	1		T86	12		T233	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T12	1		T136	10		T158	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T209	2		T35	10		T38	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T36	1		T214	4		T243	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T140	18		T160	3		T161	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T29	13		T72	7		T219	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T183	9		T159	9		T162	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T21	6		T134	16		T233	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T25	6		T34	6		T230	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T13	1		T159	8		T188	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T8	4		T35	1		T219	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T2	12		T133	2		T208	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T39	5		T29	2		T152	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T9	11		T209	2		T84	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	327	1			T136	12		T152	18		T140	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1116	1			T167	19		T133	12		T134	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T33	2		T29	2		T13	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T2	13		T39	1		T139	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T1	1		T25	13		T144	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T9	2		T142	1		T140	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1367	1			T10	2		T12	4		T22	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T1	1		T3	1		T209	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T36	4		T243	5		T89	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T111	1		T210	1		T140	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T12	1		T23	1		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T1	1		T23	1		T33	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T21	10		T134	17		T88	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T25	7		T35	2		T154	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T2	10		T137	1		T208	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T8	5		T151	2		T158	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T2	4		T34	1		T133	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T3	1		T39	6		T29	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T9	12		T111	1		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	372	1			T5	1		T23	1		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T133	13		T134	15		T209	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T11	1		T258	1		T186	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T107	16		T298	10		T315	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17121	1			T4	20		T6	179		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T3	1		T39	11		T208	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T139	5		T160	11		T258	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T168	19		T229	24		T146	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T142	7		T140	5		T35	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1292	1			T12	2		T22	13		T135	34
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T160	13		T38	1		T168	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T36	1		T243	11		T148	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T140	19		T78	1		T14	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T23	13		T141	6		T29	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T23	13		T34	4		T159	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T21	3		T134	11		T174	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T216	1		T169	11		T147	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T137	11		T159	17		T162	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T8	4		T158	7		T72	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T133	2		T83	28		T86	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T39	15		T152	7		T158	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T9	12		T137	12		T78	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T5	6		T23	2		T141	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T133	11		T134	14		T37	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T258	12		T186	16		T316	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T298	4		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T134	12		T38	3		T155	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T39	12		T266	1		T319	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T11	1		T141	1		T136	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T107	16		T298	10		T303	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T244	12		T306	5		T292	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T314	13		T318	1		T17	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T2	13		T39	1		T134	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T1	1		T3	1		T25	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T9	2		T142	1		T86	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T12	4		T136	11		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T1	1		T209	3		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T36	4		T214	5		T243	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T3	1		T111	1		T210	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T12	1		T23	1		T29	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T1	1		T23	1		T33	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T21	10		T141	1		T134	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T25	7		T34	8		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T137	1		T13	5		T205	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T8	5		T151	1		T35	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T2	14		T34	1		T133	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T3	1		T39	6		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T9	12		T111	1		T209	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	394	1			T5	1		T23	1		T136	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1486	1			T10	2		T22	1		T167	21
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17009	1			T4	20		T6	179		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T141	9		T136	14		T197	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T298	4		T303	11		T319	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T244	12		T306	4		T292	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T17	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T134	12		T139	5		T160	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T39	12		T168	19		T229	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T142	7		T86	13		T258	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T12	2		T136	2		T139	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T140	5		T35	9		T38	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T36	1		T214	2		T243	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T140	19		T160	13		T78	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T23	13		T29	17		T72	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T23	13		T159	10		T162	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T21	3		T141	6		T134	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T34	4		T216	1		T169	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T137	11		T159	7		T162	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T8	4		T170	6		T147	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T133	2		T83	28		T86	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T39	15		T152	7		T158	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T9	12		T14	2		T261	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T5	6		T23	2		T136	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1398	1			T22	13		T135	34		T133	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22089

1

T1

3

T2

27

T3

3

auto[1]

auto[0]

4366

1

T5

6

T8

4

T9

12