CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 26455 | 1 | T1 | 3 | T2 | 27 | T3 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[ADC_CTRL_FILTER_COND_IN] | 20600 | 1 | T1 | 1 | T2 | 13 | T3 | 2 | ||||
auto[ADC_CTRL_FILTER_COND_OUT] | 5855 | 1 | T1 | 2 | T2 | 14 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 20043 | 1 | T1 | 1 | T2 | 13 | T3 | 1 | ||||
auto[1] | 6412 | 1 | T1 | 2 | T2 | 14 | T3 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 22301 | 1 | T1 | 3 | T2 | 3 | T3 | 3 | ||||
auto[1] | 4154 | 1 | T2 | 24 | T8 | 4 | T9 | 12 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 12 | 0 | 12 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
maximum | 26 | 1 | T232 | 5 | T320 | 9 | T321 | 12 | ||||
values[0] | 93 | 1 | T38 | 6 | T175 | 10 | T306 | 9 | ||||
values[1] | 659 | 1 | T1 | 1 | T2 | 13 | T3 | 1 | ||||
values[2] | 752 | 1 | T9 | 2 | T12 | 6 | T136 | 13 | ||||
values[3] | 659 | 1 | T1 | 1 | T29 | 31 | T209 | 3 | ||||
values[4] | 709 | 1 | T3 | 1 | T21 | 13 | T23 | 14 | ||||
values[5] | 711 | 1 | T1 | 1 | T12 | 1 | T23 | 14 | ||||
values[6] | 578 | 1 | T25 | 7 | T34 | 13 | T137 | 12 | ||||
values[7] | 721 | 1 | T2 | 14 | T8 | 9 | T133 | 5 | ||||
values[8] | 771 | 1 | T3 | 1 | T9 | 24 | T39 | 21 | ||||
values[9] | 3767 | 1 | T5 | 7 | T10 | 2 | T11 | 1 | ||||
minimum | 17009 | 1 | T4 | 20 | T6 | 179 | T7 | 14 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 12 | 1 | 11 | 91.67 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
maximum | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 922 | 1 | T1 | 1 | T2 | 13 | T3 | 1 | ||||
values[1] | 2999 | 1 | T9 | 2 | T10 | 2 | T12 | 6 | ||||
values[2] | 636 | 1 | T1 | 1 | T3 | 1 | T209 | 3 | ||||
values[3] | 811 | 1 | T12 | 1 | T23 | 14 | T141 | 7 | ||||
values[4] | 565 | 1 | T1 | 1 | T21 | 13 | T23 | 14 | ||||
values[5] | 669 | 1 | T2 | 10 | T25 | 7 | T34 | 12 | ||||
values[6] | 728 | 1 | T2 | 4 | T8 | 9 | T39 | 21 | ||||
values[7] | 848 | 1 | T3 | 1 | T9 | 24 | T111 | 1 | ||||
values[8] | 1090 | 1 | T5 | 7 | T23 | 3 | T141 | 10 | ||||
values[9] | 138 | 1 | T11 | 1 | T133 | 24 | T258 | 13 | ||||
minimum | 17049 | 1 | T4 | 20 | T6 | 179 | T7 | 14 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 22089 | 1 | T1 | 3 | T2 | 27 | T3 | 3 | ||||
auto[1] | 4366 | 1 | T5 | 6 | T8 | 4 | T9 | 12 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 48 | 4 | 44 | 91.67 | 4 |
interrupt_cp | min_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
* | [maximum] | * | -- | -- | 4 |
interrupt_cp | min_v_cp | cond_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 248 | 1 | T2 | 1 | T39 | 1 | T142 | 8 | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 258 | 1 | T1 | 1 | T3 | 1 | T25 | 1 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 213 | 1 | T9 | 1 | T140 | 6 | T35 | 11 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 1614 | 1 | T10 | 2 | T12 | 5 | T22 | 14 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 188 | 1 | T1 | 1 | T3 | 1 | T209 | 1 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 169 | 1 | T36 | 4 | T89 | 1 | T148 | 10 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 199 | 1 | T111 | 1 | T210 | 1 | T140 | 20 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 266 | 1 | T12 | 1 | T23 | 14 | T141 | 7 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 175 | 1 | T23 | 14 | T33 | 6 | T138 | 1 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 145 | 1 | T1 | 1 | T21 | 7 | T134 | 12 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 136 | 1 | T25 | 1 | T34 | 6 | T151 | 1 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 219 | 1 | T2 | 1 | T137 | 12 | T208 | 1 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 170 | 1 | T8 | 5 | T39 | 16 | T151 | 1 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 259 | 1 | T2 | 1 | T34 | 1 | T133 | 3 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 268 | 1 | T3 | 1 | T29 | 1 | T152 | 8 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 232 | 1 | T9 | 13 | T111 | 1 | T137 | 13 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 347 | 1 | T5 | 7 | T23 | 3 | T141 | 10 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 233 | 1 | T134 | 15 | T209 | 1 | T84 | 1 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 48 | 1 | T11 | 1 | T258 | 13 | T186 | 17 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 31 | 1 | T133 | 12 | T148 | 11 | T298 | 5 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 16876 | 1 | T4 | 20 | T6 | 179 | T7 | 14 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_OUT] | 7 | 1 | T260 | 6 | T250 | 1 | - | - | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 210 | 1 | T2 | 12 | T134 | 12 | T139 | 9 | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 206 | 1 | T25 | 12 | T39 | 10 | T208 | 9 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 157 | 1 | T9 | 1 | T35 | 10 | T86 | 12 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 1015 | 1 | T12 | 1 | T167 | 19 | T136 | 10 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 143 | 1 | T209 | 2 | T160 | 3 | T38 | 1 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 136 | 1 | T36 | 1 | T89 | 1 | T148 | 10 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 184 | 1 | T140 | 18 | T183 | 9 | T78 | 10 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 162 | 1 | T29 | 13 | T72 | 7 | T219 | 10 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 96 | 1 | T159 | 9 | T162 | 10 | T174 | 12 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 149 | 1 | T21 | 6 | T134 | 16 | T233 | 9 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 133 | 1 | T25 | 6 | T34 | 6 | T35 | 1 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 181 | 1 | T2 | 9 | T208 | 12 | T13 | 1 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 107 | 1 | T8 | 4 | T39 | 5 | T158 | 7 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 192 | 1 | T2 | 3 | T133 | 2 | T143 | 12 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 222 | 1 | T29 | 2 | T152 | 6 | T82 | 2 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 126 | 1 | T9 | 11 | T209 | 2 | T230 | 5 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 289 | 1 | T136 | 16 | T152 | 18 | T208 | 9 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 221 | 1 | T134 | 14 | T209 | 15 | T84 | 5 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 29 | 1 | T186 | 16 | T93 | 8 | T292 | 3 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 30 | 1 | T133 | 12 | T148 | 2 | T298 | 9 | ||||
auto[1] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 162 | 1 | T33 | 2 | T29 | 2 | T13 | 1 | ||||
auto[1] | minimum | auto[ADC_CTRL_FILTER_COND_OUT] | 4 | 1 | T260 | 4 | - | - | - | - |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 48 | 2 | 46 | 95.83 | 2 |
interrupt_cp | max_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
* | [minimum] | [auto[ADC_CTRL_FILTER_COND_OUT]] | -- | -- | 2 |
interrupt_cp | max_v_cp | cond_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | maximum | auto[ADC_CTRL_FILTER_COND_IN] | 6 | 1 | T320 | 6 | - | - | - | - | ||||
auto[0] | maximum | auto[ADC_CTRL_FILTER_COND_OUT] | 12 | 1 | T232 | 5 | T321 | 7 | - | - | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 39 | 1 | T38 | 4 | T306 | 5 | T301 | 10 | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 13 | 1 | T175 | 1 | T314 | 1 | T322 | 7 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 188 | 1 | T2 | 1 | T39 | 1 | T142 | 8 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 161 | 1 | T1 | 1 | T3 | 1 | T25 | 1 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 222 | 1 | T9 | 1 | T35 | 11 | T86 | 14 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 195 | 1 | T12 | 5 | T136 | 3 | T139 | 13 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 155 | 1 | T1 | 1 | T209 | 1 | T140 | 6 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 210 | 1 | T29 | 18 | T36 | 4 | T223 | 15 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 196 | 1 | T3 | 1 | T111 | 1 | T210 | 1 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 224 | 1 | T21 | 7 | T23 | 14 | T138 | 1 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 211 | 1 | T23 | 14 | T33 | 6 | T138 | 1 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 184 | 1 | T1 | 1 | T12 | 1 | T141 | 7 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 151 | 1 | T25 | 1 | T34 | 6 | T154 | 2 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 185 | 1 | T34 | 1 | T137 | 12 | T13 | 4 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 128 | 1 | T8 | 5 | T151 | 1 | T35 | 1 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 281 | 1 | T2 | 2 | T133 | 3 | T208 | 1 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 291 | 1 | T3 | 1 | T39 | 16 | T151 | 1 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 158 | 1 | T9 | 13 | T111 | 1 | T209 | 1 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 421 | 1 | T5 | 7 | T11 | 1 | T23 | 3 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 1810 | 1 | T10 | 2 | T22 | 14 | T167 | 2 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 16860 | 1 | T4 | 20 | T6 | 179 | T7 | 14 | ||||
auto[1] | maximum | auto[ADC_CTRL_FILTER_COND_IN] | 3 | 1 | T320 | 3 | - | - | - | - | ||||
auto[1] | maximum | auto[ADC_CTRL_FILTER_COND_OUT] | 5 | 1 | T321 | 5 | - | - | - | - | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 13 | 1 | T38 | 2 | T306 | 4 | T301 | 2 | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 28 | 1 | T175 | 9 | T314 | 12 | T322 | 6 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 174 | 1 | T2 | 12 | T134 | 12 | T139 | 9 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 136 | 1 | T25 | 12 | T39 | 10 | T208 | 9 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 183 | 1 | T9 | 1 | T35 | 10 | T86 | 12 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 152 | 1 | T12 | 1 | T136 | 10 | T158 | 8 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 121 | 1 | T209 | 2 | T38 | 1 | T243 | 4 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 173 | 1 | T29 | 13 | T36 | 1 | T223 | 12 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 152 | 1 | T140 | 18 | T160 | 3 | T161 | 15 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 137 | 1 | T21 | 6 | T72 | 7 | T211 | 3 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 141 | 1 | T183 | 9 | T159 | 9 | T162 | 10 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 175 | 1 | T134 | 16 | T233 | 9 | T107 | 8 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 134 | 1 | T25 | 6 | T34 | 6 | T230 | 1 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 108 | 1 | T13 | 1 | T159 | 19 | T188 | 8 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 76 | 1 | T8 | 4 | T35 | 1 | T219 | 11 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 236 | 1 | T2 | 12 | T133 | 2 | T208 | 12 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 236 | 1 | T39 | 5 | T29 | 2 | T152 | 6 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 86 | 1 | T9 | 11 | T209 | 2 | T84 | 5 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 350 | 1 | T136 | 16 | T152 | 18 | T208 | 9 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 1186 | 1 | T167 | 19 | T133 | 12 | T134 | 14 | ||||
auto[1] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 149 | 1 | T33 | 2 | T29 | 2 | T13 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 48 | 4 | 44 | 91.67 | 4 |
wakeup_cp | min_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
* | [maximum] | * | -- | -- | 4 |
wakeup_cp | min_v_cp | cond_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 252 | 1 | T2 | 13 | T39 | 1 | T142 | 1 | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 262 | 1 | T1 | 1 | T3 | 1 | T25 | 13 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 199 | 1 | T9 | 2 | T140 | 1 | T35 | 12 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 1356 | 1 | T10 | 2 | T12 | 4 | T22 | 1 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 184 | 1 | T1 | 1 | T3 | 1 | T209 | 3 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 168 | 1 | T36 | 4 | T89 | 2 | T148 | 11 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 231 | 1 | T111 | 1 | T210 | 1 | T140 | 19 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 198 | 1 | T12 | 1 | T23 | 1 | T141 | 1 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 133 | 1 | T23 | 1 | T33 | 6 | T138 | 1 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 183 | 1 | T1 | 1 | T21 | 10 | T134 | 17 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 170 | 1 | T25 | 7 | T34 | 8 | T151 | 1 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 219 | 1 | T2 | 10 | T137 | 1 | T208 | 13 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 138 | 1 | T8 | 5 | T39 | 6 | T151 | 1 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 239 | 1 | T2 | 4 | T34 | 1 | T133 | 3 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 263 | 1 | T3 | 1 | T29 | 3 | T152 | 7 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 164 | 1 | T9 | 12 | T111 | 1 | T137 | 1 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 355 | 1 | T5 | 1 | T23 | 1 | T141 | 1 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 273 | 1 | T134 | 15 | T209 | 16 | T84 | 6 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 36 | 1 | T11 | 1 | T258 | 1 | T186 | 17 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 35 | 1 | T133 | 13 | T148 | 3 | T298 | 10 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 17025 | 1 | T4 | 20 | T6 | 179 | T7 | 14 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_OUT] | 6 | 1 | T260 | 5 | T250 | 1 | - | - | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 206 | 1 | T142 | 7 | T134 | 12 | T139 | 5 | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 202 | 1 | T39 | 12 | T139 | 12 | T168 | 7 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 171 | 1 | T140 | 5 | T35 | 9 | T86 | 13 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 1273 | 1 | T12 | 2 | T22 | 13 | T135 | 34 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 147 | 1 | T160 | 13 | T38 | 1 | T243 | 11 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 137 | 1 | T36 | 1 | T148 | 9 | T267 | 18 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 152 | 1 | T140 | 19 | T78 | 1 | T14 | 1 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 230 | 1 | T23 | 13 | T141 | 6 | T29 | 17 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 138 | 1 | T23 | 13 | T159 | 10 | T162 | 11 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 111 | 1 | T21 | 3 | T134 | 11 | T221 | 8 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 99 | 1 | T34 | 4 | T216 | 1 | T169 | 11 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 181 | 1 | T137 | 11 | T159 | 17 | T162 | 15 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 139 | 1 | T8 | 4 | T39 | 15 | T158 | 7 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 212 | 1 | T133 | 2 | T83 | 28 | T86 | 2 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 227 | 1 | T152 | 7 | T158 | 9 | T179 | 6 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 194 | 1 | T9 | 12 | T137 | 12 | T78 | 9 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 281 | 1 | T5 | 6 | T23 | 2 | T141 | 9 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 181 | 1 | T134 | 14 | T37 | 3 | T169 | 16 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 41 | 1 | T258 | 12 | T186 | 16 | T292 | 6 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 26 | 1 | T133 | 11 | T148 | 10 | T298 | 4 | ||||
auto[1] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 13 | 1 | T306 | 4 | T213 | 9 | - | - | ||||
auto[1] | minimum | auto[ADC_CTRL_FILTER_COND_OUT] | 5 | 1 | T260 | 5 | - | - | - | - |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 48 | 3 | 45 | 93.75 | 3 |
wakeup_cp | max_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] | [minimum] | * | -- | -- | 2 |
wakeup_cp | max_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[0]] | [minimum] | [auto[ADC_CTRL_FILTER_COND_OUT]] | 0 | 1 | 1 |
wakeup_cp | max_v_cp | cond_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | maximum | auto[ADC_CTRL_FILTER_COND_IN] | 6 | 1 | T320 | 6 | - | - | - | - | ||||
auto[0] | maximum | auto[ADC_CTRL_FILTER_COND_OUT] | 7 | 1 | T232 | 1 | T321 | 6 | - | - | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 19 | 1 | T38 | 3 | T306 | 5 | T301 | 3 | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 33 | 1 | T175 | 10 | T314 | 13 | T322 | 7 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 209 | 1 | T2 | 13 | T39 | 1 | T142 | 1 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 174 | 1 | T1 | 1 | T3 | 1 | T25 | 13 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 219 | 1 | T9 | 2 | T35 | 12 | T86 | 13 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 195 | 1 | T12 | 4 | T136 | 11 | T139 | 1 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 162 | 1 | T1 | 1 | T209 | 3 | T140 | 1 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 208 | 1 | T29 | 14 | T36 | 4 | T223 | 13 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 202 | 1 | T3 | 1 | T111 | 1 | T210 | 1 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 171 | 1 | T21 | 10 | T23 | 1 | T138 | 1 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 179 | 1 | T23 | 1 | T33 | 6 | T138 | 1 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 212 | 1 | T1 | 1 | T12 | 1 | T141 | 1 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 167 | 1 | T25 | 7 | T34 | 8 | T154 | 2 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 139 | 1 | T34 | 1 | T137 | 1 | T13 | 5 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 106 | 1 | T8 | 5 | T151 | 1 | T35 | 2 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 287 | 1 | T2 | 14 | T133 | 3 | T208 | 13 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 285 | 1 | T3 | 1 | T39 | 6 | T151 | 1 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 111 | 1 | T9 | 12 | T111 | 1 | T209 | 3 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 423 | 1 | T5 | 1 | T11 | 1 | T23 | 1 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 1566 | 1 | T10 | 2 | T22 | 1 | T167 | 21 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 17009 | 1 | T4 | 20 | T6 | 179 | T7 | 14 | ||||
auto[1] | maximum | auto[ADC_CTRL_FILTER_COND_IN] | 3 | 1 | T320 | 3 | - | - | - | - | ||||
auto[1] | maximum | auto[ADC_CTRL_FILTER_COND_OUT] | 10 | 1 | T232 | 4 | T321 | 6 | - | - | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 33 | 1 | T38 | 3 | T306 | 4 | T301 | 9 | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 8 | 1 | T322 | 6 | T17 | 2 | - | - | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 153 | 1 | T142 | 7 | T134 | 12 | T139 | 5 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 123 | 1 | T39 | 12 | T168 | 7 | T229 | 15 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 186 | 1 | T35 | 9 | T86 | 13 | T258 | 11 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 152 | 1 | T12 | 2 | T136 | 2 | T139 | 12 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 114 | 1 | T140 | 5 | T38 | 1 | T243 | 11 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 175 | 1 | T29 | 17 | T36 | 1 | T223 | 14 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 146 | 1 | T140 | 19 | T160 | 13 | T78 | 1 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 190 | 1 | T21 | 3 | T23 | 13 | T72 | 7 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 173 | 1 | T23 | 13 | T159 | 10 | T162 | 11 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 147 | 1 | T141 | 6 | T134 | 11 | T107 | 7 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 118 | 1 | T34 | 4 | T216 | 1 | T174 | 11 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 154 | 1 | T137 | 11 | T159 | 17 | T162 | 15 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 98 | 1 | T8 | 4 | T179 | 6 | T170 | 6 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 230 | 1 | T133 | 2 | T83 | 14 | T86 | 2 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 242 | 1 | T39 | 15 | T152 | 7 | T158 | 16 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 133 | 1 | T9 | 12 | T83 | 14 | T261 | 14 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 348 | 1 | T5 | 6 | T23 | 2 | T141 | 9 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 1430 | 1 | T22 | 13 | T135 | 34 | T133 | 11 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 4 | 2 | 2 | 50.00 | 2 |
wakeup_cp | clk_gate_cp | COUNT | AT LEAST | NUMBER | STATUS |
* | [auto[1]] | -- | -- | 2 |
wakeup_cp | clk_gate_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | auto[0] | 22089 | 1 | T1 | 3 | T2 | 27 | T3 | 3 | ||||
auto[1] | auto[0] | 4366 | 1 | T5 | 6 | T8 | 4 | T9 | 12 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |