Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T1	1		T208	13		T139	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T11	1		T141	1		T29	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T3	3		T138	1		T209	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T2	4		T9	2		T33	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T23	1		T136	24		T209	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T25	7		T111	1		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1314	1			T1	1		T5	1		T8	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T151	1		T134	15		T35	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T1	1		T23	1		T39	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T136	5		T134	13		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T2	10		T25	13		T39	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T12	1		T13	4		T153	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T2	13		T23	1		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T141	1		T152	9		T84	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T142	1		T144	1		T160	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T39	6		T83	14		T158	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T21	10		T210	1		T208	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T9	12		T29	3		T208	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T12	4		T34	1		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T133	13		T159	12		T145	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17022	1			T4	20		T6	179		T7	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T139	12		T159	7		T155	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T141	6		T29	17		T152	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T86	2		T72	7		T37	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T107	17		T224	19		T239	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T23	2		T136	15		T168	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T137	11		T158	7		T36	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1266	1			T5	6		T8	4		T22	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T134	14		T35	7		T240	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T23	13		T152	4		T159	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T136	14		T134	12		T137	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T39	12		T34	4		T133	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T147	21		T235	11		T212	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T23	13		T134	11		T140	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T141	9		T152	7		T179	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T142	7		T160	13		T216	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T39	15		T83	14		T158	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T21	3		T140	5		T158	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T9	12		T139	5		T168	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T12	2		T137	5		T83	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T133	11		T159	10		T241	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T227	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T208	13		T146	13		T234	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T141	1		T13	1		T174	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T3	1		T139	1		T159	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T29	14		T152	7		T35	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T1	1		T3	2		T209	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T9	2		T11	1		T33	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T23	1		T136	24		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T2	4		T25	7		T158	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T1	2		T8	5		T140	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T111	1		T151	1		T134	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1388	1			T5	1		T10	2		T22	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T136	5		T134	13		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	335	1			T39	12		T34	8		T133	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T147	1		T235	1		T236	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T2	10		T25	13		T134	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T12	1		T141	1		T13	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T2	13		T21	10		T23	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T152	9		T158	9		T179	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T12	4		T34	1		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	408	1			T9	12		T39	6		T133	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17009	1			T4	20		T6	179		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T227	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T234	7		T237	13		T242	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T141	6		T174	11		T237	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T139	12		T159	7		T155	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T29	17		T152	7		T35	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T37	3		T38	3		T78	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T224	19		T146	9		T239	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T23	2		T136	15		T86	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T158	7		T36	1		T243	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T8	4		T140	10		T244	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T134	14		T137	11		T35	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1332	1			T5	6		T22	13		T23	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T136	14		T134	12		T137	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T39	12		T34	4		T133	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T147	21		T235	11		T245	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T134	11		T140	19		T83	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T141	9		T38	1		T78	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T21	3		T23	13		T142	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T152	7		T158	8		T179	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T12	2		T137	5		T140	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T9	12		T39	15		T133	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22089

1

T1

3

T2

27

T3

3

auto[1]

auto[0]

4366

1

T5

6

T8

4

T9

12