Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26455

1

T1

3

T2

27

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22795

1

T1

1

T2

17

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3660

1

T1

2

T2

10

T3

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20278

1

T2

4

T4

20

T5

7

auto[1]

6177

1

T1

3

T2

23

T3

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22301

1

T1

3

T2

3

T3

3

auto[1]

4154

1

T2

24

T8

4

T9

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	390	1			T12	1		T25	7		T39	23
values[0]	1	1			T246	1		-	-		-	-
values[1]	530	1			T3	1		T9	24		T21	13
values[2]	797	1			T1	1		T3	1		T111	2
values[3]	797	1			T2	13		T136	19		T151	1
values[4]	522	1			T1	1		T2	4		T5	7
values[5]	778	1			T8	9		T39	1		T141	7
values[6]	823	1			T23	14		T25	13		T136	26
values[7]	718	1			T1	1		T34	13		T141	10
values[8]	658	1			T2	10		T3	1		T9	2
values[9]	3432	1			T10	2		T11	1		T22	14
minimum	17009	1			T4	20		T6	179		T7	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	669	1			T21	13		T111	1		T136	13
values[1]	753	1			T1	1		T2	13		T3	1
values[2]	681	1			T2	4		T136	19		T209	3
values[3]	625	1			T1	1		T5	7		T8	9
values[4]	656	1			T39	1		T141	7		T133	24
values[5]	961	1			T23	14		T25	13		T136	26
values[6]	3025	1			T1	1		T10	2		T22	14
values[7]	611	1			T2	10		T3	1		T9	2
values[8]	1157	1			T11	1		T12	1		T25	7
values[9]	196	1			T23	3		T142	8		T29	31
minimum	17121	1			T3	1		T4	20		T6	179

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22089

1

T1

3

T2

27

T3

3

auto[1]

4366

1

T5

6

T8

4

T9

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T152	5		T153	1		T154	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T21	7		T111	1		T136	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T1	1		T2	1		T152	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T3	1		T111	1		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T2	1		T136	15		T83	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T209	1		T140	6		T158	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T12	5		T39	16		T88	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T1	1		T5	7		T8	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T39	1		T141	7		T133	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T134	13		T84	1		T159	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T23	14		T25	1		T134	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T136	14		T140	20		T247	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1637	1			T10	2		T22	14		T167	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T1	1		T34	7		T210	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T3	1		T143	1		T160	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T2	1		T9	1		T137	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	360	1			T25	1		T39	13		T33	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T11	1		T12	1		T133	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T23	3		T142	8		T225	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T29	18		T83	15		T147	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16889	1			T4	20		T6	179		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T3	1		T144	1		T102	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T152	10		T72	7		T219	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T21	6		T136	10		T82	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T2	12		T152	6		T35	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T208	9		T183	9		T72	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T2	3		T136	4		T83	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T209	2		T158	7		T159	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T12	1		T39	5		T233	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T8	4		T14	2		T170	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T133	12		T29	2		T208	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T134	12		T84	5		T159	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T25	12		T134	14		T208	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T136	12		T140	18		T146	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	964	1			T167	19		T220	19		T150	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T34	6		T152	8		T139	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T143	12		T160	3		T77	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T2	9		T9	1		T36	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T25	6		T39	10		T134	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T133	2		T140	8		T84	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T248	13		T249	11		T250	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T29	13		T187	8		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T9	11		T33	2		T29	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T102	12		T251	1		T252	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T25	1		T39	13		T33	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T12	1		T133	3		T83	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T246	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T9	13		T152	5		T13	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T3	1		T21	7		T82	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T1	1		T152	8		T35	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T3	1		T111	2		T136	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T2	1		T136	15		T83	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T151	1		T209	1		T140	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T2	1		T12	5		T39	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T1	1		T5	7		T23	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T39	1		T141	7		T133	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T8	5		T134	13		T140	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T23	14		T25	1		T134	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T136	14		T247	1		T14	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T141	10		T138	1		T139	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T1	1		T34	7		T158	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T3	1		T143	1		T160	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T2	1		T9	1		T137	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1790	1			T10	2		T22	14		T23	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T11	1		T29	18		T140	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16860	1			T4	20		T6	179		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T25	6		T39	10		T159	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T133	2		T253	12		T254	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T9	11		T152	10		T72	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T21	6		T82	2		T161	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T152	6		T35	1		T233	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T136	10		T208	9		T183	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T2	12		T136	4		T83	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T209	2		T158	7		T159	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T2	3		T12	1		T39	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T14	2		T170	2		T148	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T133	12		T13	1		T233	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T8	4		T134	12		T140	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T25	12		T134	14		T29	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T136	12		T146	12		T170	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T170	2		T175	9		T255	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T34	6		T158	8		T233	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T143	12		T160	3		T77	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T2	9		T9	1		T152	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1162	1			T167	19		T134	16		T220	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T29	13		T140	8		T84	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T33	2		T29	2		T13	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T152	11		T153	1		T154	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T21	10		T111	1		T136	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T1	1		T2	13		T152	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T3	1		T111	1		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T2	4		T136	5		T83	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T209	3		T140	1		T158	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T12	4		T39	6		T88	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T1	1		T5	1		T8	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T39	1		T141	1		T133	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T134	13		T84	6		T159	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T23	1		T25	13		T134	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T136	13		T140	19		T247	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1301	1			T10	2		T22	1		T167	21
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T1	1		T34	9		T210	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T3	1		T143	13		T160	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T2	10		T9	2		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	354	1			T25	7		T39	11		T33	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T11	1		T12	1		T133	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T23	1		T142	1		T225	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T29	14		T83	1		T147	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17034	1			T4	20		T6	179		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T3	1		T144	1		T102	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T152	4		T72	7		T38	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T21	3		T136	2		T179	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T152	7		T211	1		T243	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T137	5		T72	24		T37	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T136	14		T83	13		T162	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T140	5		T158	7		T159	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T12	2		T39	15		T180	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T5	6		T8	4		T23	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T141	6		T133	11		T38	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T134	12		T159	10		T78	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T23	13		T134	14		T139	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T136	13		T140	19		T170	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1300	1			T22	13		T135	34		T141	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T34	4		T152	7		T139	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T160	13		T77	10		T256	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T137	11		T36	1		T174	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T39	12		T134	11		T137	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T133	2		T140	10		T86	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T23	2		T142	7		T225	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T29	17		T83	14		T147	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T9	12		T245	10		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T252	9		T18	4		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T25	7		T39	11		T33	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T12	1		T133	3		T83	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T246	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T9	12		T152	11		T13	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T3	1		T21	10		T82	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T1	1		T152	7		T35	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T3	1		T111	2		T136	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T2	13		T136	5		T83	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T151	1		T209	3		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T2	4		T12	4		T39	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T1	1		T5	1		T23	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T39	1		T141	1		T133	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T8	5		T134	13		T140	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T23	1		T25	13		T134	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T136	13		T247	1		T14	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T141	1		T138	1		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T1	1		T34	9		T158	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T3	1		T143	13		T160	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T2	10		T9	2		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1526	1			T10	2		T22	1		T23	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T11	1		T29	14		T140	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17009	1			T4	20		T6	179		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T39	12		T159	7		T248	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T133	2		T83	14		T147	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T9	12		T152	4		T72	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T21	3		T179	6		T257	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T152	7		T211	1		T243	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T136	2		T137	5		T72	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T136	14		T83	13		T162	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T140	5		T158	7		T159	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T12	2		T39	15		T231	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T5	6		T23	13		T14	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T141	6		T133	11		T180	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T8	4		T134	12		T140	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T23	13		T134	14		T35	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T136	13		T170	13		T222	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T141	9		T139	12		T258	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T34	4		T158	9		T146	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T160	13		T77	10		T259	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T137	11		T152	7		T139	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1426	1			T22	13		T23	2		T135	34
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T29	17		T140	10		T86	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22089

1

T1

3

T2

27

T3

3

auto[1]

auto[0]

4366

1

T5

6

T8

4

T9

12