Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26455

1

T1

3

T2

27

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22934

1

T1

1

T2

4

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3521

1

T1

2

T2

23

T3

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20384

1

T1

2

T2

4

T3

1

auto[1]

6071

1

T1

1

T2

23

T3

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22301

1

T1

3

T2

3

T3

3

auto[1]

4154

1

T2

24

T8

4

T9

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	16	1			T197	4		T260	12		-	-
values[0]	81	1			T82	8		T84	6		T261	28
values[1]	787	1			T1	1		T2	4		T34	1
values[2]	2961	1			T10	2		T11	1		T22	14
values[3]	597	1			T2	13		T9	2		T39	1
values[4]	805	1			T9	24		T23	28		T134	29
values[5]	688	1			T3	1		T8	9		T33	6
values[6]	741	1			T1	1		T3	1		T23	3
values[7]	777	1			T2	10		T39	44		T134	28
values[8]	566	1			T3	1		T5	7		T12	6
values[9]	1427	1			T1	1		T12	1		T25	20
minimum	17009	1			T4	20		T6	179		T7	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1008	1			T1	1		T2	4		T34	1
values[1]	2955	1			T2	13		T10	2		T22	14
values[2]	675	1			T9	2		T11	1		T23	14
values[3]	667	1			T9	24		T23	14		T33	6
values[4]	727	1			T3	1		T8	9		T23	3
values[5]	908	1			T1	1		T2	10		T3	1
values[6]	626	1			T5	7		T21	13		T136	13
values[7]	721	1			T3	1		T12	6		T25	13
values[8]	906	1			T1	1		T12	1		T25	7
values[9]	246	1			T38	6		T215	11		T107	16
minimum	17016	1			T4	20		T6	179		T7	14

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22089

1

T1

3

T2

27

T3

3

auto[1]

4366

1

T5

6

T8

4

T9

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	326	1			T2	1		T34	1		T136	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T1	1		T134	13		T139	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1654	1			T10	2		T22	14		T39	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T2	1		T210	1		T152	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T9	1		T23	14		T34	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T11	1		T29	18		T208	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T9	13		T214	3		T168	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T23	14		T33	6		T152	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T8	5		T23	3		T133	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T3	1		T111	1		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T39	29		T141	7		T111	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T1	1		T2	1		T3	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T5	7		T140	11		T13	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T21	7		T136	3		T205	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T3	1		T84	1		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T12	5		T25	1		T137	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T1	1		T12	1		T141	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T25	1		T137	6		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T107	8		T262	10		T263	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T38	5		T215	1		T256	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16860	1			T4	20		T6	179		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T91	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T2	3		T136	12		T209	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T134	12		T139	9		T13	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1027	1			T167	19		T133	2		T29	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T2	12		T152	10		T36	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T9	1		T34	6		T35	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T29	13		T208	9		T158	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T9	11		T214	4		T170	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T152	8		T219	11		T38	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T8	4		T133	12		T86	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T134	14		T233	12		T211	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T39	15		T136	4		T134	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T2	9		T35	10		T160	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T140	8		T158	7		T183	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T21	6		T136	10		T230	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T84	5		T77	1		T146	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T12	1		T25	12		T208	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T152	6		T162	10		T148	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T25	6		T86	12		T233	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T107	8		T263	7		T264	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T38	1		T215	10		T176	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T33	2		T29	2		T13	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T91	2		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T197	3		T260	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T84	1		T261	15		T93	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T82	1		T265	8		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T2	1		T34	1		T136	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T1	1		T134	13		T152	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1665	1			T10	2		T22	14		T34	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T11	1		T36	4		T240	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T9	1		T39	1		T83	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T2	1		T29	18		T210	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T9	13		T23	14		T35	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T23	14		T134	15		T140	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T8	5		T133	12		T86	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T3	1		T33	6		T111	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T23	3		T141	7		T111	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T1	1		T3	1		T142	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T39	29		T134	12		T139	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T2	1		T88	1		T160	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T3	1		T5	7		T84	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T12	5		T21	7		T137	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T1	1		T12	1		T141	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	468	1			T25	2		T137	6		T140	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16860	1			T4	20		T6	179		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T197	1		T260	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T84	5		T261	13		T93	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T82	7		T265	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T2	3		T136	12		T209	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T134	12		T152	10		T139	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1042	1			T34	6		T167	19		T133	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T36	1		T146	10		T89	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T9	1		T223	12		T14	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T2	12		T29	13		T208	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T9	11		T35	1		T83	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T134	14		T219	11		T107	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T8	4		T133	12		T86	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T152	8		T35	10		T38	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T136	4		T158	8		T183	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T136	10		T233	12		T72	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T39	15		T134	16		T140	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T2	9		T160	10		T78	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T84	5		T77	1		T156	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T12	1		T21	6		T208	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T152	6		T107	8		T162	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	409	1			T25	18		T140	18		T82	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T33	2		T29	2		T13	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	331	1			T2	4		T34	1		T136	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T1	1		T134	13		T139	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1368	1			T10	2		T22	1		T39	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T2	13		T210	1		T152	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T9	2		T23	1		T34	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T11	1		T29	14		T208	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T9	12		T214	5		T168	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T23	1		T33	6		T152	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T8	5		T23	1		T133	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T3	1		T111	1		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T39	17		T141	1		T111	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T1	1		T2	10		T3	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T5	1		T140	9		T13	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T21	10		T136	11		T205	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T3	1		T84	6		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T12	4		T25	13		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T1	1		T12	1		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	343	1			T25	7		T137	1		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T107	9		T262	1		T263	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T38	5		T215	11		T256	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17009	1			T4	20		T6	179		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T91	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T136	13		T35	7		T72	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T134	12		T139	5		T146	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1313	1			T22	13		T135	34		T133	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T152	4		T36	1		T78	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T23	13		T34	4		T83	27
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T29	17		T158	8		T266	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T9	12		T214	2		T168	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T23	13		T152	7		T140	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T8	4		T23	2		T133	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T134	14		T211	1		T169	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T39	27		T141	6		T136	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T142	7		T35	9		T160	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T5	6		T140	10		T158	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T21	3		T136	2		T78	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T168	12		T146	10		T267	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T12	2		T137	11		T140	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T141	9		T152	7		T162	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T137	5		T86	13		T160	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T107	7		T262	9		T263	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T38	1		T256	5		T176	16

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T197	3		T260	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T84	6		T261	14		T93	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T82	8		T265	5		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T2	4		T34	1		T136	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T1	1		T134	13		T152	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1388	1			T10	2		T22	1		T34	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T11	1		T36	4		T240	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T9	2		T39	1		T83	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T2	13		T29	14		T210	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T9	12		T23	1		T35	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T23	1		T134	15		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T8	5		T133	13		T86	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T3	1		T33	6		T111	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T23	1		T141	1		T111	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T1	1		T3	1		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T39	17		T134	17		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T2	10		T88	1		T160	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T3	1		T5	1		T84	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T12	4		T21	10		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	324	1			T1	1		T12	1		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	499	1			T25	20		T137	1		T140	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17009	1			T4	20		T6	179		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T197	1		T260	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T261	14		T268	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T265	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T136	13		T35	7		T72	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T134	12		T152	4		T139	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1319	1			T22	13		T34	4		T135	34
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T36	1		T240	11		T146	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T83	14		T223	14		T168	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T29	17		T158	8		T78	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T9	12		T23	13		T83	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T23	13		T134	14		T140	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T8	4		T133	11		T86	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T152	7		T35	9		T38	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T23	2		T141	6		T136	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T142	7		T136	2		T72	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T39	27		T134	11		T139	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T160	11		T258	11		T78	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T5	6		T168	12		T267	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T12	2		T21	3		T137	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T141	9		T152	7		T107	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	378	1			T137	5		T140	19		T86	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22089

1

T1

3

T2

27

T3

3

auto[1]

auto[0]

4366

1

T5

6

T8

4

T9

12